WebSVN – Kolibri OS – Blame – /kernel/branches/kolibri-ahci/blkdev/ahci.inc

Rev	Author	Line No.	Line
9020	rgimad	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
		4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		7
		8	$Revision$
		9
		10	PCI_REG_STATUS_COMMAND = 0x0004
		11	PCI_REG_BAR5 = 0x0024
		12
9023	rgimad	13	; bit_ prefix means that its index of bit
		14	; format: bit_AHCI_STR_REG_BIT
		15	bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff
9020	rgimad	16
9023	rgimad	17	bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
		18	bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
		19	bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
9020	rgimad	20
9023	rgimad	21	bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode
		22	bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA
		23	bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA
		24
9065	rgimad	25	bit_AHCI_HBA_PxCMD_ST = 0
		26	bit_AHCI_HBA_PxCMD_FRE = 4
		27	bit_AHCI_HBA_PxCMD_FR = 14
		28	bit_AHCI_HBA_PxCMD_CR = 15
		29
9037	rgimad	30	AHCI_HBA_PxSSTS_DET = 0xF
		31	AHCI_HBA_PORT_IPM_ACTIVE = 1
		32	AHCI_HBA_PxSSTS_DET_PRESENT = 3
		33
9023	rgimad	34	AHCI_MAX_PORTS = 32 ;
9064	rgimad	35	;HBA_MEMORY_SIZE = 0x1100
9020	rgimad	36
9064	rgimad	37	; Frame Information Structure Types
		38	FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device
		39	FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host
		40	FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host
		41	FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional
		42	FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional
		43	FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional
		44	FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host
		45	FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host
		46
9020	rgimad	47	struct AHCI_DATA
		48	abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
		49	pcidev dd ? ; pointer to corresponding PCIDEV structure
		50	ends
		51
		52	; Generic Host Control registers
		53	struct HBA_MEM
9064	rgimad	54	cap dd ? ; 0x00, Host capabilities
		55	ghc dd ? ; 0x04, Global host control
		56	is dd ? ; 0x08, Interrupt status
		57	pi dd ? ; 0x0C, Port implemented
		58	version dd ? ; 0x10, Version
9020	rgimad	59	ccc_ctl dd ? ; 0x14, Command completion coalescing control
		60	ccc_pts dd ? ; 0x18, Command completion coalescing ports
		61	em_loc dd ? ; 0x1C, Enclosure management location
		62	em_ctl dd ? ; 0x20, Enclosure management control
9064	rgimad	63	cap2 dd ? ; 0x24, Host capabilities extended
9020	rgimad	64	bohc dd ? ; 0x28, BIOS/OS handoff control and status
		65	reserved rb (0xA0-0x2C) ; 0x2C - 0x9F, Reserved
		66	vendor rb (0x100-0xA0) ; 0xA0 - 0xFF, Vendor specific
9023	rgimad	67	ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS
9020	rgimad	68	ends
		69
		70	; Port Control registers
		71	struct HBA_PORT
9064	rgimad	72	command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
		73	command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
		74	fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
		75	fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
		76	interrupt_status dd ? ; 0x10
		77	interrupt_enable dd ? ; 0x14
		78	command dd ? ; 0x18, command and status
		79	reserved0 dd ? ; 0x1C
		80	task_file_data dd ? ; 0x20
		81	signature dd ? ; 0x24
		82	sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
		83	sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
		84	sata_error dd ? ; 0x30, SATA error (SCR1:SError)
		85	sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
		86	command_issue dd ? ; 0x38
		87	sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
		88	fis_based_switch_control dd ? ; 0x40
		89	reserved1 rd 11 ; 0x44 - 0x6F
		90	vendor rd 4 ; 0x70 - 0x7F, vendor specific
9020	rgimad	91	ends
		92
9068	rgimad	93	; Command header structure
		94	struct HBA_CMD_HDR
		95	_flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H)
		96	; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16
		97
		98	_flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved,
		99	; C - Clear busy upon R_OK, B - BIST, Re - Reset
		100
		101	prdtl dw ? ; Physical region descriptor table length in entries
		102	prdbc dd ? ; Physical region descriptor byte count transferred
		103	ctba dd ? ; Command table descriptor base address
		104	ctbau dd ? ; Command table descriptor base address upper 32 bits
		105	rsv1 rd 4 ; Reserved
		106	ends
		107
		108	; Contains virtual mappings for port phys memory regions
		109	struct PORT_DATA
		110	clb dd ? ; Command list base
		111	fb dd ? ; FIS base
		112	ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on.
		113	port dd ? ; address of correspoding HBA_PORT structure
		114	ends
		115
9064	rgimad	116	; Register FIS – Host to Device
		117	struct FIS_REG_H2D
		118	fis_type db ? ; FIS_TYPE_REG_H2D
		119	_flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control
		120	; R - Reserved, P - Port multiplier
		121
		122	command db ? ; Command register
		123	featurel db ? ; Feature register, 7:0
		124
		125	lba0 db ? ; LBA low register, 7:0
		126	lba1 db ? ; LBA mid register, 15:8
		127	lba2 db ? ; LBA high register, 23:16
		128	device db ? ; Device register
		129
		130	lba3 db ? ; LBA register, 31:24
		131	lba4 db ? ; LBA register, 39:32
		132	lba5 db ? ; LBA register, 47:40
		133	featureh db ? ; Feature register, 15:8
		134
		135	countl db ? ; Count register, 7:0
		136	counth db ? ; Count register, 15:8
		137	icc db ? ; Isochronous command completion
		138	control db ? ; Control register
		139
		140	rsv1 rb 4 ; Reserved
		141	ends
		142
		143	; Register FIS – Device to Host
		144	struct FIS_REG_D2H
		145	fis_type db ? ; FIS_TYPE_REG_D2H
		146
		147	_flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved
		148	; I - Interrupt bit
		149
		150	status db ? ; Status register
		151	error db ? ; Error register
		152
		153	lba0 db ? ; LBA low register, 7:0
		154	lba1 db ? ; LBA mid register, 15:8
		155	lba2 db ? ; LBA high register, 23:16
		156	device db ? ; Device register
		157
		158	lba3 db ? ; LBA register, 31:24
		159	lba4 db ? ; LBA register, 39:32
		160	lba5 db ? ; LBA register, 47:40
		161	rsv2 db ? ; Reserved
		162
		163	countl db ? ; Count register, 7:0
		164	counth db ? ; Count register, 15:8
		165	rsv3 rb 2 ; Reserved
		166
		167	rsv4 rb 4 ; Reserved
		168	ends
		169
		170	; Data FIS – Bidirectional
		171	struct FIS_DATA
		172	fis_type db ? ; FIS_TYPE_DATA
		173	_flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier
		174	rsv1 rb 2 ; Reserved
		175	; DWORD 1 ~ N (?)
		176	data rd 1 ; Payload
		177	ends
		178
		179	; PIO Setup – Device to Host
		180	struct FIS_PIO_SETUP
		181	fis_type db ? ; FIS_TYPE_PIO_SETUP
		182
		183	_flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved
		184	; I - Interrupt bit, D - Data transfer direction, 1 - device to host
		185
		186	status db ? ; Status register
		187	error db ? ; Error register
		188
		189	lba0 db ? ; LBA low register, 7:0
		190	lba1 db ? ; LBA mid register, 15:8
		191	lba2 db ? ; LBA high register, 23:16
		192	device db ? ; Device register
		193
		194	lba3 db ? ; LBA register, 31:24
		195	lba4 db ? ; LBA register, 39:32
		196	lba5 db ? ; LBA register, 47:40
		197	rsv2 db ? ; Reserved
		198
		199	countl db ? ; Count register, 7:0
		200	counth db ? ; Count register, 15:8
		201	rsv3 db ? ; Reserved
		202	e_status db ? ; New value of status register
		203
		204	tc dw ? ; Transfer count
		205	rsv4 rb 2 ; Reserved
		206	ends
		207
		208	; DMA Setup – Device to Host
		209	struct FIS_DMA_SETUP
		210	fis_type db ? ; FIS_TYPE_DMA_SETUP
		211	_flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed,
		212	; I - Interrupt bit, D - Data transfer direction, 1 - device to host,
		213	; R - Reserved, P - Port multiplier
		214
		215	rsved rb 2 ; Reserved
		216	DMAbufferID dq ? ; DMA Buffer Identifier.
		217	; Used to Identify DMA buffer in host memory.
		218	; SATA Spec says host specific and not in Spec.
		219	; Trying AHCI spec might work.
		220
		221	TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0
		222	resvd dd ? ; Reserved
		223	ends
		224
		225	; Set device bits FIS - device to host
		226	struct FIS_DEV_BITS
		227	fis_type db ? ; FIS_TYPE_DEV_BITS
		228	_flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt,
		229	; R - Reserved, P - Port multiplier
		230
		231	status db ? ; Status register
		232	error db ? ; Error register
		233
		234	protocol dd ? ; Protocol
		235	ends
		236
		237	; --------------------------------------------------
9020	rgimad	238	uglobal
		239	align 4
		240	ahci_controller AHCI_DATA
9068	rgimad	241	port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS)
9020	rgimad	242	endg
		243
9064	rgimad	244	; -----------------------------------------------------------------------
9020	rgimad	245	; detect ahci controller and initialize
		246	align 4
9068	rgimad	247	ahci_init:
9020	rgimad	248	mov ecx, ahci_controller
		249	mov esi, pcidev_list
		250	.find_ahci_ctr:
		251	mov esi, [esi + PCIDEV.fd]
		252	cmp esi, pcidev_list
		253	jz .ahci_ctr_not_found
		254	mov eax, [esi + PCIDEV.class]
		255	;DEBUGF 1, "K: device class = %x\n", eax
		256	shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
		257	cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
		258	jz .ahci_ctr_found
		259	jmp .find_ahci_ctr
		260
		261	.ahci_ctr_not_found:
		262	DEBUGF 1, "K: AHCI controller not found\n"
		263	ret
		264
		265	.ahci_ctr_found:
		266	mov [ahci_controller + AHCI_DATA.pcidev], esi
		267
		268	mov eax, [esi+PCIDEV.class]
		269	movzx ebx, byte [esi+PCIDEV.bus]
		270	movzx ecx, byte [esi+PCIDEV.devfn]
		271	shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
		272	movzx edx, byte [esi+PCIDEV.devfn]
		273	and edx, 00000111b ; get only 3 lowest bits (function code)
		274	DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
		275
9023	rgimad	276	; get BAR5 value, it is physical address
9037	rgimad	277	movzx ebx, [esi + PCIDEV.bus]
		278	movzx ebp, [esi + PCIDEV.devfn]
		279	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		280	DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax
		281	mov edi, eax
9020	rgimad	282
9037	rgimad	283	; get the size of MMIO region
		284	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF
		285	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		286	not eax
		287	inc eax
		288	DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax
		289
		290	; Map MMIO region to virtual memory
		291	stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE
9020	rgimad	292	mov [ahci_controller + AHCI_DATA.abar], eax
		293	DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
		294
9037	rgimad	295	; Restore the original BAR5 value
		296	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi
		297
9023	rgimad	298	; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit
		299	; Usually, it is already done before us
9024	rgimad	300	movzx ebx, [esi + PCIDEV.bus]
		301	movzx ebp, [esi + PCIDEV.devfn]
		302	stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND
9020	rgimad	303	DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
		304	or eax, 0x06 ; pci.command \|= 0x06 (dma bus mastering + memory space access)
		305	btr eax, 10 ; clear the "disable interrupts" bit
		306	DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
9024	rgimad	307	stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax
9020	rgimad	308
9023	rgimad	309	; ; Print some register values to debug board
		310	; mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	311	; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version]
9020	rgimad	312
9023	rgimad	313	;-------------------------------------------------------
		314	; Request BIOS/OS ownership handoff, if supported. (TODO check correctness)
		315	mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	316	;mov ebx, [esi + HBA_MEM.cap2]
9023	rgimad	317	;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
9064	rgimad	318	bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH
9020	rgimad	319	jnc .end_handoff
9023	rgimad	320	DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n"
9024	rgimad	321	bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS
9020	rgimad	322
		323	.wait_not_bos:
9024	rgimad	324	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS
9020	rgimad	325	jc .wait_not_bos
		326
		327	mov ebx, 3
		328	call delay_hs
		329
9023	rgimad	330	; if Bios Busy is still set after 30 mS, wait 2 seconds.
9024	rgimad	331	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB
9020	rgimad	332	jnc @f
		333
		334	mov ebx, 200
		335	call delay_hs
		336	@@:
9023	rgimad	337	DEBUGF 1, "K: AHCI: ownership change completed.\n"
9020	rgimad	338
		339	.end_handoff:
9023	rgimad	340	;-------------------------------------------------------
9020	rgimad	341
9023	rgimad	342	; enable the AHCI and reset it
9064	rgimad	343	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		344	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9020	rgimad	345
9023	rgimad	346	; wait for reset to complete
		347	.wait_reset:
9064	rgimad	348	bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9023	rgimad	349	jc .wait_reset
9020	rgimad	350
9023	rgimad	351	; enable the AHCI and interrupts
9064	rgimad	352	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		353	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE
9023	rgimad	354	mov ebx, 2
		355	call delay_hs
		356
9064	rgimad	357	DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi]
9020	rgimad	358
9037	rgimad	359	; TODO:
		360	; calculate irq line
		361	; ahciHBA->ghc \|= AHCI_GHC_IE;
		362	; IDT::RegisterInterruptHandler(irq, InterruptHandler);
9064	rgimad	363	; ahciHBA->is = 0xffffffff;
9037	rgimad	364
		365	xor ebx, ebx
		366	.detect_drives:
		367	cmp ebx, AHCI_MAX_PORTS
		368	jae .end_detect_drives
		369
		370	; if port with index ebx is not implemented then go to next
9064	rgimad	371	mov ecx, [esi + HBA_MEM.pi]
9037	rgimad	372	bt ecx, ebx
		373	jnc .continue_detect_drives
		374
		375	mov edi, ebx
		376	shl edi, BSF sizeof.HBA_PORT
		377	add edi, HBA_MEM.ports
		378	add edi, esi
		379	; now edi - base of HBA_MEM.ports[ebx]
		380
		381	DEBUGF 1, "K: AHCI: port %d, ssts = %x\n", ebx, [edi + HBA_PORT.sata_status]
		382
		383	mov ecx, [edi + HBA_PORT.sata_status]
		384	shr ecx, 8
		385	and ecx, 0x0F
		386	cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE
		387	jne .continue_detect_drives
		388
		389	mov ecx, [edi + HBA_PORT.sata_status]
		390	and ecx, AHCI_HBA_PxSSTS_DET
		391	cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT
9068	rgimad	392	jne .continue_detect_drives
9037	rgimad	393
9068	rgimad	394	DEBUGF 1, "K: AHCI: found drive at port %d, signature = %x\n", ebx, [edi + HBA_PORT.signature]
9037	rgimad	395
9068	rgimad	396	mov ecx, ebx
		397	shl ecx, BSF sizeof.PORT_DATA
		398	add ecx, port_data_arr
		399	stdcall ahci_port_rebase, edi, ebx, ecx
		400
9037	rgimad	401	.continue_detect_drives:
		402	inc ebx
		403	jmp .detect_drives
		404
9064	rgimad	405
9037	rgimad	406
		407	.end_detect_drives:
		408
		409
9020	rgimad	410	ret
9065	rgimad	411	; -------------------------------------------------
9020	rgimad	412
9065	rgimad	413	; Start command engine
		414	; in: eax - address of HBA_PORT structure
9068	rgimad	415	ahci_start_cmd:
9065	rgimad	416	.wait_cr: ; Wait until CR (bit15) is cleared
		417	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		418	jc .wait_cr
		419
		420	; Set FRE (bit4) and ST (bit0)
		421	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE
		422	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST
9068	rgimad	423	; maybe here call ahci flush cmd ? TODO (see seakernel)
9065	rgimad	424	ret
		425
		426	; Stop command engine
		427	; in: eax - address of HBA_PORT structure
9068	rgimad	428	ahci_stop_cmd:
9065	rgimad	429	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0)
		430	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4)
		431	.wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared
		432	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR
		433	jc .wait_fr_cr
		434	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		435	jc .wait_fr_cr
		436
		437	ret
		438
9068	rgimad	439	; The commands may not take effect until the command
		440	; register is read again by software, because reasons.
		441	; in: eax - address of HBA_PORT structure
		442	; out: eax - command register value
		443	ahci_flush_cmd:
		444	mov eax, [eax + HBA_PORT.command]
		445	ret
9065	rgimad	446
9068	rgimad	447	; Send command to port
		448	; in: eax - address of HBA_PORT structure
		449	; ebx - index of command slot
		450	ahci_send_cmd:
		451	push ecx
		452	mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF
		453
		454	mov cl, bl
		455	mov [eax + HBA_PORT.command_issue], 1
		456	shl [eax + HBA_PORT.command_issue], cl
9065	rgimad	457
9068	rgimad	458	call ahci_flush_cmd
		459	pop ecx
		460	ret
9065	rgimad	461
9068	rgimad	462	; ---------------------------------------------------------------------------
		463	; TODO: check correctness
		464	; in: port - address of HBA_PORT structure
		465	; portno - port index (0..31)
		466	; pdata - address of PORT_DATA structure
		467	proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword
		468	locals
		469	phys_page1 dd ?
		470	virt_page1 dd ?
		471	phys_page23 dd ?
		472	virt_page23 dd ?
		473	tmp dd ?
		474	endl
		475
		476	pushad
		477
		478	DEBUGF 1, "Rebasing port %u\n", [portno]
		479
		480	mov eax, [port]
		481	call ahci_stop_cmd
		482
		483	; Command list entry size = 32
		484	; Command list entry maxim count = 32
		485	; Command list maxim size = 32*32 = 1K per port
		486	call alloc_page
		487	mov [phys_page1], eax
		488
		489	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		490	mov [virt_page1], eax
		491
		492	mov esi, [port]
		493	mov ebx, [phys_page1]
		494	mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base
		495	mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os
		496
		497	mov edi, [pdata]
		498	mov ebx, [virt_page1]
		499	mov [edi + PORT_DATA.clb], ebx ; set pdata->clb
		500
		501	mov eax, [port]
		502	mov [edi + PORT_DATA.port], eax ; set pdata->port
		503
		504	stdcall _memset, ebx, 0, 1024 ; zero out the command list
		505
		506	; FIS entry size = 256 bytes per port
		507	mov eax, [phys_page1]
		508	add eax, 1024
		509	mov [esi + HBA_PORT.fis_base_l], eax
		510	mov [esi + HBA_PORT.fis_base_h], 0
		511
		512	mov eax, [virt_page1]
		513	add eax, 1024
		514	mov [edi + PORT_DATA.fb], eax ; set pdata->fb
		515	stdcall _memset, eax, 0, 256 ; zero out
		516
		517	stdcall alloc_pages, 2
		518	mov [phys_page23], eax
		519	stdcall map_io_mem, eax, 2*4096, PG_NOCACHE + PG_SWR
		520	mov [virt_page23], eax
		521
		522	; Command table size = 256*32 = 8K per port
		523	mov edx, [edi + PORT_DATA.clb] ; cmdheader array base
		524	xor ecx, ecx
		525
		526	.for1:
		527	cmp ecx, 32
		528	jae .for1_end
		529
		530	mov ebx, ecx
		531	shl ebx, BSF sizeof.HBA_CMD_HDR
		532	add ebx, edx ; ebx = cmdheader[ecx]
		533
		534	mov [ebx + HBA_CMD_HDR.prdtl], 8 ; 8 prdt entries per command table
		535
		536	; 256 bytes per command table, 64+16+48+16*8
		537
		538	push edx
		539
		540	; cmdheader[ecx].ctba = phys_page23 + ecx*256
		541	mov [ebx + HBA_CMD_HDR.ctba], ecx
		542	shl [ebx + HBA_CMD_HDR.ctba], BSF 256 ; *= 256
		543	mov eax, [ebx + HBA_CMD_HDR.ctba]
		544	mov edx, [phys_page23]
		545	add [ebx + HBA_CMD_HDR.ctba], edx
		546
		547	add eax, [virt_page23]
		548	mov [tmp], eax ; tmp = virt_page23 + ecx*256
		549	mov eax, ecx
		550	shl eax, BSF 4 ; *= 4
		551	add eax, PORT_DATA.ctba_arr
		552	add eax, edi ; eax = pdata->ctba_arr[ecx]
		553	mov edx, [tmp]
		554	mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*256
		555
		556	pop edx
		557
		558	mov [ebx + HBA_CMD_HDR.ctbau], 0
		559	stdcall _memset, [eax], 0, 256 ; zero out
		560
		561	inc ecx
		562	jmp .for1
		563	.for1_end:
		564
		565	mov eax, [port]
		566	call ahci_start_cmd
		567
		568	DEBUGF 1, "End rebasing port %u\n", [portno]
		569	popad
		570	ret
		571	endp
		572
		573
		574
		575	proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers
		576	;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt]
		577	push eax ecx edi
		578	mov edi, dword [dest]
		579	mov al, byte [val]
		580	mov ecx, dword [cnt]
		581	rep stosb
		582	pop edi ecx eax
		583	ret
		584	endp

Subversion Repositories Kolibri OS

(root)/kernel/branches/kolibri-ahci/blkdev/ahci.inc @ 9417 – Rev 9068