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9020 | rgimad | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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7 | |||
8 | $Revision$ |
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9 | |||
10 | PCI_REG_STATUS_COMMAND = 0x0004 |
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11 | PCI_REG_BAR5 = 0x0024 |
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12 | |||
9023 | rgimad | 13 | ; bit_ prefix means that its index of bit |
14 | ; format: bit_AHCI_STR_REG_BIT |
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15 | bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff |
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9020 | rgimad | 16 | |
9023 | rgimad | 17 | bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller) |
18 | bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller) |
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19 | bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up |
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9020 | rgimad | 20 | |
9023 | rgimad | 21 | bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode |
22 | bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA |
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23 | bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA |
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24 | |||
25 | AHCI_MAX_PORTS = 32 ; |
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9020 | rgimad | 26 | HBA_MEMORY_SIZE = 0x1100 |
27 | |||
28 | struct AHCI_DATA |
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29 | ;; |
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30 | abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory |
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31 | pcidev dd ? ; pointer to corresponding PCIDEV structure |
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32 | ends |
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33 | |||
34 | ; Generic Host Control registers |
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35 | struct HBA_MEM |
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36 | capability dd ? ; 0x00 |
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37 | global_host_control dd ? ; 0x04 |
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38 | interrupt_status dd ? ; 0x08 |
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39 | port_implemented dd ? ; 0x0C |
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40 | version dd ? ; 0x10 |
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41 | ccc_ctl dd ? ; 0x14, Command completion coalescing control |
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42 | ccc_pts dd ? ; 0x18, Command completion coalescing ports |
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43 | em_loc dd ? ; 0x1C, Enclosure management location |
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44 | em_ctl dd ? ; 0x20, Enclosure management control |
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45 | capability2 dd ? ; 0x24, Host capabilities extended |
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46 | bohc dd ? ; 0x28, BIOS/OS handoff control and status |
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47 | reserved rb (0xA0-0x2C) ; 0x2C - 0x9F, Reserved |
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48 | vendor rb (0x100-0xA0) ; 0xA0 - 0xFF, Vendor specific |
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9023 | rgimad | 49 | ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS |
9020 | rgimad | 50 | ends |
51 | |||
52 | ; Port Control registers |
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53 | struct HBA_PORT |
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54 | command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned |
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55 | command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems |
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56 | fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned |
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57 | fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems |
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58 | interrupt_status dd ? ; 0x10 |
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59 | interrupt_enable dd ? ; 0x14 |
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60 | command dd ? ; 0x18, command and status |
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61 | reserved0 dd ? ; 0x1C |
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62 | task_file_data dd ? ; 0x20 |
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63 | signature dd ? ; 0x24 |
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64 | sata_status dd ? ; 0x28, SATA status (SCR0:SStatus) |
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65 | sata_control dd ? ; 0x2C, SATA control (SCR2:SControl) |
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66 | sata_error dd ? ; 0x30, SATA error (SCR1:SError) |
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67 | sata_active dd ? ; 0x34, SATA active (SCR3:SActive) |
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68 | command_issue dd ? ; 0x38 |
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69 | sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification) |
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70 | fis_based_switch_control dd ? ; 0x40 |
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71 | reserved1 rd 11 ; 0x44 - 0x6F |
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72 | vendor rd 4 ; 0x70 - 0x7F, vendor specific |
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73 | ends |
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74 | |||
75 | uglobal |
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76 | align 4 |
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77 | ahci_controller AHCI_DATA |
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78 | endg |
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79 | |||
80 | |||
81 | ; detect ahci controller and initialize |
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82 | align 4 |
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83 | init_ahci: |
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84 | mov ecx, ahci_controller |
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85 | mov esi, pcidev_list |
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86 | .find_ahci_ctr: |
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87 | mov esi, [esi + PCIDEV.fd] |
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88 | cmp esi, pcidev_list |
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89 | jz .ahci_ctr_not_found |
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90 | mov eax, [esi + PCIDEV.class] |
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91 | ;DEBUGF 1, "K: device class = %x\n", eax |
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92 | shr eax, 8 ; shift right because lowest 8 bits if ProgIf field |
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93 | cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass |
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94 | jz .ahci_ctr_found |
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95 | jmp .find_ahci_ctr |
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96 | |||
97 | .ahci_ctr_not_found: |
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98 | DEBUGF 1, "K: AHCI controller not found\n" |
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99 | ret |
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100 | |||
101 | .ahci_ctr_found: |
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102 | mov [ahci_controller + AHCI_DATA.pcidev], esi |
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103 | |||
104 | mov eax, [esi+PCIDEV.class] |
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105 | movzx ebx, byte [esi+PCIDEV.bus] |
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106 | movzx ecx, byte [esi+PCIDEV.devfn] |
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107 | shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code |
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108 | movzx edx, byte [esi+PCIDEV.devfn] |
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109 | and edx, 00000111b ; get only 3 lowest bits (function code) |
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110 | DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx |
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111 | |||
9023 | rgimad | 112 | ; get BAR5 value, it is physical address |
9020 | rgimad | 113 | mov ah, [esi + PCIDEV.bus] |
114 | mov al, 2 ; read dword |
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115 | mov bh, [esi + PCIDEV.devfn] |
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116 | mov bl, PCI_REG_BAR5 |
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117 | call pci_read_reg |
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118 | DEBUGF 1, "K: AHCI controller BAR5 = %x\n", eax |
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119 | |||
9023 | rgimad | 120 | ; Map BAR5 to virtual memory |
9020 | rgimad | 121 | stdcall map_io_mem, eax, HBA_MEMORY_SIZE, PG_SWR + PG_NOCACHE |
122 | mov [ahci_controller + AHCI_DATA.abar], eax |
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123 | DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax |
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124 | |||
9023 | rgimad | 125 | ; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit |
126 | ; Usually, it is already done before us |
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9020 | rgimad | 127 | mov ah, [esi + PCIDEV.bus] |
128 | mov al, 2 ; read dword |
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129 | mov bh, [esi + PCIDEV.devfn] |
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130 | mov bl, PCI_REG_STATUS_COMMAND |
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131 | call pci_read_reg |
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132 | DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax |
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133 | or eax, 0x06 ; pci.command |= 0x06 (dma bus mastering + memory space access) |
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134 | btr eax, 10 ; clear the "disable interrupts" bit |
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135 | DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax |
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136 | mov ecx, eax |
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137 | mov ah, [esi + PCIDEV.bus] |
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138 | mov al, 2 ; write dword |
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139 | mov bh, [esi + PCIDEV.devfn] |
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140 | mov bl, PCI_REG_STATUS_COMMAND |
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141 | call pci_write_reg |
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142 | |||
9023 | rgimad | 143 | ; ; Print some register values to debug board |
144 | ; mov esi, [ahci_controller + AHCI_DATA.abar] |
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145 | ; mov ebx, [esi + HBA_MEM.capability] |
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146 | ; mov ecx, [esi + HBA_MEM.global_host_control] |
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147 | ; mov edx, [esi + HBA_MEM.version] |
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148 | ; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", ebx, ecx, edx |
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9020 | rgimad | 149 | |
9023 | rgimad | 150 | ;------------------------------------------------------- |
151 | ; Request BIOS/OS ownership handoff, if supported. (TODO check correctness) |
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152 | mov esi, [ahci_controller + AHCI_DATA.abar] |
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153 | ;mov ebx, [esi + HBA_MEM.capability2] |
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154 | ;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx |
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155 | bt dword [esi + HBA_MEM.capability2], bit_AHCI_HBA_CAP2_BOH |
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9020 | rgimad | 156 | jnc .end_handoff |
9023 | rgimad | 157 | DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n" |
158 | bts dword [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS |
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9020 | rgimad | 159 | |
160 | .wait_not_bos: |
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9023 | rgimad | 161 | bt dword [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS |
9020 | rgimad | 162 | jc .wait_not_bos |
163 | |||
164 | mov ebx, 3 |
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165 | call delay_hs |
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166 | |||
9023 | rgimad | 167 | ; if Bios Busy is still set after 30 mS, wait 2 seconds. |
168 | bt dword [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB |
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9020 | rgimad | 169 | jnc @f |
170 | |||
171 | mov ebx, 200 |
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172 | call delay_hs |
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173 | @@: |
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9023 | rgimad | 174 | DEBUGF 1, "K: AHCI: ownership change completed.\n" |
9020 | rgimad | 175 | |
176 | .end_handoff: |
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9023 | rgimad | 177 | ;------------------------------------------------------- |
9020 | rgimad | 178 | |
9023 | rgimad | 179 | ; enable the AHCI and reset it |
180 | bts dword [esi + HBA_MEM.global_host_control], bit_AHCI_HBA_GHC_AHCI_ENABLE |
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181 | bts dword [esi + HBA_MEM.global_host_control], bit_AHCI_HBA_GHC_RESET |
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9020 | rgimad | 182 | |
9023 | rgimad | 183 | ; wait for reset to complete |
184 | .wait_reset: |
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185 | bt dword [esi + HBA_MEM.global_host_control], bit_AHCI_HBA_GHC_RESET |
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186 | jc .wait_reset |
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9020 | rgimad | 187 | |
9023 | rgimad | 188 | ; enable the AHCI and interrupts |
189 | bts dword [esi + HBA_MEM.global_host_control], bit_AHCI_HBA_GHC_AHCI_ENABLE |
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190 | bts dword [esi + HBA_MEM.global_host_control], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE |
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191 | mov ebx, 2 |
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192 | call delay_hs |
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193 | mov ebx, [esi + HBA_MEM.capability] |
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194 | mov ecx, [esi + HBA_MEM.capability2] |
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195 | mov edx, [esi + HBA_MEM.version] |
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196 | mov edi, [esi + HBA_MEM.global_host_control] |
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197 | |||
198 | DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x\n", ebx, ecx, edx, edi |
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9020 | rgimad | 199 | |
200 | ret |
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201 |