Rev 5565 | Go to most recent revision | Details | Last modification | View Log | RSS feed
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5201 | serge | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2014. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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7 | |||
8 | $Revision: 5147 $ |
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9 | |||
10 | |||
11 | ;----------------------------------------------------------------------------- |
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12 | ; find the IDE controller in the device list |
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13 | ;----------------------------------------------------------------------------- |
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14 | mov ecx, IDE_controller_1 |
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15 | mov esi, pcidev_list |
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16 | ;-------------------------------------- |
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17 | align 4 |
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18 | .loop: |
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19 | mov esi, [esi+PCIDEV.fd] |
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20 | cmp esi, pcidev_list |
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21 | jz find_IDE_controller_done |
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22 | |||
23 | mov eax, [esi+PCIDEV.class] |
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24 | ; shr eax, 4 |
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25 | ; cmp eax, 0x01018 |
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26 | shr eax, 7 |
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27 | cmp eax, 0x010180 shr 7 |
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28 | jnz .loop |
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29 | ;-------------------------------------- |
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30 | .found: |
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31 | mov eax, [esi+PCIDEV.class] |
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32 | DEBUGF 1, 'K : IDE controller programming interface %x\n', eax |
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33 | mov [ecx+IDE_DATA.ProgrammingInterface], eax |
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34 | |||
35 | mov ah, [esi+PCIDEV.bus] |
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36 | mov al, 2 |
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37 | mov bh, [esi+PCIDEV.devfn] |
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38 | ;-------------------------------------- |
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39 | mov dx, 0x1F0 |
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40 | test byte [esi+PCIDEV.class], 1 |
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41 | jz @f |
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42 | mov bl, 0x10 |
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43 | push eax |
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44 | call pci_read_reg |
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45 | and eax, 0xFFFC |
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46 | mov edx, eax |
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47 | pop eax |
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48 | @@: |
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49 | DEBUGF 1, 'K : BAR0 IDE base addr %x\n', dx |
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50 | mov [StandardATABases], dx |
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51 | mov [ecx+IDE_DATA.BAR0_val], dx |
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52 | ;-------------------------------------- |
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53 | mov dx, 0x3F4 |
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54 | test byte [esi+PCIDEV.class], 1 |
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55 | jz @f |
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56 | mov bl, 0x14 |
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57 | push eax |
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58 | call pci_read_reg |
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59 | and eax, 0xFFFC |
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60 | mov edx, eax |
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61 | pop eax |
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62 | @@: |
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63 | DEBUGF 1, 'K : BAR1 IDE base addr %x\n', dx |
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64 | mov [ecx+IDE_DATA.BAR1_val], dx |
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65 | ;-------------------------------------- |
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66 | mov dx, 0x170 |
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67 | test byte [esi+PCIDEV.class], 4 |
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68 | jz @f |
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69 | mov bl, 0x18 |
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70 | push eax |
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71 | call pci_read_reg |
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72 | and eax, 0xFFFC |
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73 | mov edx, eax |
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74 | pop eax |
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75 | @@: |
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76 | DEBUGF 1, 'K : BAR2 IDE base addr %x\n', dx |
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77 | mov [StandardATABases+2], dx |
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78 | mov [ecx+IDE_DATA.BAR2_val], dx |
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79 | ;-------------------------------------- |
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80 | mov dx, 0x374 |
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81 | test byte [esi+PCIDEV.class], 4 |
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82 | jz @f |
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83 | mov bl, 0x1C |
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84 | push eax |
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85 | call pci_read_reg |
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86 | and eax, 0xFFFC |
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87 | mov edx, eax |
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88 | pop eax |
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89 | @@: |
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90 | DEBUGF 1, 'K : BAR3 IDE base addr %x\n', dx |
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91 | mov [ecx+IDE_DATA.BAR3_val], dx |
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92 | ;-------------------------------------- |
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93 | mov bl, 0x20 |
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94 | push eax |
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95 | call pci_read_reg |
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96 | and eax, 0xFFFC |
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97 | DEBUGF 1, 'K : BAR4 IDE controller register base addr %x\n', ax |
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98 | mov [ecx+IDE_DATA.RegsBaseAddres], ax |
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99 | pop eax |
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100 | ;-------------------------------------- |
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101 | mov bl, 0x3C |
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102 | push eax |
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103 | call pci_read_reg |
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104 | and eax, 0xFF |
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105 | DEBUGF 1, 'K : IDE Interrupt %x\n', al |
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106 | mov [ecx+IDE_DATA.Interrupt], ax |
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107 | pop eax |
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108 | |||
109 | add ecx, sizeof.IDE_DATA |
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110 | ;-------------------------------------- |
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111 | jmp .loop |
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112 | ;----------------------------------------------------------------------------- |
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113 | uglobal |
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114 | align 4 |
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115 | ;-------------------------------------- |
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116 | IDE_controller_pointer dd ? |
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117 | ;-------------------------------------- |
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118 | IDE_controller_1 IDE_DATA |
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119 | IDE_controller_2 IDE_DATA |
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120 | IDE_controller_3 IDE_DATA |
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121 | ;-------------------------------------- |
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122 | cache_ide0 IDE_CACHE |
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123 | cache_ide1 IDE_CACHE |
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124 | cache_ide2 IDE_CACHE |
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125 | cache_ide3 IDE_CACHE |
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126 | cache_ide4 IDE_CACHE |
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127 | cache_ide5 IDE_CACHE |
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128 | cache_ide6 IDE_CACHE |
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129 | cache_ide7 IDE_CACHE |
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130 | cache_ide8 IDE_CACHE |
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131 | cache_ide9 IDE_CACHE |
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132 | cache_ide10 IDE_CACHE |
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133 | cache_ide11 IDE_CACHE |
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134 | ;-------------------------------------- |
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135 | IDE_device_1 rd 2 |
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136 | IDE_device_2 rd 2 |
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137 | IDE_device_3 rd 2 |
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138 | ;-------------------------------------- |
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139 | endg |
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140 | ;----------------------------------------------------------------------------- |
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141 | ; START of initialisation IDE ATA code |
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142 | ;----------------------------------------------------------------------------- |
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143 | Init_IDE_ATA_controller: |
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144 | cmp [ecx+IDE_DATA.ProgrammingInterface], 0 |
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145 | jne @f |
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146 | |||
147 | ret |
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148 | ;-------------------------------------- |
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149 | @@: |
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150 | mov esi, boot_disabling_ide |
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151 | call boot_log |
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152 | ;-------------------------------------- |
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153 | ; Disable IDE interrupts, because the search |
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154 | ; for IDE partitions is in the PIO mode. |
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155 | ;-------------------------------------- |
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156 | .disable_IDE_interrupt: |
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157 | ; Disable interrupts in IDE controller for PIO |
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158 | mov al, 2 |
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159 | mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4 |
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160 | add dx, 2 ;0x3F6 |
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161 | out dx, al |
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162 | mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374 |
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163 | add dx, 2 ;0x376 |
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164 | out dx, al |
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165 | ;----------------------------------------------------------------------------- |
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166 | ; set current ata bases |
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167 | @@: |
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168 | mov ax, [ecx+IDE_DATA.BAR0_val] |
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169 | mov [StandardATABases], ax |
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170 | mov ax, [ecx+IDE_DATA.BAR2_val] |
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171 | mov [StandardATABases+2], ax |
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172 | |||
173 | mov esi, boot_detecthdcd |
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174 | call boot_log |
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175 | ;-------------------------------------- |
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176 | include 'dev_hdcd.inc' |
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177 | ;-------------------------------------- |
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178 | ret |
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179 | ;----------------------------------------------------------------------------- |
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180 | Init_IDE_ATA_controller_2: |
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181 | cmp [ecx+IDE_DATA.ProgrammingInterface], 0 |
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182 | jne @f |
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183 | |||
184 | ret |
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185 | ;-------------------------------------- |
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186 | @@: |
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187 | mov dx, [ecx+IDE_DATA.RegsBaseAddres] |
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188 | ; test whether it is our interrupt? |
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189 | add dx, 2 |
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190 | in al, dx |
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191 | test al, 100b |
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192 | jz @f |
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193 | ; clear Bus Master IDE Status register |
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194 | ; clear Interrupt bit |
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195 | out dx, al |
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196 | ;-------------------------------------- |
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197 | @@: |
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198 | add dx, 8 |
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199 | ; test whether it is our interrupt? |
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200 | in al, dx |
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201 | test al, 100b |
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202 | jz @f |
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203 | ; clear Bus Master IDE Status register |
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204 | ; clear Interrupt bit |
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205 | out dx, al |
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206 | ;-------------------------------------- |
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207 | @@: |
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208 | ; read status register and remove the interrupt request |
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209 | mov dx, [ecx+IDE_DATA.BAR0_val] ;0x1F0 |
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210 | add dx, 0x7 ;0x1F7 |
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211 | in al, dx |
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212 | mov dx, [ecx+IDE_DATA.BAR2_val] ;0x170 |
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213 | add dx, 0x7 ;0x177 |
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214 | in al, dx |
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215 | ;----------------------------------------------------------------------------- |
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216 | ; push eax edx |
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217 | ; mov dx, [ecx+IDE_DATA.RegsBaseAddres] |
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218 | ; xor eax, eax |
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219 | ; add dx, 2 |
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220 | ; in al, dx |
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221 | ; DEBUGF 1, "K : Primary Bus Master IDE Status Register %x\n", eax |
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222 | |||
223 | ; add dx, 8 |
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224 | ; in al, dx |
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225 | ; DEBUGF 1, "K : Secondary Bus Master IDE Status Register %x\n", eax |
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226 | ; pop edx eax |
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227 | |||
228 | ; cmp [ecx+IDE_DATA.RegsBaseAddres], 0 |
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229 | ; setnz [ecx+IDE_DATA.dma_hdd] |
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230 | ;----------------------------------------------------------------------------- |
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231 | ; set interrupts for IDE Controller |
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232 | ;----------------------------------------------------------------------------- |
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233 | pushfd |
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234 | cli |
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235 | .enable_IDE_interrupt: |
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236 | mov esi, boot_enabling_ide |
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237 | call boot_log |
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238 | ; Enable interrupts in IDE controller for DMA |
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239 | xor ebx, ebx |
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240 | cmp ecx, IDE_controller_2 |
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241 | jne @f |
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242 | |||
243 | add ebx, 5 |
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244 | jmp .check_DRIVE_DATA |
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245 | ;-------------------------------------- |
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246 | @@: |
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247 | cmp ecx, IDE_controller_3 |
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248 | jne .check_DRIVE_DATA |
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249 | |||
250 | add ebx, 10 |
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251 | ;-------------------------------------- |
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252 | .check_DRIVE_DATA: |
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253 | mov al, 0 |
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254 | mov ah, [ebx+DRIVE_DATA+1] |
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255 | test ah, 10100000b ; check for ATAPI devices |
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256 | jz @f |
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257 | ;-------------------------------------- |
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258 | .ch1_pio_set_ATAPI: |
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259 | DEBUGF 1, "K : IDE CH1 PIO, because ATAPI drive present\n" |
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260 | jmp .ch1_pio_set_for_all |
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261 | ;-------------------------------------- |
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262 | .ch1_pio_set_no_devices: |
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263 | DEBUGF 1, "K : IDE CH1 PIO because no devices\n" |
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264 | jmp .ch1_pio_set_for_all |
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265 | ;------------------------------------- |
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266 | .ch1_pio_set: |
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267 | DEBUGF 1, "K : IDE CH1 PIO because device not support UDMA\n" |
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268 | ;------------------------------------- |
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269 | .ch1_pio_set_for_all: |
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270 | mov [ecx+IDE_DATA.dma_hdd_channel_1], al |
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271 | jmp .ch2_check |
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272 | ;-------------------------------------- |
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273 | @@: |
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274 | xor ebx, ebx |
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275 | call calculate_IDE_device_values_storage |
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276 | |||
277 | test ah, 1010000b |
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278 | jz .ch1_pio_set_no_devices |
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279 | |||
280 | test ah, 1000000b |
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281 | jz @f |
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282 | |||
283 | cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al |
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284 | je .ch1_pio_set |
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285 | |||
286 | cmp [ebx+IDE_DEVICE.UDMA_set_mode], al |
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287 | je .ch1_pio_set |
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288 | ;-------------------------------------- |
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289 | @@: |
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290 | test ah, 10000b |
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291 | jz @f |
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292 | |||
293 | add ebx, 2 |
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294 | |||
295 | cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al |
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296 | je .ch1_pio_set |
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297 | |||
298 | cmp [ebx+IDE_DEVICE.UDMA_set_mode], al |
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299 | je .ch1_pio_set |
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300 | ;-------------------------------------- |
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301 | @@: |
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302 | mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4 |
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303 | add dx, 2 ;0x3F6 |
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304 | out dx, al |
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305 | DEBUGF 1, "K : IDE CH1 DMA enabled\n" |
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306 | mov [ecx+IDE_DATA.dma_hdd_channel_1], byte 1 |
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307 | ;-------------------------------------- |
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308 | .ch2_check: |
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309 | test ah, 1010b ; check for ATAPI devices |
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310 | jz @f |
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311 | ;-------------------------------------- |
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312 | .ch2_pio_set_ATAPI: |
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313 | DEBUGF 1, "K : IDE CH2 PIO, because ATAPI drive present\n" |
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314 | jmp .ch2_pio_set_for_all |
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315 | ;-------------------------------------- |
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316 | .ch2_pio_set_no_devices: |
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317 | DEBUGF 1, "K : IDE CH2 PIO because no devices\n" |
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318 | jmp .ch2_pio_set_for_all |
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319 | ;-------------------------------------- |
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320 | .ch2_pio_set: |
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321 | DEBUGF 1, "K : IDE CH2 PIO because device not support UDMA\n" |
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322 | ;-------------------------------------- |
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323 | .ch2_pio_set_for_all: |
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324 | mov [ecx+IDE_DATA.dma_hdd_channel_2], al |
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325 | jmp .set_interrupts_for_IDE_controllers |
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326 | ;-------------------------------------- |
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327 | @@: |
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328 | mov ebx, 4 |
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329 | call calculate_IDE_device_values_storage |
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330 | |||
331 | test ah, 101b |
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332 | jz .ch2_pio_set_no_devices |
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333 | |||
334 | test ah, 100b |
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335 | jz @f |
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336 | |||
337 | cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al |
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338 | je .ch2_pio_set |
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339 | |||
340 | cmp [ebx+IDE_DEVICE.UDMA_set_mode], al |
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341 | je .ch2_pio_set |
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342 | ;-------------------------------------- |
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343 | @@: |
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344 | test ah, 1b |
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345 | jz @f |
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346 | |||
347 | add ebx, 2 |
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348 | |||
349 | cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al |
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350 | je .ch2_pio_set |
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351 | |||
352 | cmp [ebx+IDE_DEVICE.UDMA_set_mode], al |
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353 | je .ch2_pio_set |
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354 | ;-------------------------------------- |
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355 | @@: |
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356 | mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374 |
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357 | add dx, 2 ;0x376 |
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358 | out dx, al |
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359 | DEBUGF 1, "K : IDE CH2 DMA enabled\n" |
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360 | mov [ecx+IDE_DATA.dma_hdd_channel_2], byte 1 |
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361 | ;-------------------------------------- |
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362 | .set_interrupts_for_IDE_controllers: |
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363 | mov esi, boot_set_int_IDE |
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364 | call boot_log |
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365 | ;-------------------------------------- |
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366 | mov eax, [ecx+IDE_DATA.ProgrammingInterface] |
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367 | ; cmp ax, 0x0180 |
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368 | ; je .pata_ide |
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369 | |||
370 | ; cmp ax, 0x018a |
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371 | ; jne .sata_ide |
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372 | |||
373 | test al, 1 ; 0 - legacy PCI mode, 1 - native PCI mode |
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374 | jnz .sata_ide |
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375 | ;-------------------------------------- |
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376 | .pata_ide: |
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377 | cmp [ecx+IDE_DATA.RegsBaseAddres], 0 |
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378 | je .end_set_interrupts |
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379 | |||
380 | push ecx |
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381 | stdcall attach_int_handler, 14, IDE_irq_14_handler, 0 |
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382 | DEBUGF 1, "K : Set IDE IRQ14 return code %x\n", eax |
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383 | stdcall attach_int_handler, 15, IDE_irq_15_handler, 0 |
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384 | DEBUGF 1, "K : Set IDE IRQ15 return code %x\n", eax |
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385 | pop ecx |
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386 | |||
387 | jmp .end_set_interrupts |
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388 | ;-------------------------------------- |
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389 | .sata_ide: |
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390 | ; cmp ax, 0x0185 |
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391 | ; je .sata_ide_1 |
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392 | |||
393 | ; cmp ax, 0x018f |
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394 | ; jne .end_set_interrupts |
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395 | ;-------------------------------------- |
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396 | ;.sata_ide_1: |
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397 | ; Some weird controllers generate an interrupt even if IDE interrupts |
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398 | ; are disabled and no IDE devices. For example, notebook ASUS K72F - |
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399 | ; IDE controller 010185 generates false interrupt when we work with |
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400 | ; the IDE controller 01018f. For this reason, the interrupt handler |
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401 | ; does not need to be installed if both channel IDE controller |
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402 | ; running in PIO mode. |
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403 | cmp [ecx+IDE_DATA.RegsBaseAddres], 0 |
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404 | je .end_set_interrupts |
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405 | |||
406 | cmp [ecx+IDE_DATA.dma_hdd_channel_1], 0 |
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407 | jne @f |
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408 | |||
409 | cmp [ecx+IDE_DATA.dma_hdd_channel_2], 0 |
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410 | je .end_set_interrupts |
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411 | ;-------------------------------------- |
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412 | @@: |
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413 | mov ax, [ecx+IDE_DATA.Interrupt] |
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414 | movzx eax, al |
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415 | push ecx |
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416 | stdcall attach_int_handler, eax, IDE_common_irq_handler, 0 |
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417 | pop ecx |
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418 | DEBUGF 1, "K : Set IDE IRQ%d return code %x\n", [ecx+IDE_DATA.Interrupt]:1, eax |
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419 | ;-------------------------------------- |
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420 | .end_set_interrupts: |
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421 | popfd |
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422 | ret |
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423 | ;----------------------------------------------------------------------------- |
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424 | ; END of initialisation IDE ATA code |
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425 | ;----------------------------------------------------------------------------- |
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426 | find_IDE_controller_done: |
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427 | mov ecx, IDE_controller_1 |
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428 | mov [IDE_controller_pointer], ecx |
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429 | call Init_IDE_ATA_controller |
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430 | mov ecx, IDE_controller_2 |
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431 | mov [IDE_controller_pointer], ecx |
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432 | call Init_IDE_ATA_controller |
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433 | mov ecx, IDE_controller_3 |
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434 | mov [IDE_controller_pointer], ecx |
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435 | call Init_IDE_ATA_controller |
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436 | ;----------------------------------------------------------------------------- |
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437 | mov esi, boot_getcache |
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438 | call boot_log |
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439 | include 'getcache.inc' |
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440 | ;----------------------------------------------------------------------------- |
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441 | mov esi, boot_detectpart |
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442 | call boot_log |
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443 | include 'sear_par.inc' |
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444 | ;----------------------------------------------------------------------------- |
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445 | mov esi, boot_init_sys |
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446 | call boot_log |
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447 | call Parser_params |
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448 | |||
449 | if ~ defined extended_primary_loader |
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450 | ; ramdisk image should be loaded by extended primary loader if it exists |
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451 | ; READ RAMDISK IMAGE FROM HD |
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452 | include '../boot/rdload.inc' |
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453 | end if |
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454 | ;----------------------------------------------------------------------------- |
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455 | mov ecx, IDE_controller_1 |
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456 | mov [IDE_controller_pointer], ecx |
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457 | call Init_IDE_ATA_controller_2 |
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458 | mov ecx, IDE_controller_2 |
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459 | mov [IDE_controller_pointer], ecx |
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460 | call Init_IDE_ATA_controller_2 |
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461 | mov ecx, IDE_controller_3 |
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462 | mov [IDE_controller_pointer], ecx |
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463 | call Init_IDE_ATA_controller_2 |
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464 | ;----------------------------------------------------------------------------- |