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Rev | Author | Line No. | Line |
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2014 | art_zh | 1 | $Revision: 1598 $ |
2 | |||
3 | SMBUS_PCIE_ADDR equ 0xF00A0000 ; bdf0:20.0 = SB7xx SMBus PCI Config Registers |
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4 | LPC_PCIE_ADDR equ 0xF00A3000 ; bdf0:20.3 = SB7xx LPC ISA bridge Config Registers |
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5 | |||
6 | SB_SIO_INDEX equ 0x2E |
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7 | SB_PM_INDEX equ 0xCD6 |
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8 | |||
9 | if PLATFORM>PLATFORM_RS780 |
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10 | include "bus/sb/hudson.inc" |
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11 | else |
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12 | include "bus/sb/sb710.inc" |
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13 | end if |
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14 | |||
15 | ;--------------------------------------------------------------------- |
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16 | align 4 |
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17 | smbus_read_pciconfig: |
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18 | ; in: dl = reg# | out: eax = data |
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19 | mov ebx, SMBUS_PCIE_ADDR |
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20 | and edx, 0x0FC |
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21 | mov eax, dword [ebx+edx] |
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22 | ret |
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23 | ;------------------------------------------------ |
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24 | align 4 |
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25 | smbus_write_pciconfig: |
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26 | ; in: dl = reg#; eax = data |
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27 | mov ebx, SMBUS_PCIE_ADDR |
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28 | and edx, 0x0FC |
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29 | mov dword [ebx+edx], eax |
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30 | ret |
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31 | |||
32 | ;-------------------------------------------------------------------- |
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33 | align 4 |
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34 | lpc_read_pciconfig: |
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35 | ; in: dl = reg# | out: eax = data |
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36 | mov ebx, LPC_PCIE_ADDR |
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37 | and edx, 0x0FC |
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38 | mov eax, dword [ebx+edx] |
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39 | ret |
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40 | ;------------------------------------------------ |
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41 | align 4 |
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42 | lpc_write_pciconfig: |
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43 | ; in: dl = reg#; eax = data |
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44 | mov ebx, LPC_PCIE_ADDR |
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45 | and edx, 0x0FC |
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46 | mov dword [ebx+edx], eax |
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47 | ret |
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48 | |||
49 | ;-------------------------------------------------------------------- |
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50 | align 4 |
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51 | read_sio_cfg: |
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52 | ; in: al = reg# | out: al = data |
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53 | push edx |
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54 | mov dx, SB_SIO_INDEX |
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55 | out dx, al |
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56 | inc dl |
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57 | in al, dx |
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58 | pop edx |
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59 | ret |
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60 | |||
61 | ;------------------------------------------------ |
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62 | align 4 |
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63 | write_pm_cfg: |
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64 | ; in: al = reg#; ah = data |
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65 | ;------------------------------------------------ |
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66 | push edx |
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67 | mov dx, SB_PM_INDEX |
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68 | out dx, al |
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69 | inc dl |
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70 | xchg al, ah |
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71 | out dx, al |
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72 | xchg al, ah |
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73 | pop edx |
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74 | ret |
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75 | ;-------------------------------------------------------------------- |
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76 | align 4 |
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77 | read_pm_cfg: |
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78 | ; in: al = reg# | out: al = data |
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79 | push edx |
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80 | mov dx, SB_PM_INDEX |
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81 | out dx, al |
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82 | inc dl |
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83 | in al, dx |
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84 | pop edx |
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85 | ret |
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86 | |||
87 | ;------------------------------------------------ |
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88 | align 4 |
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89 | write_sio_cfg: |
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90 | ; in: al = reg#; ah = data |
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91 | ;------------------------------------------------ |
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92 | push edx |
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93 | mov dx, SB_SIO_INDEX |
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94 | out dx, al |
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95 | inc dl |
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96 | xchg al, ah |
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97 | out dx, al |
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98 | xchg al, ah |
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99 | pop edx |
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100 | ret |
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101 | ;------------------------------------------------ |
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102 | align 4 |
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103 | enter_sio_cfg_mode: |
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104 | ; the magic sequence to unlock the port |
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105 | ;------------------------------------------------ |
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106 | mov dx, SB_SIO_INDEX |
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107 | mov eax, 0x55550187 ; low byte first |
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108 | out dx, al |
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109 | shr eax, 8 |
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110 | out dx, al |
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111 | shr eax, 8 |
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112 | out dx, al |
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113 | shr eax, 8 |
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114 | out dx, al |
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115 | ret |
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116 | |||
117 | ;----------------------------------------------------------------------- |
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118 | ; ATTENTION: the functions assume that RESET# signals use pins 84 and 34 |
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119 | ; of IT8712F SuperIO chip. These signals may be (and will be!) different |
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120 | ; for every particular motherboard and SIO. Please refer to your m/board |
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121 | ; documentation to define the correct pins and GPIO lines! |
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122 | ; |
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123 | ; Note this example DOES NOT PRETEND to be 100% correct implementation |
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124 | ; of PCIe hotplug techniques !! |
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125 | ;----------------------------------------------------------------------- |
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126 | align 4 |
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127 | init_pcie_slot_control: |
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128 | ;------------------------------------------------ |
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129 | call enter_sio_cfg_mode |
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130 | mov ax, 0x0707 ; LDN = 07 |
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131 | call write_sio_cfg |
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132 | mov al, 0x25 |
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133 | call read_sio_cfg ; ah = reg25h (Multy-function pin selector) |
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134 | or ah, 3 ; set bits 0, 1 (GPIO) |
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135 | call write_sio_cfg |
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136 | mov al, 0x2A |
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137 | call read_sio_cfg ; ah = reg2Ah (Extended fn pin selector) |
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138 | or ah, 3 ; set bits 0, 1 (GPIO) |
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139 | call write_sio_cfg |
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140 | mov al, 0xB8 |
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141 | call read_sio_cfg ; ah = regB8h (internal pull-up enable) |
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142 | or ah, 3 ; set bits 0, 1 |
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143 | call write_sio_cfg |
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144 | mov al, 0xC0 |
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145 | call read_sio_cfg ; ah = regC0h (simple IO enable) |
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146 | or ah, 3 ; set bits 0, 1 |
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147 | call write_sio_cfg |
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148 | mov ax, 0x0202 ; Lock SIO config ports |
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149 | call write_sio_cfg |
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150 | ret |
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151 | |||
152 | align 4 |
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153 | reset_pcie_slot: |
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154 | ;------------------------------------------------ |
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155 | call enter_sio_cfg_mode |
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156 | mov ax, 0x0707 ; LDN = 07 |
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157 | call write_sio_cfg |
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158 | mov al, 0xB0 |
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159 | call read_sio_cfg ; ah = regB0h (Pin polarity) |
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160 | and ah, 0xFC ; invert bits 0, 1 |
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161 | call write_sio_cfg |
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162 | or ah, 3 ; restore bits 0, 1 |
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163 | call write_sio_cfg |
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164 | mov ax, 0x0202 ; Lock SIO config ports |
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165 | call write_sio_cfg |
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166 | ret |
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167 |