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1551 art_zh 1 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                                                              ;;
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;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;;                                                              ;;
1683 art_zh 6 
;;  HT.inc                                                      ;;                                                    ;;
1551 art_zh 7 
;;                                                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;                                                              ;;
1599 art_zh 10 
;;                  art_zh                ;;
1551 art_zh 11 
;;                                                              ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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1560 art_zh 14 
$Revision: 1554 $
1551 art_zh 15 
 
1599 art_zh 16 
NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
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NB_MISC_DATA	equ	0xF0000064
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PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
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HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
1551 art_zh 20 
 
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;=============================================================================
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;
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; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
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;
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;=============================================================================
1683 art_zh 26 
 
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org $-OS_BASE	; physical addresses needed at initial stage
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1560 art_zh 29 
align 4
1551 art_zh 30 
 
31 
;------------------------------------------
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;       params:   al = nbconfig register#
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;       returns: eax = register content
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;
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rs7xx_nbconfig_read_pci:
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	and	eax, 0x0FC		 ; leave register# only
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	or	eax, 0x80000000 	 ; bdf = 0:0.0
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	mov	dx,  0x0CF8		 ; write to index reg
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	out	dx, eax
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	add	dl, 4
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	in	eax, dx
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	ret
1560 art_zh 43 
align 4
1551 art_zh 44 
 
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rs7xx_nbconfig_flush_pci:
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	mov	eax, 0x0B0		; a scratch reg
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	mov	dx,  0xCF8
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	out	dx,  eax
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	ret
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1560 art_zh 51 
align 4
1551 art_zh 52 
 
1599 art_zh 53 
;------------------------------------------
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;       params:   al = nbconfig register#
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;                ebx = register content
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;
1551 art_zh 57 
rs7xx_nbconfig_write_pci:
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	and	eax, 0x0FC		 ; leave register# only
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	or	eax, 0x80000000 	 ; bdf = 0:0.0
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	mov	dx,  0x0CF8		 ; write to index reg
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	out	dx, eax
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	add	dl, 4
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	mov	eax, ebx
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	out	dx, eax
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	ret
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67 
;***************************************************************************
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;   Function
1599 art_zh 69 
;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
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;                             makes pcie config address space visible
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;   -----------------------
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;   in: nothing      out: nothing      destroys:   eax ebx edx
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;
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;***************************************************************************
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align 4
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rs7xx_unlock_bar3:
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	mov	eax, NB_MISC_INDEX
1683 art_zh 78 
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
1599 art_zh 79 
	call	rs7xx_nbconfig_write_pci	; set index
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	mov	eax, NB_MISC_DATA
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	call	rs7xx_nbconfig_read_pci 	; read data
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	mov	ebx, eax
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	and	ebx, 0xFFFFFFF7 		; clear bit3
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	mov	eax, NB_MISC_DATA
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	call	rs7xx_nbconfig_write_pci	; write it back
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	mov	eax, NB_MISC_INDEX
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	xor	ebx, ebx			; reg#0; write-locked
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	call	rs7xx_nbconfig_write_pci	; set index
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	ret
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1683 art_zh 91 
 
92 
 
93 
;***************************************************************************
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;   Function
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;      rs7xx_pcie_init:
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;
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;   Description
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;       PCIe extended (memory-mapped) config space detection
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;
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;***************************************************************************
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102 
align 4
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104 
rs7xx_pcie_init:
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	call	rs7xx_unlock_bar3
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	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
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	call	rs7xx_nbconfig_read_pci
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	mov	ebx, eax
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;       call    rs7xx_nbconfig_flush_pci
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	test	ebx, 0x20000000 		; BAR3 locked?
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	jz	$
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	mov	al, 0x84			; NB_PCI_ARB
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	call	rs7xx_nbconfig_read_pci
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	shr	eax,16
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	and	ax, 7				; the Bus range lays here:
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	jnz	@f
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	mov	ax, 8					; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
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@@:
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	mov	word[PCIe_bus_range-OS_BASE], ax	; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
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	mov	cl, al
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	call	rs7xx_nbconfig_flush_pci
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	dec	cl				; <4M ?
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	jz	@f
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	dec	cl				; one PDE needed anyway
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@@:
126 
	mov	ebx, 1
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	shl	ebx, cl
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	mov	word[mmio_pcie_cfg_pdes-OS_BASE], bx	; 1..64 PDE(s) needed,
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	shl	ebx, 22
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], ebx	; or 4..256Mb space to map
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	dec	dword[mmio_pcie_cfg_lim-OS_BASE]
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133 
	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
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	call	rs7xx_nbconfig_read_pci
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	mov	ebx, eax
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	call	rs7xx_nbconfig_flush_pci
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	mov	eax, ebx
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	and	eax, 0xFFE00000 		; valid bits [31..21]
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	jz	$				; NB BAR3 may be invisible!
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.addr_found:
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	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
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	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
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144 
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ebx, ecx
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
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	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
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	jb	@f
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	mov	dl, 0x33
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	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
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@@:
155 
	xor	dx,  dx 			; PDEs counter
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.write_pde:
157 
	mov	dword[ebx], eax 		; map 4 buses
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	add	bx,  4				; new PDE
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	add	eax, 0x400000			; +4M phys.
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	add	ecx, 0x400000			; +4M lin.
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	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
162 
	jae	.pcie_cfg_mapped
163 
	inc	dl
164 
	jmp	.write_pde
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;        mov     eax, cr3
166 
;        mov     cr3, eax                        ; flush TLB
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.pcie_cfg_mapped:
168 
	ret	; <<< OK >>>
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170 
 
171 
; ================================================================================
172 
 
173 
org OS_BASE+$	; back to the linear address space
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1599 art_zh 175 
;--------------------------------------------------------------
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align 4
177 
rs780_read_misc:
178 
;  in: eax(al) - reg#           out: eax = NBMISCIND data
179 
	push	edx
180 
	mov	edx, NB_MISC_INDEX
181 
	and	eax, 0x07F
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	mov	[edx], eax
183 
	add	dl, 4
184 
	mov	eax, [edx]
185 
	pop	edx
186 
	ret
187 
 
188 
;-------------------------------------------
189 
align 4
190 
rs780_write_misc:
191 
;  in: eax(al) - reg#     ebx = NBMISCIND data
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	push	edx
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	mov	edx, NB_MISC_INDEX
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	and	eax, 0x07F
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	or	eax, 0x080		; set WE
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	mov	[edx], eax
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	add	dl, 4
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	mov	[edx], ebx
199 
	sub	dl, 4
200 
	xor	eax,   eax
201 
	mov	[edx], eax		; safety last
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	pop	edx
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	ret
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205 
;-------------------------------------------------------------
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align 4
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rs780_read_pcieind:
208 
;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
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	push	edx
210 
	xor	edx, edx
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	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
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	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
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	shl	edx, 15 		; device#
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	add	edx, PCIEIND_INDEX	; full bdf-address
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	and	eax, 0x30FF
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	or	al,  al
217 
	jnz	@f
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	shl	eax, 4			; set bits 17..16 for a Core bridge
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@@:
220 
	mov	[edx], eax
221 
	add	dl,  4
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	mov	eax, [edx]
223 
	pop	edx
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	ret
225 
 
226 
;-------------------------------------------
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align 4
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rs780_write_pcieind:
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;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
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	push	edx
231 
	xor	edx, edx
232 
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
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	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
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	shl	edx, 15 		; device#
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	add	edx, PCIEIND_INDEX	; full bdf-address
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	and	eax, 0x30FF
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	or	al,  al
238 
	jnz	@f
239 
	shl	eax, 4			; set bits 17..16 for a Core bridge
240 
@@:
241 
	mov	[edx], eax
242 
	add	dl,  4
243 
	mov	[edx], ebx
244 
	sub	dl,  4
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	xor	eax,   eax
246 
	mov	[edx], eax		; safety last
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	pop	edx
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	ret
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250 
;------------------------------------------------
251 
align 4
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rs780_read_htiu:
253 
; in:  al = reg#  |  out: eax = HTIU data
254 
;------------------------------------------------
255 
	push	edx
256 
	mov	edx,  HTIU_NB_INDEX
257 
	and	eax, 0x07F
258 
	mov	[edx], eax
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	add	dl,  4
260 
	mov	eax, [edx]
261 
	pop	edx
262 
	ret
263 
;------------------------------------------------
264 
align 4
265 
rs780_write_htiu:
266 
; in:  al = reg#; ebx = data
267 
;------------------------------------------------
268 
	push	edx
269 
	mov	edx,  HTIU_NB_INDEX
270 
	and	eax, 0x07F
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	or	eax, 0x100
272 
	mov	[edx], eax
273 
	add	dl,  4
274 
	mov	[edx], ebx
275 
	sub	dl,  4
276 
	xor	eax,   eax
277 
	mov	[edx], eax
278 
	pop	edx
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	ret
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