Subversion Repositories Kolibri OS

Rev

Rev 1560 | Go to most recent revision | Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
1551 art_zh 1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2
;;                                                              ;;
3
;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
4
;; Distributed under terms of the GNU General Public License    ;;
5
;;                                                              ;;
6
;;  HT.inc                                                      ;;                                                    ;;
7
;;                                                              ;;
8
;;  AMD HyperTransport bus control                              ;;
9
;;                                                              ;;
10
;;                  art_zh                  ;;
11
;;                                                              ;;
12
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13
 
14
 
15
 
16
align 4
17
 
18
;=============================================================================
19
;
20
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
21
;
22
;=============================================================================
23
 
24
;------------------------------------------
25
;       params:   al = nbconfig register#
26
;       returns: eax = register content
27
;
28
rs7xx_nbconfig_read_pci:
29
	and	eax, 0x0FC		 ; leave register# only
30
	or	eax, 0x80000000 	 ; bdf = 0:0.0
31
	mov	dx,  0x0CF8		 ; write to index reg
32
	out	dx, eax
33
	add	dl, 4
34
	in	eax, dx
35
	ret
36
 
37
rs7xx_nbconfig_flush_pci:
38
	mov	eax, 0x0B0		; a scratch reg
39
	mov	dx,  0xCF8
40
	out	dx,  eax
41
	ret
42
 
43
 
44
rs7xx_nbconfig_write_pci:
45
	and	eax, 0x0FC		 ; leave register# only
46
	or	eax, 0x80000000 	 ; bdf = 0:0.0
47
	mov	dx,  0x0CF8		 ; write to index reg
48
	out	dx, eax
49
	add	dl, 4
50
	mov	eax, ebx
51
	out	dx, eax
52
	ret
53
 
54
;***************************************************************************
55
;   Function
56
;      rs7xx_pcie_init:
57
;
58
;   Description
59
;       PCIe extended (memory-mapped) config space detection
60
;
61
;***************************************************************************
62
 
63
rs7xx_pcie_init:
64
;        mov     al,  0x7C                       ; NB_IOC_CFG_CNTL
65
;        mov     ebx, 0x20000000
66
;        call    rs7xx_nbconfig_write_pci
67
	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
68
	call	rs7xx_nbconfig_read_pci
69
	mov	ebx, eax
70
	call	rs7xx_nbconfig_flush_pci
71
	test	ebx, 0x20000000 		; BAR3 locked?
72
	jz	.rs7xx_pcie_blocked
73
	mov	al, 0x84			; NB_PCI_ARB
74
	call	rs7xx_nbconfig_read_pci
75
	shr	eax,16
76
	and	ax, 7				; the Bus range lays here:
77
	jnz	@f
78
	mov	ax, 8				; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
79
@@:
80
	mov	[PCIe_bus_range], ax		; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
81
	mov	cl, al
82
	call	rs7xx_nbconfig_flush_pci
83
	dec	cl				; <4M ?
84
	jnz	@f
85
	inc	cl				; one PDE needed anyway
86
@@:
87
	dec	cl
88
	mov	ebx, 1
89
	shl	ebx, cl
90
	mov	[mmio_pcie_cfg_pdes], bx	; 1..64 PDE(s) needed,
91
	shl	ebx, 22
92
	mov	[mmio_pcie_cfg_lim], ebx	; or 4..256Mb space to map
93
	dec	[mmio_pcie_cfg_lim]
94
 
95
	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
96
	call	rs7xx_nbconfig_read_pci
97
	mov	ebx, eax
98
	call	rs7xx_nbconfig_flush_pci
99
	mov	eax, ebx
100
	and	eax, 0xFFE00000 		; valid bits [31..21]
101
	jnz	@f				; NB BAR3 may be invisible!
102
	call  pci_ext_config		; try to get pcie ecfg address indirectly
103
@@:
104
	or 	eax, eax
105
	jz	.rs7xx_pcie_fail
106
	mov	[mmio_pcie_cfg_addr], eax	; physical address (lower 32 bits)
107
	add	[mmio_pcie_cfg_lim],  eax
108
 
109
;       -- map the whole PCIe config space;
110
	or	eax, (PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
111
	mov	ecx, PCIe_CONFIG_SPACE		; linear address
112
	mov	ebx, ecx
113
	shr	ebx, 20
114
	add	ebx, sys_pgdir			; PgDir entry @
115
	xor	dx,  dx 				; PDEs counter
116
@@:
117
	mov	dword[ebx], eax 			; map 4 buses
118
	invlpg	[ecx]				; next PgDir entry
119
	add	bx,  4				; new PDE
120
	add	eax, 0x400000			; +4M phys.
121
	add	ecx, 0x400000			; +4M lin.
122
	inc	dx
123
	cmp	dx, [mmio_pcie_cfg_pdes]	; all mapped yet?
124
	jnz	@b
125
 
126
.pcie_cfg_mapped:
127
	mov	esi, boot_pcie_ok
128
	call	boot_log
129
	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
130
 
131
.rs7xx_pcie_fail:
132
	mov	esi, boot_rs7xx_fail
133
	call	boot_log
134
	ret
135
 
136
.rs7xx_pcie_blocked:
137
	mov	esi, boot_rs7xx_blkd
138
	call	boot_log
139
 
140
 
141
	ret
142