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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | /* |
| 2 | * Copyright 2007-2008 Luc Verhaegen |
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| 3 | * Copyright 2007-2008 Matthias Hopf |
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| 4 | * Copyright 2007-2008 Egbert Eich |
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| 5 | * Copyright 2007-2008 Advanced Micro Devices, Inc. |
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| 6 | * |
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| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | * copy of this software and associated documentation files (the "Software"), |
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| 9 | * to deal in the Software without restriction, including without limitation |
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| 10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | * Software is furnished to do so, subject to the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice shall be included in |
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| 15 | * all copies or substantial portions of the Software. |
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| 16 | * |
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 20 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 23 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | */ |
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| 25 | |||
| 26 | /* |
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| 27 | * Deals with the Primary TMDS device (TMDSA) of R500s, R600s. |
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| 28 | * Gets replaced by DDIA on RS690 and DIG/UNIPHY on RV620. |
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| 29 | */ |
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| 30 | |||
| 31 | #ifdef HAVE_CONFIG_H |
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| 32 | #include "config.h" |
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| 33 | #endif |
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| 34 | |||
| 35 | #include "xf86.h" |
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| 36 | |||
| 37 | /* for usleep */ |
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| 38 | #if HAVE_XF86_ANSIC_H |
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| 39 | # include "xf86_ansic.h" |
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| 40 | #else |
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| 41 | # include |
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| 42 | #endif |
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| 43 | #include "rhd.h" |
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| 44 | #include "rhd_crtc.h" |
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| 45 | #include "rhd_connector.h" |
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| 46 | #include "rhd_output.h" |
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| 47 | #include "rhd_regs.h" |
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| 48 | #include "rhd_hdmi.h" |
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| 49 | |||
| 50 | #ifdef ATOM_BIOS |
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| 51 | #include "rhd_atombios.h" |
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| 52 | #endif |
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| 53 | |||
| 54 | struct rhdTMDSPrivate { |
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| 55 | Bool RunsDualLink; |
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| 56 | DisplayModePtr Mode; |
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| 57 | Bool Coherent; |
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| 58 | int PowerState; |
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| 59 | |||
| 60 | struct rhdHdmi *Hdmi; |
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| 61 | |||
| 62 | Bool Stored; |
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| 63 | |||
| 64 | CARD32 StoreControl; |
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| 65 | CARD32 StoreSource; |
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| 66 | CARD32 StoreFormat; |
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| 67 | CARD32 StoreForce; |
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| 68 | CARD32 StoreReduction; |
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| 69 | CARD32 StoreDCBalancer; |
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| 70 | CARD32 StoreDataSynchro; |
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| 71 | CARD32 StoreTXEnable; |
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| 72 | CARD32 StoreMacro; |
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| 73 | CARD32 StoreTXControl; |
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| 74 | CARD32 StoreTXAdjust; |
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| 75 | }; |
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| 76 | |||
| 77 | /* |
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| 78 | * We cannot sense for dual link here at all, plus, we need a bit more work |
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| 79 | * for enabling the transmitter for sensing to happen on most R5xx cards. |
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| 80 | * RV570 (0x7280) and R600 and above seem ok. |
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| 81 | */ |
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| 82 | static enum rhdSensedOutput |
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| 83 | TMDSASense(struct rhdOutput *Output, struct rhdConnector *Connector) |
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| 84 | { |
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| 85 | RHDPtr rhdPtr = RHDPTRI(Output); |
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| 86 | CARD32 Enable, Control, Detect; |
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| 87 | enum rhdConnectorType Type = Connector->Type; |
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| 88 | Bool ret; |
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| 89 | |||
| 90 | RHDFUNC(Output); |
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| 91 | |||
| 92 | if ((Type != RHD_CONNECTOR_DVI) && (Type != RHD_CONNECTOR_DVI_SINGLE)) { |
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| 93 | xf86DrvMsg(Output->scrnIndex, X_WARNING, |
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| 94 | "%s: connector type %d is not supported.\n", |
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| 95 | __func__, Type); |
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| 96 | return RHD_SENSED_NONE; |
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| 97 | } |
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| 98 | |||
| 99 | Enable = RHDRegRead(Output, TMDSA_TRANSMITTER_ENABLE); |
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| 100 | Control = RHDRegRead(Output, TMDSA_TRANSMITTER_CONTROL); |
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| 101 | Detect = RHDRegRead(Output, TMDSA_LOAD_DETECT); |
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| 102 | |||
| 103 | if (rhdPtr->ChipSet < RHD_R600) { |
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| 104 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x00000003, 0x00000003); |
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| 105 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000001, 0x00000003); |
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| 106 | } |
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| 107 | |||
| 108 | RHDRegMask(Output, TMDSA_LOAD_DETECT, 0x00000001, 0x00000001); |
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| 109 | usleep(1); |
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| 110 | ret = RHDRegRead(Output, TMDSA_LOAD_DETECT) & 0x00000010; |
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| 111 | |||
| 112 | RHDRegMask(Output, TMDSA_LOAD_DETECT, Detect, 0x00000001); |
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| 113 | |||
| 114 | if (rhdPtr->ChipSet < RHD_R600) { |
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| 115 | RHDRegWrite(Output, TMDSA_TRANSMITTER_ENABLE, Enable); |
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| 116 | RHDRegWrite(Output, TMDSA_TRANSMITTER_CONTROL, Control); |
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| 117 | } |
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| 118 | |||
| 119 | RHDDebug(Output->scrnIndex, "%s: %s\n", __func__, |
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| 120 | ret ? "Attached" : "Disconnected"); |
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| 121 | |||
| 122 | if (ret) |
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| 123 | return RHD_SENSED_DVI; |
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| 124 | else |
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| 125 | return RHD_SENSED_NONE; |
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| 126 | } |
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| 127 | |||
| 128 | /* |
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| 129 | * |
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| 130 | */ |
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| 131 | static ModeStatus |
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| 132 | TMDSAModeValid(struct rhdOutput *Output, DisplayModePtr Mode) |
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| 133 | { |
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| 134 | RHDFUNC(Output); |
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| 135 | |||
| 136 | if (Mode->Flags & V_INTERLACE) |
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| 137 | return MODE_NO_INTERLACE; |
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| 138 | |||
| 139 | if (Mode->Clock < 25000) |
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| 140 | return MODE_CLOCK_LOW; |
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| 141 | |||
| 142 | if (Output->Connector->Type == RHD_CONNECTOR_DVI_SINGLE) { |
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| 143 | if (Mode->Clock > 165000) |
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| 144 | return MODE_CLOCK_HIGH; |
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| 145 | } else if (Output->Connector->Type == RHD_CONNECTOR_DVI) { |
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| 146 | if (Mode->Clock > 330000) /* could go higher still */ |
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| 147 | return MODE_CLOCK_HIGH; |
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| 148 | } |
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| 149 | |||
| 150 | return MODE_OK; |
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| 151 | } |
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| 152 | |||
| 153 | /* |
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| 154 | * This information is not provided in an atombios data table. |
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| 155 | */ |
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| 156 | static struct R5xxTMDSAMacro { |
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| 157 | CARD16 Device; |
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| 158 | CARD32 Macro; |
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| 159 | } R5xxTMDSAMacro[] = { |
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| 160 | { 0x7104, 0x00C00414 }, /* R520 */ |
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| 161 | { 0x7142, 0x00A00415 }, /* RV515 */ |
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| 162 | { 0x7145, 0x00A00416 }, /* M54 */ |
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| 163 | { 0x7146, 0x00C0041F }, /* RV515 */ |
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| 164 | { 0x7147, 0x00C00418 }, /* RV505 */ |
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| 165 | { 0x7149, 0x00800416 }, /* M56 */ |
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| 166 | { 0x7152, 0x00A00415 }, /* RV515 */ |
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| 167 | { 0x7183, 0x00600412 }, /* RV530 */ |
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| 168 | { 0x71C1, 0x00C0041F }, /* RV535 */ |
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| 169 | { 0x71C2, 0x00A00416 }, /* RV530 */ |
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| 170 | { 0x71C4, 0x00A00416 }, /* M56 */ |
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| 171 | { 0x71C5, 0x00A00416 }, /* M56 */ |
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| 172 | { 0x71C6, 0x00A00513 }, /* RV530 */ |
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| 173 | { 0x71D2, 0x00A00513 }, /* RV530 */ |
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| 174 | { 0x71D5, 0x00A00513 }, /* M66 */ |
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| 175 | { 0x7249, 0x00A00513 }, /* R580 */ |
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| 176 | { 0x724B, 0x00A00513 }, /* R580 */ |
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| 177 | { 0x7280, 0x00C0041F }, /* RV570 */ |
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| 178 | { 0x7288, 0x00C0041F }, /* RV570 */ |
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| 179 | { 0x9400, 0x00910419 }, /* R600: */ |
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| 180 | { 0, 0} /* End marker */ |
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| 181 | }; |
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| 182 | |||
| 183 | static struct Rv6xxTMDSAMacro { |
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| 184 | CARD16 Device; |
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| 185 | CARD32 PLL; |
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| 186 | CARD32 TX; |
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| 187 | } Rv6xxTMDSAMacro[] = { |
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| 188 | { 0x94C1, 0x00010416, 0x00010308 }, /* RV610 */ |
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| 189 | { 0x94C3, 0x00010416, 0x00010308 }, /* RV610 */ |
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| 190 | { 0x9501, 0x00010416, 0x00010308 }, /* RV670: != atombios */ |
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| 191 | { 0x9505, 0x00010416, 0x00010308 }, /* RV670: != atombios */ |
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| 192 | { 0x950F, 0x00010416, 0x00010308 }, /* R680 : != atombios */ |
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| 193 | { 0x9581, 0x00030410, 0x00301044 }, /* M76 */ |
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| 194 | { 0x9587, 0x00010416, 0x00010308 }, /* RV630 */ |
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| 195 | { 0x9588, 0x00010416, 0x00010388 }, /* RV630 */ |
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| 196 | { 0x9589, 0x00010416, 0x00010388 }, /* RV630 */ |
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| 197 | { 0, 0, 0} /* End marker */ |
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| 198 | }; |
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| 199 | |||
| 200 | static void |
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| 201 | TMDSAVoltageControl(struct rhdOutput *Output) |
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| 202 | { |
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| 203 | RHDPtr rhdPtr = RHDPTRI(Output); |
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| 204 | int i; |
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| 205 | |||
| 206 | if (rhdPtr->ChipSet < RHD_RV610) { |
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| 207 | for (i = 0; R5xxTMDSAMacro[i].Device; i++) |
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| 208 | if (R5xxTMDSAMacro[i].Device == rhdPtr->PciDeviceID) { |
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| 209 | RHDRegWrite(Output, TMDSA_MACRO_CONTROL, R5xxTMDSAMacro[i].Macro); |
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| 210 | return; |
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| 211 | } |
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| 212 | |||
| 213 | xf86DrvMsg(Output->scrnIndex, X_ERROR, "%s: unhandled chipset: 0x%04X.\n", |
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| 214 | __func__, rhdPtr->PciDeviceID); |
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| 215 | xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_MACRO_CONTROL: 0x%08X\n", |
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| 216 | (unsigned int) RHDRegRead(Output, TMDSA_MACRO_CONTROL)); |
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| 217 | } else { |
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| 218 | for (i = 0; Rv6xxTMDSAMacro[i].Device; i++) |
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| 219 | if (Rv6xxTMDSAMacro[i].Device == rhdPtr->PciDeviceID) { |
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| 220 | RHDRegWrite(Output, TMDSA_PLL_ADJUST, Rv6xxTMDSAMacro[i].PLL); |
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| 221 | RHDRegWrite(Output, TMDSA_TRANSMITTER_ADJUST, Rv6xxTMDSAMacro[i].TX); |
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| 222 | return; |
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| 223 | } |
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| 224 | xf86DrvMsg(Output->scrnIndex, X_ERROR, "%s: unhandled chipset: 0x%04X.\n", |
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| 225 | __func__, rhdPtr->PciDeviceID); |
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| 226 | xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_PLL_ADJUST: 0x%08X\n", |
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| 227 | (unsigned int) RHDRegRead(Output, TMDSA_PLL_ADJUST)); |
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| 228 | xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_TRANSMITTER_ADJUST: 0x%08X\n", |
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| 229 | (unsigned int) RHDRegRead(Output, TMDSA_TRANSMITTER_ADJUST)); |
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| 230 | } |
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| 231 | } |
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| 232 | |||
| 233 | /* |
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| 234 | * |
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| 235 | */ |
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| 236 | static Bool |
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| 237 | TMDSAPropertyControl(struct rhdOutput *Output, |
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| 238 | enum rhdPropertyAction Action, enum rhdOutputProperty Property, union rhdPropertyData *val) |
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| 239 | { |
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| 240 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
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| 241 | |||
| 242 | RHDFUNC(Output); |
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| 243 | switch (Action) { |
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| 244 | case rhdPropertyCheck: |
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| 245 | switch (Property) { |
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| 246 | case RHD_OUTPUT_COHERENT: |
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| 247 | return TRUE; |
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| 248 | default: |
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| 249 | return FALSE; |
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| 250 | } |
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| 251 | case rhdPropertyGet: |
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| 252 | switch (Property) { |
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| 253 | case RHD_OUTPUT_COHERENT: |
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| 254 | val->Bool = Private->Coherent; |
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| 255 | return TRUE; |
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| 256 | break; |
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| 257 | default: |
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| 258 | return FALSE; |
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| 259 | } |
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| 260 | break; |
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| 261 | case rhdPropertySet: |
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| 262 | switch (Property) { |
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| 263 | case RHD_OUTPUT_COHERENT: |
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| 264 | Private->Coherent = val->Bool; |
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| 265 | Output->Mode(Output, Private->Mode); |
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| 266 | Output->Power(Output, RHD_POWER_ON); |
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| 267 | break; |
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| 268 | default: |
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| 269 | return FALSE; |
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| 270 | } |
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| 271 | break; |
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| 272 | } |
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| 273 | return TRUE; |
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| 274 | } |
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| 275 | |||
| 276 | /* |
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| 277 | * |
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| 278 | */ |
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| 279 | static void |
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| 280 | TMDSASet(struct rhdOutput *Output, DisplayModePtr Mode) |
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| 281 | { |
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| 282 | RHDPtr rhdPtr = RHDPTRI(Output); |
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| 283 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
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| 284 | |||
| 285 | RHDFUNC(Output); |
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| 286 | |||
| 287 | /* Clear out some HPD events first: this should be under driver control. */ |
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| 288 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x0000000C); |
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| 289 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00070000); |
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| 290 | RHDRegMask(Output, TMDSA_CNTL, 0, 0x00000010); |
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| 291 | |||
| 292 | /* Disable the transmitter */ |
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| 293 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001D1F); |
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| 294 | |||
| 295 | /* Disable bit reduction and reset temporal dither */ |
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| 296 | RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x00010101); |
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| 297 | if (rhdPtr->ChipSet < RHD_R600) { |
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| 298 | RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0x04000000, 0x04000000); |
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| 299 | usleep(2); |
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| 300 | RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x04000000); |
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| 301 | } else { |
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| 302 | RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0x02000000, 0x02000000); |
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| 303 | usleep(2); |
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| 304 | RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x02000000); |
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| 305 | } |
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| 306 | |||
| 307 | /* reset phase on vsync and use RGB */ |
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| 308 | RHDRegMask(Output, TMDSA_CNTL, 0x00001000, 0x00011000); |
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| 309 | |||
| 310 | /* Select CRTC, select syncA, no stereosync */ |
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| 311 | RHDRegMask(Output, TMDSA_SOURCE_SELECT, Output->Crtc->Id, 0x00010101); |
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| 312 | |||
| 313 | /* Single link, for now */ |
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| 314 | RHDRegWrite(Output, TMDSA_COLOR_FORMAT, 0); |
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| 315 | |||
| 316 | /* store this for TRANSMITTER_ENABLE in TMDSAPower */ |
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| 317 | Private->Mode = Mode; |
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| 318 | if (Mode->SynthClock > 165000) { |
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| 319 | RHDRegMask(Output, TMDSA_CNTL, 0x01000000, 0x01000000); |
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| 320 | Private->RunsDualLink = TRUE; /* for TRANSMITTER_ENABLE in TMDSAPower */ |
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| 321 | } else { |
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| 322 | RHDRegMask(Output, TMDSA_CNTL, 0, 0x01000000); |
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| 323 | Private->RunsDualLink = FALSE; |
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| 324 | } |
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| 325 | |||
| 326 | /* Disable force data */ |
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| 327 | RHDRegMask(Output, TMDSA_FORCE_OUTPUT_CNTL, 0, 0x00000001); |
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| 328 | |||
| 329 | /* DC balancer enable */ |
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| 330 | RHDRegMask(Output, TMDSA_DCBALANCER_CONTROL, 0x00000001, 0x00000001); |
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| 331 | |||
| 332 | TMDSAVoltageControl(Output); |
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| 333 | |||
| 334 | /* use IDCLK */ |
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| 335 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000010, 0x00000010); |
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| 336 | |||
| 337 | if (Private->Coherent) |
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| 338 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000000, 0x10000000); |
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| 339 | else |
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| 340 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x10000000, 0x10000000); |
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| 341 | |||
| 342 | RHDHdmiSetMode(Private->Hdmi, Mode); |
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| 343 | } |
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| 344 | |||
| 345 | /* |
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| 346 | * |
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| 347 | */ |
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| 348 | static void |
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| 349 | TMDSAPower(struct rhdOutput *Output, int Power) |
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| 350 | { |
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| 351 | RHDPtr rhdPtr = RHDPTRI(Output); |
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| 352 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
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| 353 | |||
| 354 | RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name, |
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| 355 | rhdPowerString[Power]); |
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| 356 | |||
| 357 | switch (Power) { |
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| 358 | case RHD_POWER_ON: |
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| 359 | if (Private->PowerState == RHD_POWER_SHUTDOWN |
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| 360 | || Private->PowerState == RHD_POWER_UNKNOWN) { |
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| 361 | RHDRegMask(Output, TMDSA_CNTL, 0x1, 0x00000001); |
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| 362 | |||
| 363 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000001, 0x00000001); |
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| 364 | usleep(20); |
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| 365 | |||
| 366 | /* reset transmitter PLL */ |
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| 367 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002); |
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| 368 | usleep(2); |
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| 369 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000002); |
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| 370 | |||
| 371 | usleep(30); |
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| 372 | |||
| 373 | /* restart data synchronisation */ |
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| 374 | if (rhdPtr->ChipSet < RHD_R600) { |
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| 375 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0x00000001, 0x00000001); |
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| 376 | usleep(2); |
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| 377 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0x00000100, 0x00000100); |
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| 378 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0, 0x00000001); |
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| 379 | } else { |
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| 380 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0x00000001, 0x00000001); |
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| 381 | usleep(2); |
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| 382 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0x00000100, 0x00000100); |
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| 383 | RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0, 0x00000001); |
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| 384 | } |
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| 385 | } |
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| 386 | |||
| 387 | if (Private->RunsDualLink) { |
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| 388 | /* bit 9 is not known by anything below RV610, but is ignored by |
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| 389 | the hardware anyway */ |
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| 390 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x00001F1F, 0x00001F1F); |
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| 391 | } else |
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| 392 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x0000001F, 0x00001F1F); |
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| 393 | |||
| 394 | if(Output->Connector != NULL && RHDConnectorEnableHDMI(Output->Connector)) |
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| 395 | RHDHdmiEnable(Private->Hdmi, TRUE); |
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| 396 | else |
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| 397 | RHDHdmiEnable(Private->Hdmi, FALSE); |
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| 398 | Private->PowerState = RHD_POWER_ON; |
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| 399 | return; |
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| 400 | |||
| 401 | case RHD_POWER_RESET: |
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| 402 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F); |
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| 403 | /* if we do a RESET after a SHUTDOWN don't raise the power level, |
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| 404 | * and similarly, don't raise from UNKNOWN state. */ |
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| 405 | if (Private->PowerState == RHD_POWER_ON) |
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| 406 | Private->PowerState = RHD_POWER_RESET; |
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| 407 | return; |
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| 408 | |||
| 409 | case RHD_POWER_SHUTDOWN: |
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| 410 | default: |
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| 411 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002); |
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| 412 | usleep(2); |
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| 413 | RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000001); |
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| 414 | RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F); |
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| 415 | RHDRegMask(Output, TMDSA_CNTL, 0, 0x00000001); |
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| 416 | RHDHdmiEnable(Private->Hdmi, FALSE); |
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| 417 | Private->PowerState = RHD_POWER_SHUTDOWN; |
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| 418 | return; |
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| 419 | } |
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| 420 | } |
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| 421 | |||
| 422 | /* |
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| 423 | * |
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| 424 | */ |
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| 425 | static void |
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| 426 | TMDSASave(struct rhdOutput *Output) |
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| 427 | { |
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| 428 | int ChipSet = RHDPTRI(Output)->ChipSet; |
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| 429 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
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| 430 | |||
| 431 | RHDFUNC(Output); |
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| 432 | |||
| 433 | Private->StoreControl = RHDRegRead(Output, TMDSA_CNTL); |
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| 434 | Private->StoreSource = RHDRegRead(Output, TMDSA_SOURCE_SELECT); |
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| 435 | Private->StoreFormat = RHDRegRead(Output, TMDSA_COLOR_FORMAT); |
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| 436 | Private->StoreForce = RHDRegRead(Output, TMDSA_FORCE_OUTPUT_CNTL); |
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| 437 | Private->StoreReduction = RHDRegRead(Output, TMDSA_BIT_DEPTH_CONTROL); |
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| 438 | Private->StoreDCBalancer = RHDRegRead(Output, TMDSA_DCBALANCER_CONTROL); |
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| 439 | |||
| 440 | if (ChipSet < RHD_R600) |
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| 441 | Private->StoreDataSynchro = RHDRegRead(Output, TMDSA_DATA_SYNCHRONIZATION_R500); |
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| 442 | else |
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| 443 | Private->StoreDataSynchro = RHDRegRead(Output, TMDSA_DATA_SYNCHRONIZATION_R600); |
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| 444 | |||
| 445 | Private->StoreTXEnable = RHDRegRead(Output, TMDSA_TRANSMITTER_ENABLE); |
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| 446 | Private->StoreMacro = RHDRegRead(Output, TMDSA_MACRO_CONTROL); |
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| 447 | Private->StoreTXControl = RHDRegRead(Output, TMDSA_TRANSMITTER_CONTROL); |
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| 448 | |||
| 449 | if (ChipSet >= RHD_RV610) |
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| 450 | Private->StoreTXAdjust = RHDRegRead(Output, TMDSA_TRANSMITTER_ADJUST); |
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| 451 | |||
| 452 | RHDHdmiSave(Private->Hdmi); |
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| 453 | |||
| 454 | Private->Stored = TRUE; |
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| 455 | } |
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| 456 | |||
| 457 | /* |
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| 458 | * |
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| 459 | */ |
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| 460 | static void |
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| 461 | TMDSARestore(struct rhdOutput *Output) |
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| 462 | { |
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| 463 | int ChipSet = RHDPTRI(Output)->ChipSet; |
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| 464 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
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| 465 | |||
| 466 | RHDFUNC(Output); |
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| 467 | |||
| 468 | if (!Private->Stored) { |
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| 469 | xf86DrvMsg(Output->scrnIndex, X_ERROR, |
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| 470 | "%s: No registers stored.\n", __func__); |
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| 471 | return; |
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| 472 | } |
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| 473 | |||
| 474 | RHDRegWrite(Output, TMDSA_CNTL, Private->StoreControl); |
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| 475 | RHDRegWrite(Output, TMDSA_SOURCE_SELECT, Private->StoreSource); |
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| 476 | RHDRegWrite(Output, TMDSA_COLOR_FORMAT, Private->StoreFormat); |
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| 477 | RHDRegWrite(Output, TMDSA_FORCE_OUTPUT_CNTL, Private->StoreForce); |
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| 478 | RHDRegWrite(Output, TMDSA_BIT_DEPTH_CONTROL, Private->StoreReduction); |
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| 479 | RHDRegWrite(Output, TMDSA_DCBALANCER_CONTROL, Private->StoreDCBalancer); |
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| 480 | |||
| 481 | if (ChipSet < RHD_R600) |
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| 482 | RHDRegWrite(Output, TMDSA_DATA_SYNCHRONIZATION_R500, Private->StoreDataSynchro); |
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| 483 | else |
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| 484 | RHDRegWrite(Output, TMDSA_DATA_SYNCHRONIZATION_R600, Private->StoreDataSynchro); |
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| 485 | |||
| 486 | RHDRegWrite(Output, TMDSA_TRANSMITTER_ENABLE, Private->StoreTXEnable); |
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| 487 | RHDRegWrite(Output, TMDSA_MACRO_CONTROL, Private->StoreMacro); |
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| 488 | RHDRegWrite(Output, TMDSA_TRANSMITTER_CONTROL, Private->StoreTXControl); |
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| 489 | |||
| 490 | if (ChipSet >= RHD_RV610) |
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| 491 | RHDRegWrite(Output, TMDSA_TRANSMITTER_ADJUST, Private->StoreTXAdjust); |
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| 492 | |||
| 493 | RHDHdmiRestore(Private->Hdmi); |
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| 494 | } |
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| 495 | |||
| 496 | /* |
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| 497 | * |
||
| 498 | */ |
||
| 499 | static void |
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| 500 | TMDSADestroy(struct rhdOutput *Output) |
||
| 501 | { |
||
| 502 | struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private; |
||
| 503 | RHDFUNC(Output); |
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| 504 | |||
| 505 | if (!Private) |
||
| 506 | return; |
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| 507 | |||
| 508 | RHDHdmiDestroy(Private->Hdmi); |
||
| 509 | |||
| 510 | xfree(Private); |
||
| 511 | Output->Private = NULL; |
||
| 512 | } |
||
| 513 | |||
| 514 | /* |
||
| 515 | * |
||
| 516 | */ |
||
| 517 | struct rhdOutput * |
||
| 518 | RHDTMDSAInit(RHDPtr rhdPtr) |
||
| 519 | { |
||
| 520 | struct rhdOutput *Output; |
||
| 521 | struct rhdTMDSPrivate *Private; |
||
| 522 | |||
| 523 | RHDFUNC(rhdPtr); |
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| 524 | |||
| 525 | Output = xnfcalloc(sizeof(struct rhdOutput), 1); |
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| 526 | |||
| 527 | Output->scrnIndex = rhdPtr->scrnIndex; |
||
| 528 | Output->Name = "TMDS A"; |
||
| 529 | Output->Id = RHD_OUTPUT_TMDSA; |
||
| 530 | |||
| 531 | Output->Sense = TMDSASense; |
||
| 532 | Output->ModeValid = TMDSAModeValid; |
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| 533 | Output->Mode = TMDSASet; |
||
| 534 | Output->Power = TMDSAPower; |
||
| 535 | Output->Save = TMDSASave; |
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| 536 | Output->Restore = TMDSARestore; |
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| 537 | Output->Destroy = TMDSADestroy; |
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| 538 | Output->Property = TMDSAPropertyControl; |
||
| 539 | |||
| 540 | Private = xnfcalloc(sizeof(struct rhdTMDSPrivate), 1); |
||
| 541 | Private->RunsDualLink = FALSE; |
||
| 542 | Private->Coherent = FALSE; |
||
| 543 | Private->PowerState = RHD_POWER_UNKNOWN; |
||
| 544 | |||
| 545 | Output->Private = Private; |
||
| 546 | |||
| 547 | return Output; |
||
| 548 | } |