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Rev | Author | Line No. | Line |
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4075 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | #define mb() asm volatile("mfence" : : : "memory") |
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4080 | Serge | 28 | #define rmb() asm volatile("lfence" : : : "memory") |
29 | #define wmb() asm volatile("sfence" : : : "memory") |
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30 | |||
4075 | Serge | 31 | #include "vmwgfx_drv.h" |
32 | #include |
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33 | #include |
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34 | |||
35 | #define TASK_INTERRUPTIBLE 1 |
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36 | #define TASK_UNINTERRUPTIBLE 2 |
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37 | |||
38 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
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39 | { |
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40 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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41 | uint32_t fifo_min, hwversion; |
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42 | const struct vmw_fifo_state *fifo = &dev_priv->fifo; |
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43 | |||
4569 | Serge | 44 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) |
45 | return false; |
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46 | |||
47 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
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48 | uint32_t result; |
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49 | |||
50 | if (!dev_priv->has_mob) |
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51 | return false; |
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52 | |||
53 | mutex_lock(&dev_priv->hw_mutex); |
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54 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); |
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55 | result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
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56 | mutex_unlock(&dev_priv->hw_mutex); |
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57 | |||
58 | return (result != 0); |
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59 | } |
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60 | |||
4075 | Serge | 61 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
62 | return false; |
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63 | |||
64 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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65 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
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66 | return false; |
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67 | |||
68 | hwversion = ioread32(fifo_mem + |
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69 | ((fifo->capabilities & |
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70 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? |
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71 | SVGA_FIFO_3D_HWVERSION_REVISED : |
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72 | SVGA_FIFO_3D_HWVERSION)); |
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73 | |||
74 | if (hwversion == 0) |
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75 | return false; |
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76 | |||
77 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
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78 | return false; |
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79 | |||
80 | /* Non-Screen Object path does not support surfaces */ |
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81 | if (!dev_priv->sou_priv) |
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82 | return false; |
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83 | |||
84 | return true; |
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85 | } |
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86 | |||
87 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
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88 | { |
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89 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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90 | uint32_t caps; |
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91 | |||
92 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
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93 | return false; |
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94 | |||
95 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
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96 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
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97 | return true; |
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98 | |||
99 | return false; |
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100 | } |
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101 | |||
102 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
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103 | { |
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104 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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105 | uint32_t max; |
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106 | uint32_t min; |
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107 | uint32_t dummy; |
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4080 | Serge | 108 | |
4075 | Serge | 109 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
110 | fifo->static_buffer = KernelAlloc(fifo->static_buffer_size); |
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111 | if (unlikely(fifo->static_buffer == NULL)) |
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112 | return -ENOMEM; |
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113 | |||
114 | fifo->dynamic_buffer = NULL; |
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115 | fifo->reserved_size = 0; |
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116 | fifo->using_bounce_buffer = false; |
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117 | |||
118 | mutex_init(&fifo->fifo_mutex); |
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119 | // init_rwsem(&fifo->rwsem); |
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120 | |||
121 | /* |
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122 | * Allow mapping the first page read-only to user-space. |
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123 | */ |
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124 | |||
125 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
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126 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); |
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127 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); |
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128 | |||
129 | mutex_lock(&dev_priv->hw_mutex); |
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130 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
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131 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); |
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132 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
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133 | vmw_write(dev_priv, SVGA_REG_ENABLE, 1); |
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134 | |||
135 | min = 4; |
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136 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) |
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137 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); |
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138 | min <<= 2; |
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139 | |||
140 | if (min < PAGE_SIZE) |
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141 | min = PAGE_SIZE; |
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142 | |||
143 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); |
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144 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); |
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145 | wmb(); |
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146 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
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147 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); |
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148 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); |
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149 | mb(); |
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150 | |||
151 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); |
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152 | mutex_unlock(&dev_priv->hw_mutex); |
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153 | |||
154 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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155 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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156 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
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157 | |||
158 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", |
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159 | (unsigned int) max, |
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160 | (unsigned int) min, |
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161 | (unsigned int) fifo->capabilities); |
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162 | |||
163 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
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164 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
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165 | vmw_marker_queue_init(&fifo->marker_queue); |
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4080 | Serge | 166 | |
167 | int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy); |
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168 | return ret; |
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4075 | Serge | 169 | } |
170 | |||
171 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
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172 | { |
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173 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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174 | |||
175 | mutex_lock(&dev_priv->hw_mutex); |
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176 | |||
177 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { |
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178 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); |
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179 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); |
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180 | } |
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181 | |||
182 | mutex_unlock(&dev_priv->hw_mutex); |
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183 | } |
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184 | |||
185 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
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186 | { |
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187 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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188 | |||
189 | mutex_lock(&dev_priv->hw_mutex); |
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190 | |||
191 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
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192 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
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193 | |||
194 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
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195 | |||
196 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, |
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197 | dev_priv->config_done_state); |
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198 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
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199 | dev_priv->enable_state); |
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200 | vmw_write(dev_priv, SVGA_REG_TRACES, |
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201 | dev_priv->traces_state); |
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202 | |||
203 | mutex_unlock(&dev_priv->hw_mutex); |
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204 | vmw_marker_queue_takedown(&fifo->marker_queue); |
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205 | |||
206 | if (likely(fifo->static_buffer != NULL)) { |
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207 | vfree(fifo->static_buffer); |
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208 | fifo->static_buffer = NULL; |
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209 | } |
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210 | |||
211 | if (likely(fifo->dynamic_buffer != NULL)) { |
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212 | vfree(fifo->dynamic_buffer); |
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213 | fifo->dynamic_buffer = NULL; |
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214 | } |
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215 | } |
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216 | |||
217 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) |
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218 | { |
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219 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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220 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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221 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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222 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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223 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
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224 | |||
225 | return ((max - next_cmd) + (stop - min) <= bytes); |
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226 | } |
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227 | |||
228 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, |
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229 | uint32_t bytes, bool interruptible, |
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230 | unsigned long timeout) |
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231 | { |
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232 | int ret = 0; |
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5078 | serge | 233 | unsigned long end_jiffies = jiffies + timeout; |
4570 | Serge | 234 | // DEFINE_WAIT(__wait); |
4075 | Serge | 235 | |
236 | DRM_INFO("Fifo wait noirq.\n"); |
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237 | |||
238 | for (;;) { |
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239 | // prepare_to_wait(&dev_priv->fifo_queue, &__wait, |
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240 | // (interruptible) ? |
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241 | // TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
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242 | if (!vmw_fifo_is_full(dev_priv, bytes)) |
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243 | break; |
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5078 | serge | 244 | if (time_after_eq(jiffies, end_jiffies)) { |
4075 | Serge | 245 | ret = -EBUSY; |
246 | DRM_ERROR("SVGA device lockup.\n"); |
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247 | break; |
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248 | } |
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249 | delay(1); |
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250 | } |
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251 | // finish_wait(&dev_priv->fifo_queue, &__wait); |
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252 | wake_up_all(&dev_priv->fifo_queue); |
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253 | DRM_INFO("Fifo noirq exit.\n"); |
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254 | return ret; |
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255 | } |
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256 | |||
257 | static int vmw_fifo_wait(struct vmw_private *dev_priv, |
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258 | uint32_t bytes, bool interruptible, |
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259 | unsigned long timeout) |
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260 | { |
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261 | long ret = 1L; |
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262 | unsigned long irq_flags; |
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263 | |||
264 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) |
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265 | return 0; |
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266 | |||
267 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); |
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268 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
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269 | return vmw_fifo_wait_noirq(dev_priv, bytes, |
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270 | interruptible, timeout); |
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271 | |||
272 | mutex_lock(&dev_priv->hw_mutex); |
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273 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
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274 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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275 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, |
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276 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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277 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
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278 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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279 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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280 | } |
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281 | mutex_unlock(&dev_priv->hw_mutex); |
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282 | |||
283 | if (interruptible) |
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284 | ret = wait_event_interruptible_timeout |
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285 | (dev_priv->fifo_queue, |
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286 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
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287 | else |
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288 | ret = wait_event_timeout |
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289 | (dev_priv->fifo_queue, |
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290 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
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291 | |||
292 | if (unlikely(ret == 0)) |
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293 | ret = -EBUSY; |
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294 | else if (likely(ret > 0)) |
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295 | ret = 0; |
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296 | |||
297 | mutex_lock(&dev_priv->hw_mutex); |
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298 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
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299 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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300 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
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301 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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302 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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303 | } |
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304 | mutex_unlock(&dev_priv->hw_mutex); |
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305 | |||
306 | return ret; |
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307 | } |
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308 | |||
309 | /** |
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310 | * Reserve @bytes number of bytes in the fifo. |
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311 | * |
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312 | * This function will return NULL (error) on two conditions: |
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313 | * If it timeouts waiting for fifo space, or if @bytes is larger than the |
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314 | * available fifo space. |
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315 | * |
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316 | * Returns: |
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317 | * Pointer to the fifo, or null on error (possible hardware hang). |
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318 | */ |
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319 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
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320 | { |
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321 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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322 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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323 | uint32_t max; |
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324 | uint32_t min; |
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325 | uint32_t next_cmd; |
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326 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
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327 | int ret; |
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328 | |||
329 | mutex_lock(&fifo_state->fifo_mutex); |
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330 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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331 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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332 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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333 | |||
334 | if (unlikely(bytes >= (max - min))) |
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335 | goto out_err; |
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336 | |||
337 | BUG_ON(fifo_state->reserved_size != 0); |
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338 | BUG_ON(fifo_state->dynamic_buffer != NULL); |
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339 | |||
340 | fifo_state->reserved_size = bytes; |
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341 | |||
342 | while (1) { |
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343 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
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344 | bool need_bounce = false; |
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345 | bool reserve_in_place = false; |
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346 | |||
347 | if (next_cmd >= stop) { |
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348 | if (likely((next_cmd + bytes < max || |
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349 | (next_cmd + bytes == max && stop > min)))) |
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350 | reserve_in_place = true; |
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351 | |||
352 | else if (vmw_fifo_is_full(dev_priv, bytes)) { |
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353 | ret = vmw_fifo_wait(dev_priv, bytes, |
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354 | false, 3 * HZ); |
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355 | if (unlikely(ret != 0)) |
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356 | goto out_err; |
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357 | } else |
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358 | need_bounce = true; |
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359 | |||
360 | } else { |
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361 | |||
362 | if (likely((next_cmd + bytes < stop))) |
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363 | reserve_in_place = true; |
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364 | else { |
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365 | ret = vmw_fifo_wait(dev_priv, bytes, |
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366 | false, 3 * HZ); |
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367 | if (unlikely(ret != 0)) |
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368 | goto out_err; |
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369 | } |
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370 | } |
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371 | |||
372 | if (reserve_in_place) { |
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373 | if (reserveable || bytes <= sizeof(uint32_t)) { |
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374 | fifo_state->using_bounce_buffer = false; |
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375 | |||
376 | if (reserveable) |
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377 | iowrite32(bytes, fifo_mem + |
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378 | SVGA_FIFO_RESERVED); |
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379 | return fifo_mem + (next_cmd >> 2); |
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380 | } else { |
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381 | need_bounce = true; |
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382 | } |
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383 | } |
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384 | |||
385 | if (need_bounce) { |
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386 | fifo_state->using_bounce_buffer = true; |
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387 | if (bytes < fifo_state->static_buffer_size) |
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388 | return fifo_state->static_buffer; |
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389 | else { |
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390 | fifo_state->dynamic_buffer = kmalloc(bytes,0); |
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391 | return fifo_state->dynamic_buffer; |
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392 | } |
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393 | } |
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394 | } |
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395 | out_err: |
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396 | fifo_state->reserved_size = 0; |
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397 | mutex_unlock(&fifo_state->fifo_mutex); |
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398 | return NULL; |
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399 | } |
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400 | |||
401 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
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402 | __le32 __iomem *fifo_mem, |
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403 | uint32_t next_cmd, |
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404 | uint32_t max, uint32_t min, uint32_t bytes) |
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405 | { |
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406 | uint32_t chunk_size = max - next_cmd; |
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407 | uint32_t rest; |
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408 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
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409 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
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410 | |||
411 | if (bytes < chunk_size) |
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412 | chunk_size = bytes; |
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413 | |||
414 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
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4080 | Serge | 415 | mb(); |
4075 | Serge | 416 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
417 | rest = bytes - chunk_size; |
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418 | if (rest) |
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419 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
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420 | rest); |
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421 | } |
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422 | |||
423 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
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424 | __le32 __iomem *fifo_mem, |
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425 | uint32_t next_cmd, |
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426 | uint32_t max, uint32_t min, uint32_t bytes) |
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427 | { |
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428 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
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429 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
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430 | |||
431 | while (bytes > 0) { |
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432 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); |
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433 | next_cmd += sizeof(uint32_t); |
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434 | if (unlikely(next_cmd == max)) |
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435 | next_cmd = min; |
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436 | mb(); |
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437 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
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438 | mb(); |
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439 | bytes -= sizeof(uint32_t); |
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440 | } |
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441 | } |
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442 | |||
443 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
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444 | { |
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445 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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446 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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447 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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448 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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449 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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450 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
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451 | |||
452 | BUG_ON((bytes & 3) != 0); |
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453 | BUG_ON(bytes > fifo_state->reserved_size); |
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454 | |||
455 | fifo_state->reserved_size = 0; |
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456 | |||
457 | if (fifo_state->using_bounce_buffer) { |
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458 | if (reserveable) |
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459 | vmw_fifo_res_copy(fifo_state, fifo_mem, |
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460 | next_cmd, max, min, bytes); |
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461 | else |
||
462 | vmw_fifo_slow_copy(fifo_state, fifo_mem, |
||
463 | next_cmd, max, min, bytes); |
||
464 | |||
465 | if (fifo_state->dynamic_buffer) { |
||
466 | vfree(fifo_state->dynamic_buffer); |
||
467 | fifo_state->dynamic_buffer = NULL; |
||
468 | } |
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469 | |||
470 | } |
||
471 | |||
472 | // down_write(&fifo_state->rwsem); |
||
473 | if (fifo_state->using_bounce_buffer || reserveable) { |
||
474 | next_cmd += bytes; |
||
475 | if (next_cmd >= max) |
||
476 | next_cmd -= max - min; |
||
477 | mb(); |
||
478 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
||
479 | } |
||
480 | |||
481 | if (reserveable) |
||
482 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
||
4080 | Serge | 483 | mb(); |
4075 | Serge | 484 | // up_write(&fifo_state->rwsem); |
485 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
||
486 | mutex_unlock(&fifo_state->fifo_mutex); |
||
487 | } |
||
488 | |||
489 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
||
490 | { |
||
491 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
||
492 | struct svga_fifo_cmd_fence *cmd_fence; |
||
493 | void *fm; |
||
494 | int ret = 0; |
||
495 | uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence); |
||
496 | |||
497 | fm = vmw_fifo_reserve(dev_priv, bytes); |
||
498 | if (unlikely(fm == NULL)) { |
||
499 | *seqno = atomic_read(&dev_priv->marker_seq); |
||
500 | ret = -ENOMEM; |
||
501 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
||
502 | false, 3*HZ); |
||
503 | goto out_err; |
||
504 | } |
||
505 | |||
506 | do { |
||
507 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
||
508 | } while (*seqno == 0); |
||
509 | |||
510 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { |
||
511 | |||
512 | /* |
||
513 | * Don't request hardware to send a fence. The |
||
514 | * waiting code in vmwgfx_irq.c will emulate this. |
||
515 | */ |
||
516 | |||
517 | vmw_fifo_commit(dev_priv, 0); |
||
518 | return 0; |
||
519 | } |
||
520 | |||
521 | *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE); |
||
522 | cmd_fence = (struct svga_fifo_cmd_fence *) |
||
523 | ((unsigned long)fm + sizeof(__le32)); |
||
524 | |||
525 | iowrite32(*seqno, &cmd_fence->fence); |
||
526 | vmw_fifo_commit(dev_priv, bytes); |
||
527 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
||
528 | vmw_update_seqno(dev_priv, fifo_state); |
||
529 | |||
530 | out_err: |
||
531 | return ret; |
||
532 | } |
||
533 | |||
534 | /** |
||
4569 | Serge | 535 | * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using |
536 | * legacy query commands. |
||
4075 | Serge | 537 | * |
538 | * @dev_priv: The device private structure. |
||
539 | * @cid: The hardware context id used for the query. |
||
540 | * |
||
4569 | Serge | 541 | * See the vmw_fifo_emit_dummy_query documentation. |
4075 | Serge | 542 | */ |
4569 | Serge | 543 | static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, |
4075 | Serge | 544 | uint32_t cid) |
545 | { |
||
546 | /* |
||
547 | * A query wait without a preceding query end will |
||
548 | * actually finish all queries for this cid |
||
549 | * without writing to the query result structure. |
||
550 | */ |
||
551 | |||
552 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; |
||
553 | struct { |
||
554 | SVGA3dCmdHeader header; |
||
555 | SVGA3dCmdWaitForQuery body; |
||
556 | } *cmd; |
||
557 | |||
558 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); |
||
559 | |||
560 | if (unlikely(cmd == NULL)) { |
||
561 | DRM_ERROR("Out of fifo space for dummy query.\n"); |
||
562 | return -ENOMEM; |
||
563 | } |
||
564 | |||
565 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY; |
||
566 | cmd->header.size = sizeof(cmd->body); |
||
567 | cmd->body.cid = cid; |
||
568 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; |
||
569 | |||
570 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
||
571 | cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER; |
||
572 | cmd->body.guestResult.offset = bo->offset; |
||
573 | } else { |
||
574 | cmd->body.guestResult.gmrId = bo->mem.start; |
||
575 | cmd->body.guestResult.offset = 0; |
||
576 | } |
||
577 | |||
578 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); |
||
579 | |||
580 | return 0; |
||
581 | } |
||
4569 | Serge | 582 | |
583 | /** |
||
584 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using |
||
585 | * guest-backed resource query commands. |
||
586 | * |
||
587 | * @dev_priv: The device private structure. |
||
588 | * @cid: The hardware context id used for the query. |
||
589 | * |
||
590 | * See the vmw_fifo_emit_dummy_query documentation. |
||
591 | */ |
||
592 | static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, |
||
593 | uint32_t cid) |
||
594 | { |
||
595 | /* |
||
596 | * A query wait without a preceding query end will |
||
597 | * actually finish all queries for this cid |
||
598 | * without writing to the query result structure. |
||
599 | */ |
||
600 | |||
601 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; |
||
602 | struct { |
||
603 | SVGA3dCmdHeader header; |
||
604 | SVGA3dCmdWaitForGBQuery body; |
||
605 | } *cmd; |
||
606 | |||
607 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); |
||
608 | |||
609 | if (unlikely(cmd == NULL)) { |
||
610 | DRM_ERROR("Out of fifo space for dummy query.\n"); |
||
611 | return -ENOMEM; |
||
612 | } |
||
613 | |||
614 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY; |
||
615 | cmd->header.size = sizeof(cmd->body); |
||
616 | cmd->body.cid = cid; |
||
617 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; |
||
618 | BUG_ON(bo->mem.mem_type != VMW_PL_MOB); |
||
619 | cmd->body.mobid = bo->mem.start; |
||
620 | cmd->body.offset = 0; |
||
621 | |||
622 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); |
||
623 | |||
624 | return 0; |
||
625 | } |
||
626 | |||
627 | |||
628 | /** |
||
629 | * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using |
||
630 | * appropriate resource query commands. |
||
631 | * |
||
632 | * @dev_priv: The device private structure. |
||
633 | * @cid: The hardware context id used for the query. |
||
634 | * |
||
635 | * This function is used to emit a dummy occlusion query with |
||
636 | * no primitives rendered between query begin and query end. |
||
637 | * It's used to provide a query barrier, in order to know that when |
||
638 | * this query is finished, all preceding queries are also finished. |
||
639 | * |
||
640 | * A Query results structure should have been initialized at the start |
||
641 | * of the dev_priv->dummy_query_bo buffer object. And that buffer object |
||
642 | * must also be either reserved or pinned when this function is called. |
||
643 | * |
||
644 | * Returns -ENOMEM on failure to reserve fifo space. |
||
645 | */ |
||
646 | int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, |
||
647 | uint32_t cid) |
||
648 | { |
||
649 | if (dev_priv->has_mob) |
||
650 | return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); |
||
651 | |||
652 | return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); |
||
653 | }>>=>>>=>>=><=>>=> |