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4075 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | #define mb() asm volatile("mfence" : : : "memory") |
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28 | #define rmb() asm volatile("lfence" : : : "memory") |
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29 | #define wmb() asm volatile("sfence" : : : "memory") |
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30 | |||
31 | #include "vmwgfx_drv.h" |
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32 | #include |
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33 | #include |
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34 | |||
35 | #define TASK_INTERRUPTIBLE 1 |
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36 | #define TASK_UNINTERRUPTIBLE 2 |
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37 | |||
38 | bool vmw_fifo_have_3d(struct vmw_private *dev_priv) |
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39 | { |
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40 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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41 | uint32_t fifo_min, hwversion; |
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42 | const struct vmw_fifo_state *fifo = &dev_priv->fifo; |
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43 | |||
44 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
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45 | return false; |
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46 | |||
47 | fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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48 | if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) |
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49 | return false; |
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50 | |||
51 | hwversion = ioread32(fifo_mem + |
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52 | ((fifo->capabilities & |
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53 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? |
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54 | SVGA_FIFO_3D_HWVERSION_REVISED : |
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55 | SVGA_FIFO_3D_HWVERSION)); |
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56 | |||
57 | if (hwversion == 0) |
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58 | return false; |
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59 | |||
60 | if (hwversion < SVGA3D_HWVERSION_WS8_B1) |
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61 | return false; |
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62 | |||
63 | /* Non-Screen Object path does not support surfaces */ |
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64 | if (!dev_priv->sou_priv) |
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65 | return false; |
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66 | |||
67 | return true; |
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68 | } |
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69 | |||
70 | bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) |
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71 | { |
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72 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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73 | uint32_t caps; |
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74 | |||
75 | if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) |
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76 | return false; |
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77 | |||
78 | caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
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79 | if (caps & SVGA_FIFO_CAP_PITCHLOCK) |
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80 | return true; |
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81 | |||
82 | return false; |
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83 | } |
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84 | |||
85 | int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
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86 | { |
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87 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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88 | uint32_t max; |
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89 | uint32_t min; |
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90 | uint32_t dummy; |
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91 | |||
92 | ENTER(); |
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93 | |||
94 | fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; |
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95 | fifo->static_buffer = KernelAlloc(fifo->static_buffer_size); |
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96 | if (unlikely(fifo->static_buffer == NULL)) |
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97 | return -ENOMEM; |
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98 | |||
99 | fifo->dynamic_buffer = NULL; |
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100 | fifo->reserved_size = 0; |
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101 | fifo->using_bounce_buffer = false; |
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102 | |||
103 | mutex_init(&fifo->fifo_mutex); |
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104 | // init_rwsem(&fifo->rwsem); |
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105 | |||
106 | /* |
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107 | * Allow mapping the first page read-only to user-space. |
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108 | */ |
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109 | |||
110 | DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); |
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111 | DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); |
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112 | DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); |
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113 | |||
114 | mutex_lock(&dev_priv->hw_mutex); |
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115 | dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); |
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116 | dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); |
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117 | dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); |
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118 | vmw_write(dev_priv, SVGA_REG_ENABLE, 1); |
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119 | |||
120 | min = 4; |
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121 | if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) |
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122 | min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); |
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123 | min <<= 2; |
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124 | |||
125 | if (min < PAGE_SIZE) |
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126 | min = PAGE_SIZE; |
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127 | |||
128 | iowrite32(min, fifo_mem + SVGA_FIFO_MIN); |
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129 | iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); |
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130 | wmb(); |
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131 | iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); |
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132 | iowrite32(min, fifo_mem + SVGA_FIFO_STOP); |
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133 | iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); |
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134 | mb(); |
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135 | |||
136 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); |
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137 | mutex_unlock(&dev_priv->hw_mutex); |
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138 | |||
139 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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140 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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141 | fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); |
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142 | |||
143 | DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", |
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144 | (unsigned int) max, |
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145 | (unsigned int) min, |
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146 | (unsigned int) fifo->capabilities); |
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147 | |||
148 | atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); |
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149 | iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); |
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150 | vmw_marker_queue_init(&fifo->marker_queue); |
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151 | |||
152 | int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy); |
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153 | LEAVE(); |
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154 | return ret; |
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155 | } |
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156 | |||
157 | void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) |
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158 | { |
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159 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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160 | |||
161 | mutex_lock(&dev_priv->hw_mutex); |
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162 | |||
163 | if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { |
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164 | iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); |
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165 | vmw_write(dev_priv, SVGA_REG_SYNC, reason); |
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166 | } |
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167 | |||
168 | mutex_unlock(&dev_priv->hw_mutex); |
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169 | } |
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170 | |||
171 | void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) |
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172 | { |
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173 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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174 | |||
175 | mutex_lock(&dev_priv->hw_mutex); |
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176 | |||
177 | while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) |
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178 | vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); |
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179 | |||
180 | dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); |
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181 | |||
182 | vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, |
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183 | dev_priv->config_done_state); |
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184 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
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185 | dev_priv->enable_state); |
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186 | vmw_write(dev_priv, SVGA_REG_TRACES, |
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187 | dev_priv->traces_state); |
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188 | |||
189 | mutex_unlock(&dev_priv->hw_mutex); |
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190 | vmw_marker_queue_takedown(&fifo->marker_queue); |
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191 | |||
192 | if (likely(fifo->static_buffer != NULL)) { |
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193 | vfree(fifo->static_buffer); |
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194 | fifo->static_buffer = NULL; |
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195 | } |
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196 | |||
197 | if (likely(fifo->dynamic_buffer != NULL)) { |
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198 | vfree(fifo->dynamic_buffer); |
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199 | fifo->dynamic_buffer = NULL; |
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200 | } |
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201 | } |
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202 | |||
203 | static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) |
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204 | { |
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205 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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206 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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207 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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208 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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209 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
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210 | |||
211 | return ((max - next_cmd) + (stop - min) <= bytes); |
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212 | } |
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213 | |||
214 | static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, |
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215 | uint32_t bytes, bool interruptible, |
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216 | unsigned long timeout) |
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217 | { |
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218 | int ret = 0; |
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219 | unsigned long end_jiffies = GetTimerTicks() + timeout; |
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220 | DEFINE_WAIT(__wait); |
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221 | |||
222 | DRM_INFO("Fifo wait noirq.\n"); |
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223 | |||
224 | for (;;) { |
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225 | // prepare_to_wait(&dev_priv->fifo_queue, &__wait, |
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226 | // (interruptible) ? |
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227 | // TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
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228 | if (!vmw_fifo_is_full(dev_priv, bytes)) |
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229 | break; |
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230 | if (time_after_eq(GetTimerTicks(), end_jiffies)) { |
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231 | ret = -EBUSY; |
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232 | DRM_ERROR("SVGA device lockup.\n"); |
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233 | break; |
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234 | } |
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235 | delay(1); |
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236 | } |
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237 | // finish_wait(&dev_priv->fifo_queue, &__wait); |
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238 | wake_up_all(&dev_priv->fifo_queue); |
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239 | DRM_INFO("Fifo noirq exit.\n"); |
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240 | return ret; |
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241 | } |
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242 | |||
243 | static int vmw_fifo_wait(struct vmw_private *dev_priv, |
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244 | uint32_t bytes, bool interruptible, |
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245 | unsigned long timeout) |
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246 | { |
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247 | long ret = 1L; |
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248 | unsigned long irq_flags; |
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249 | |||
250 | if (likely(!vmw_fifo_is_full(dev_priv, bytes))) |
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251 | return 0; |
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252 | |||
253 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); |
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254 | if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) |
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255 | return vmw_fifo_wait_noirq(dev_priv, bytes, |
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256 | interruptible, timeout); |
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257 | |||
258 | mutex_lock(&dev_priv->hw_mutex); |
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259 | if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { |
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260 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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261 | outl(SVGA_IRQFLAG_FIFO_PROGRESS, |
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262 | dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); |
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263 | dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; |
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264 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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265 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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266 | } |
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267 | mutex_unlock(&dev_priv->hw_mutex); |
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268 | |||
269 | if (interruptible) |
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270 | ret = wait_event_interruptible_timeout |
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271 | (dev_priv->fifo_queue, |
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272 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
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273 | else |
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274 | ret = wait_event_timeout |
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275 | (dev_priv->fifo_queue, |
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276 | !vmw_fifo_is_full(dev_priv, bytes), timeout); |
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277 | |||
278 | if (unlikely(ret == 0)) |
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279 | ret = -EBUSY; |
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280 | else if (likely(ret > 0)) |
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281 | ret = 0; |
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282 | |||
283 | mutex_lock(&dev_priv->hw_mutex); |
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284 | if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { |
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285 | spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); |
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286 | dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; |
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287 | vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); |
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288 | spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); |
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289 | } |
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290 | mutex_unlock(&dev_priv->hw_mutex); |
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291 | |||
292 | return ret; |
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293 | } |
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294 | |||
295 | /** |
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296 | * Reserve @bytes number of bytes in the fifo. |
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297 | * |
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298 | * This function will return NULL (error) on two conditions: |
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299 | * If it timeouts waiting for fifo space, or if @bytes is larger than the |
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300 | * available fifo space. |
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301 | * |
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302 | * Returns: |
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303 | * Pointer to the fifo, or null on error (possible hardware hang). |
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304 | */ |
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305 | void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) |
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306 | { |
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307 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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308 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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309 | uint32_t max; |
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310 | uint32_t min; |
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311 | uint32_t next_cmd; |
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312 | uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
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313 | int ret; |
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314 | |||
315 | mutex_lock(&fifo_state->fifo_mutex); |
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316 | max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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317 | min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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318 | next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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319 | |||
320 | if (unlikely(bytes >= (max - min))) |
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321 | goto out_err; |
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322 | |||
323 | BUG_ON(fifo_state->reserved_size != 0); |
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324 | BUG_ON(fifo_state->dynamic_buffer != NULL); |
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325 | |||
326 | fifo_state->reserved_size = bytes; |
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327 | |||
328 | while (1) { |
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329 | uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); |
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330 | bool need_bounce = false; |
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331 | bool reserve_in_place = false; |
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332 | |||
333 | if (next_cmd >= stop) { |
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334 | if (likely((next_cmd + bytes < max || |
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335 | (next_cmd + bytes == max && stop > min)))) |
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336 | reserve_in_place = true; |
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337 | |||
338 | else if (vmw_fifo_is_full(dev_priv, bytes)) { |
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339 | ret = vmw_fifo_wait(dev_priv, bytes, |
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340 | false, 3 * HZ); |
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341 | if (unlikely(ret != 0)) |
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342 | goto out_err; |
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343 | } else |
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344 | need_bounce = true; |
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345 | |||
346 | } else { |
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347 | |||
348 | if (likely((next_cmd + bytes < stop))) |
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349 | reserve_in_place = true; |
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350 | else { |
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351 | ret = vmw_fifo_wait(dev_priv, bytes, |
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352 | false, 3 * HZ); |
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353 | if (unlikely(ret != 0)) |
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354 | goto out_err; |
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355 | } |
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356 | } |
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357 | |||
358 | if (reserve_in_place) { |
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359 | if (reserveable || bytes <= sizeof(uint32_t)) { |
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360 | fifo_state->using_bounce_buffer = false; |
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361 | |||
362 | if (reserveable) |
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363 | iowrite32(bytes, fifo_mem + |
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364 | SVGA_FIFO_RESERVED); |
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365 | return fifo_mem + (next_cmd >> 2); |
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366 | } else { |
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367 | need_bounce = true; |
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368 | } |
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369 | } |
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370 | |||
371 | if (need_bounce) { |
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372 | fifo_state->using_bounce_buffer = true; |
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373 | if (bytes < fifo_state->static_buffer_size) |
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374 | return fifo_state->static_buffer; |
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375 | else { |
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376 | fifo_state->dynamic_buffer = kmalloc(bytes,0); |
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377 | return fifo_state->dynamic_buffer; |
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378 | } |
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379 | } |
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380 | } |
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381 | out_err: |
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382 | fifo_state->reserved_size = 0; |
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383 | mutex_unlock(&fifo_state->fifo_mutex); |
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384 | return NULL; |
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385 | } |
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386 | |||
387 | static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, |
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388 | __le32 __iomem *fifo_mem, |
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389 | uint32_t next_cmd, |
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390 | uint32_t max, uint32_t min, uint32_t bytes) |
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391 | { |
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392 | uint32_t chunk_size = max - next_cmd; |
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393 | uint32_t rest; |
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394 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
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395 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
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396 | |||
397 | if (bytes < chunk_size) |
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398 | chunk_size = bytes; |
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399 | |||
400 | iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); |
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401 | // mb(); |
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402 | memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); |
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403 | rest = bytes - chunk_size; |
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404 | if (rest) |
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405 | memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), |
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406 | rest); |
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407 | } |
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408 | |||
409 | static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, |
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410 | __le32 __iomem *fifo_mem, |
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411 | uint32_t next_cmd, |
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412 | uint32_t max, uint32_t min, uint32_t bytes) |
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413 | { |
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414 | uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? |
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415 | fifo_state->dynamic_buffer : fifo_state->static_buffer; |
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416 | |||
417 | while (bytes > 0) { |
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418 | iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); |
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419 | next_cmd += sizeof(uint32_t); |
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420 | if (unlikely(next_cmd == max)) |
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421 | next_cmd = min; |
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422 | mb(); |
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423 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
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424 | mb(); |
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425 | bytes -= sizeof(uint32_t); |
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426 | } |
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427 | } |
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428 | |||
429 | void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) |
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430 | { |
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431 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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432 | __le32 __iomem *fifo_mem = dev_priv->mmio_virt; |
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433 | uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); |
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434 | uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); |
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435 | uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); |
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436 | bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; |
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437 | |||
438 | BUG_ON((bytes & 3) != 0); |
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439 | BUG_ON(bytes > fifo_state->reserved_size); |
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440 | |||
441 | fifo_state->reserved_size = 0; |
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442 | |||
443 | if (fifo_state->using_bounce_buffer) { |
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444 | if (reserveable) |
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445 | vmw_fifo_res_copy(fifo_state, fifo_mem, |
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446 | next_cmd, max, min, bytes); |
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447 | else |
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448 | vmw_fifo_slow_copy(fifo_state, fifo_mem, |
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449 | next_cmd, max, min, bytes); |
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450 | |||
451 | if (fifo_state->dynamic_buffer) { |
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452 | vfree(fifo_state->dynamic_buffer); |
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453 | fifo_state->dynamic_buffer = NULL; |
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454 | } |
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455 | |||
456 | } |
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457 | |||
458 | // down_write(&fifo_state->rwsem); |
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459 | if (fifo_state->using_bounce_buffer || reserveable) { |
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460 | next_cmd += bytes; |
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461 | if (next_cmd >= max) |
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462 | next_cmd -= max - min; |
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463 | mb(); |
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464 | iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); |
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465 | } |
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466 | |||
467 | if (reserveable) |
||
468 | iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); |
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469 | // mb(); |
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470 | // up_write(&fifo_state->rwsem); |
||
471 | vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); |
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472 | mutex_unlock(&fifo_state->fifo_mutex); |
||
473 | } |
||
474 | |||
475 | int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) |
||
476 | { |
||
477 | struct vmw_fifo_state *fifo_state = &dev_priv->fifo; |
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478 | struct svga_fifo_cmd_fence *cmd_fence; |
||
479 | void *fm; |
||
480 | int ret = 0; |
||
481 | uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence); |
||
482 | |||
483 | fm = vmw_fifo_reserve(dev_priv, bytes); |
||
484 | if (unlikely(fm == NULL)) { |
||
485 | *seqno = atomic_read(&dev_priv->marker_seq); |
||
486 | ret = -ENOMEM; |
||
487 | (void)vmw_fallback_wait(dev_priv, false, true, *seqno, |
||
488 | false, 3*HZ); |
||
489 | goto out_err; |
||
490 | } |
||
491 | |||
492 | do { |
||
493 | *seqno = atomic_add_return(1, &dev_priv->marker_seq); |
||
494 | } while (*seqno == 0); |
||
495 | |||
496 | if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { |
||
497 | |||
498 | /* |
||
499 | * Don't request hardware to send a fence. The |
||
500 | * waiting code in vmwgfx_irq.c will emulate this. |
||
501 | */ |
||
502 | |||
503 | vmw_fifo_commit(dev_priv, 0); |
||
504 | return 0; |
||
505 | } |
||
506 | |||
507 | *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE); |
||
508 | cmd_fence = (struct svga_fifo_cmd_fence *) |
||
509 | ((unsigned long)fm + sizeof(__le32)); |
||
510 | |||
511 | iowrite32(*seqno, &cmd_fence->fence); |
||
512 | vmw_fifo_commit(dev_priv, bytes); |
||
513 | (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); |
||
514 | vmw_update_seqno(dev_priv, fifo_state); |
||
515 | |||
516 | out_err: |
||
517 | return ret; |
||
518 | } |
||
519 | |||
520 | /** |
||
521 | * vmw_fifo_emit_dummy_query - emits a dummy query to the fifo. |
||
522 | * |
||
523 | * @dev_priv: The device private structure. |
||
524 | * @cid: The hardware context id used for the query. |
||
525 | * |
||
526 | * This function is used to emit a dummy occlusion query with |
||
527 | * no primitives rendered between query begin and query end. |
||
528 | * It's used to provide a query barrier, in order to know that when |
||
529 | * this query is finished, all preceding queries are also finished. |
||
530 | * |
||
531 | * A Query results structure should have been initialized at the start |
||
532 | * of the dev_priv->dummy_query_bo buffer object. And that buffer object |
||
533 | * must also be either reserved or pinned when this function is called. |
||
534 | * |
||
535 | * Returns -ENOMEM on failure to reserve fifo space. |
||
536 | */ |
||
537 | int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, |
||
538 | uint32_t cid) |
||
539 | { |
||
540 | /* |
||
541 | * A query wait without a preceding query end will |
||
542 | * actually finish all queries for this cid |
||
543 | * without writing to the query result structure. |
||
544 | */ |
||
545 | |||
546 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; |
||
547 | struct { |
||
548 | SVGA3dCmdHeader header; |
||
549 | SVGA3dCmdWaitForQuery body; |
||
550 | } *cmd; |
||
551 | |||
552 | cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); |
||
553 | |||
554 | if (unlikely(cmd == NULL)) { |
||
555 | DRM_ERROR("Out of fifo space for dummy query.\n"); |
||
556 | return -ENOMEM; |
||
557 | } |
||
558 | |||
559 | cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY; |
||
560 | cmd->header.size = sizeof(cmd->body); |
||
561 | cmd->body.cid = cid; |
||
562 | cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION; |
||
563 | |||
564 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
||
565 | cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER; |
||
566 | cmd->body.guestResult.offset = bo->offset; |
||
567 | } else { |
||
568 | cmd->body.guestResult.gmrId = bo->mem.start; |
||
569 | cmd->body.guestResult.offset = 0; |
||
570 | } |
||
571 | |||
572 | vmw_fifo_commit(dev_priv, sizeof(*cmd)); |
||
573 | |||
574 | return 0; |
||
575 | }>>=>>>=>>=><=>>=> |