Subversion Repositories Kolibri OS

Rev

Rev 4111 | Rev 4570 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
4075 Serge 1
/**************************************************************************
2
 *
3
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4
 * All Rights Reserved.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the
8
 * "Software"), to deal in the Software without restriction, including
9
 * without limitation the rights to use, copy, modify, merge, publish,
10
 * distribute, sub license, and/or sell copies of the Software, and to
11
 * permit persons to whom the Software is furnished to do so, subject to
12
 * the following conditions:
13
 *
14
 * The above copyright notice and this permission notice (including the
15
 * next paragraph) shall be included in all copies or substantial portions
16
 * of the Software.
17
 *
18
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25
 *
26
 **************************************************************************/
27
#include 
28
 
29
#include 
30
#include "vmwgfx_drv.h"
31
#include 
32
#include 
33
#include 
34
//#include 
4569 Serge 35
#include 
4075 Serge 36
 
37
#define VMWGFX_DRIVER_NAME "vmwgfx"
38
#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39
#define VMWGFX_CHIP_SVGAII 0
40
#define VMW_FB_RESERVATION 0
41
 
42
#define VMW_MIN_INITIAL_WIDTH 800
43
#define VMW_MIN_INITIAL_HEIGHT 600
44
 
45
#if 0
46
/**
47
 * Fully encoded drm commands. Might move to vmw_drm.h
48
 */
49
 
50
#define DRM_IOCTL_VMW_GET_PARAM					\
51
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,		\
52
		 struct drm_vmw_getparam_arg)
53
#define DRM_IOCTL_VMW_ALLOC_DMABUF				\
54
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,	\
55
		union drm_vmw_alloc_dmabuf_arg)
56
#define DRM_IOCTL_VMW_UNREF_DMABUF				\
57
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,	\
58
		struct drm_vmw_unref_dmabuf_arg)
59
#define DRM_IOCTL_VMW_CURSOR_BYPASS				\
60
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,	\
61
		 struct drm_vmw_cursor_bypass_arg)
62
 
63
#define DRM_IOCTL_VMW_CONTROL_STREAM				\
64
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,	\
65
		 struct drm_vmw_control_stream_arg)
66
#define DRM_IOCTL_VMW_CLAIM_STREAM				\
67
	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,	\
68
		 struct drm_vmw_stream_arg)
69
#define DRM_IOCTL_VMW_UNREF_STREAM				\
70
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,	\
71
		 struct drm_vmw_stream_arg)
72
 
73
#define DRM_IOCTL_VMW_CREATE_CONTEXT				\
74
	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,	\
75
		struct drm_vmw_context_arg)
76
#define DRM_IOCTL_VMW_UNREF_CONTEXT				\
77
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,	\
78
		struct drm_vmw_context_arg)
79
#define DRM_IOCTL_VMW_CREATE_SURFACE				\
80
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,	\
81
		 union drm_vmw_surface_create_arg)
82
#define DRM_IOCTL_VMW_UNREF_SURFACE				\
83
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,	\
84
		 struct drm_vmw_surface_arg)
85
#define DRM_IOCTL_VMW_REF_SURFACE				\
86
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,	\
87
		 union drm_vmw_surface_reference_arg)
88
#define DRM_IOCTL_VMW_EXECBUF					\
89
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,		\
90
		struct drm_vmw_execbuf_arg)
91
#define DRM_IOCTL_VMW_GET_3D_CAP				\
92
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,		\
93
		 struct drm_vmw_get_3d_cap_arg)
94
#define DRM_IOCTL_VMW_FENCE_WAIT				\
95
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,		\
96
		 struct drm_vmw_fence_wait_arg)
97
#define DRM_IOCTL_VMW_FENCE_SIGNALED				\
98
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,	\
99
		 struct drm_vmw_fence_signaled_arg)
100
#define DRM_IOCTL_VMW_FENCE_UNREF				\
101
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,		\
102
		 struct drm_vmw_fence_arg)
103
#define DRM_IOCTL_VMW_FENCE_EVENT				\
104
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,		\
105
		 struct drm_vmw_fence_event_arg)
106
#define DRM_IOCTL_VMW_PRESENT					\
107
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,		\
108
		 struct drm_vmw_present_arg)
109
#define DRM_IOCTL_VMW_PRESENT_READBACK				\
110
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,	\
111
		 struct drm_vmw_present_readback_arg)
112
#define DRM_IOCTL_VMW_UPDATE_LAYOUT				\
113
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,	\
114
		 struct drm_vmw_update_layout_arg)
4569 Serge 115
#define DRM_IOCTL_VMW_CREATE_SHADER				\
116
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,	\
117
		 struct drm_vmw_shader_create_arg)
118
#define DRM_IOCTL_VMW_UNREF_SHADER				\
119
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,	\
120
		 struct drm_vmw_shader_arg)
121
#define DRM_IOCTL_VMW_GB_SURFACE_CREATE				\
122
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,	\
123
		 union drm_vmw_gb_surface_create_arg)
124
#define DRM_IOCTL_VMW_GB_SURFACE_REF				\
125
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,	\
126
		 union drm_vmw_gb_surface_reference_arg)
127
#define DRM_IOCTL_VMW_SYNCCPU					\
128
	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,		\
129
		 struct drm_vmw_synccpu_arg)
4075 Serge 130
 
131
/**
132
 * The core DRM version of this macro doesn't account for
133
 * DRM_COMMAND_BASE.
134
 */
135
 
136
#define VMW_IOCTL_DEF(ioctl, func, flags) \
137
  [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
138
 
139
/**
140
 * Ioctl definitions.
141
 */
142
 
4111 Serge 143
static const struct drm_ioctl_desc vmw_ioctls[] = {
4075 Serge 144
	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
145
		      DRM_AUTH | DRM_UNLOCKED),
146
	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
147
		      DRM_AUTH | DRM_UNLOCKED),
148
	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
149
		      DRM_AUTH | DRM_UNLOCKED),
150
	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
151
		      vmw_kms_cursor_bypass_ioctl,
152
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
153
 
154
	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
155
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
156
	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
157
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
158
	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
159
		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
160
 
161
	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
162
		      DRM_AUTH | DRM_UNLOCKED),
163
	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
164
		      DRM_AUTH | DRM_UNLOCKED),
165
	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
166
		      DRM_AUTH | DRM_UNLOCKED),
167
	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
168
		      DRM_AUTH | DRM_UNLOCKED),
169
	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
170
		      DRM_AUTH | DRM_UNLOCKED),
171
	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
172
		      DRM_AUTH | DRM_UNLOCKED),
173
	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174
		      DRM_AUTH | DRM_UNLOCKED),
175
	VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176
		      vmw_fence_obj_signaled_ioctl,
177
		      DRM_AUTH | DRM_UNLOCKED),
178
	VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
179
		      DRM_AUTH | DRM_UNLOCKED),
180
	VMW_IOCTL_DEF(VMW_FENCE_EVENT,
181
		      vmw_fence_event_ioctl,
182
		      DRM_AUTH | DRM_UNLOCKED),
183
	VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
184
		      DRM_AUTH | DRM_UNLOCKED),
185
 
186
	/* these allow direct access to the framebuffers mark as master only */
187
	VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
188
		      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
189
	VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
190
		      vmw_present_readback_ioctl,
191
		      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
192
	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
193
		      vmw_kms_update_layout_ioctl,
194
		      DRM_MASTER | DRM_UNLOCKED),
4569 Serge 195
	VMW_IOCTL_DEF(VMW_CREATE_SHADER,
196
		      vmw_shader_define_ioctl,
197
		      DRM_AUTH | DRM_UNLOCKED),
198
	VMW_IOCTL_DEF(VMW_UNREF_SHADER,
199
		      vmw_shader_destroy_ioctl,
200
		      DRM_AUTH | DRM_UNLOCKED),
201
	VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
202
		      vmw_gb_surface_define_ioctl,
203
		      DRM_AUTH | DRM_UNLOCKED),
204
	VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
205
		      vmw_gb_surface_reference_ioctl,
206
		      DRM_AUTH | DRM_UNLOCKED),
207
	VMW_IOCTL_DEF(VMW_SYNCCPU,
208
		      vmw_user_dmabuf_synccpu_ioctl,
209
		      DRM_AUTH | DRM_UNLOCKED),
4075 Serge 210
};
211
#endif
212
 
213
static struct pci_device_id vmw_pci_id_list[] = {
214
	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
215
	{0, 0, 0}
216
};
217
 
218
static int enable_fbdev = 1;
4569 Serge 219
static int vmw_force_iommu;
220
static int vmw_restrict_iommu;
221
static int vmw_force_coherent;
222
static int vmw_restrict_dma_mask;
4075 Serge 223
 
224
static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
225
static void vmw_master_init(struct vmw_master *);
226
 
227
MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
228
module_param_named(enable_fbdev, enable_fbdev, int, 0600);
4569 Serge 229
MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
230
module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
231
MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
232
module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
233
MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
234
module_param_named(force_coherent, vmw_force_coherent, int, 0600);
235
MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
236
module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
4075 Serge 237
 
4569 Serge 238
 
4075 Serge 239
static void vmw_print_capabilities(uint32_t capabilities)
240
{
241
	DRM_INFO("Capabilities:\n");
242
	if (capabilities & SVGA_CAP_RECT_COPY)
243
		DRM_INFO("  Rect copy.\n");
244
	if (capabilities & SVGA_CAP_CURSOR)
245
		DRM_INFO("  Cursor.\n");
246
	if (capabilities & SVGA_CAP_CURSOR_BYPASS)
247
		DRM_INFO("  Cursor bypass.\n");
248
	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
249
		DRM_INFO("  Cursor bypass 2.\n");
250
	if (capabilities & SVGA_CAP_8BIT_EMULATION)
251
		DRM_INFO("  8bit emulation.\n");
252
	if (capabilities & SVGA_CAP_ALPHA_CURSOR)
253
		DRM_INFO("  Alpha cursor.\n");
254
	if (capabilities & SVGA_CAP_3D)
255
		DRM_INFO("  3D.\n");
256
	if (capabilities & SVGA_CAP_EXTENDED_FIFO)
257
		DRM_INFO("  Extended Fifo.\n");
258
	if (capabilities & SVGA_CAP_MULTIMON)
259
		DRM_INFO("  Multimon.\n");
260
	if (capabilities & SVGA_CAP_PITCHLOCK)
261
		DRM_INFO("  Pitchlock.\n");
262
	if (capabilities & SVGA_CAP_IRQMASK)
263
		DRM_INFO("  Irq mask.\n");
264
	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
265
		DRM_INFO("  Display Topology.\n");
266
	if (capabilities & SVGA_CAP_GMR)
267
		DRM_INFO("  GMR.\n");
268
	if (capabilities & SVGA_CAP_TRACES)
269
		DRM_INFO("  Traces.\n");
270
	if (capabilities & SVGA_CAP_GMR2)
271
		DRM_INFO("  GMR2.\n");
272
	if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
273
		DRM_INFO("  Screen Object 2.\n");
4569 Serge 274
	if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
275
		DRM_INFO("  Command Buffers.\n");
276
	if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
277
		DRM_INFO("  Command Buffers 2.\n");
278
	if (capabilities & SVGA_CAP_GBOBJECTS)
279
		DRM_INFO("  Guest Backed Resources.\n");
4075 Serge 280
}
281
 
282
/**
4569 Serge 283
 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
4075 Serge 284
 *
4569 Serge 285
 * @dev_priv: A device private structure.
4075 Serge 286
 *
4569 Serge 287
 * This function creates a small buffer object that holds the query
288
 * result for dummy queries emitted as query barriers.
289
 * The function will then map the first page and initialize a pending
290
 * occlusion query result structure, Finally it will unmap the buffer.
291
 * No interruptible waits are done within this function.
4075 Serge 292
 *
4569 Serge 293
 * Returns an error if bo creation or initialization fails.
4075 Serge 294
 */
4569 Serge 295
static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
4075 Serge 296
{
4569 Serge 297
	int ret;
298
	struct ttm_buffer_object *bo;
4075 Serge 299
	struct ttm_bo_kmap_obj map;
300
	volatile SVGA3dQueryResult *result;
301
	bool dummy;
302
 
4569 Serge 303
	/*
304
	 * Create the bo as pinned, so that a tryreserve will
305
	 * immediately succeed. This is because we're the only
306
	 * user of the bo currently.
307
	 */
308
	ret = ttm_bo_create(&dev_priv->bdev,
309
			     PAGE_SIZE,
310
			     ttm_bo_type_device,
311
			    &vmw_sys_ne_placement,
312
			     0, false, NULL,
313
			    &bo);
314
 
4075 Serge 315
	if (unlikely(ret != 0))
4569 Serge 316
		return ret;
317
 
318
	ret = ttm_bo_reserve(bo, false, true, false, 0);
319
	BUG_ON(ret != 0);
320
 
4075 Serge 321
	ret = ttm_bo_kmap(bo, 0, 1, &map);
322
	if (likely(ret == 0)) {
323
		result = ttm_kmap_obj_virtual(&map, &dummy);
324
		result->totalSize = sizeof(*result);
325
		result->state = SVGA3D_QUERYSTATE_PENDING;
326
		result->result32 = 0xff;
327
		ttm_bo_kunmap(&map);
4569 Serge 328
	}
329
	vmw_bo_pin(bo, false);
4075 Serge 330
	ttm_bo_unreserve(bo);
331
 
4569 Serge 332
	if (unlikely(ret != 0)) {
333
		DRM_ERROR("Dummy query buffer map failed.\n");
334
		ttm_bo_unref(&bo);
335
	} else
336
		dev_priv->dummy_query_bo = bo;
4075 Serge 337
 
4569 Serge 338
	return ret;
4075 Serge 339
}
340
 
341
static int vmw_request_device(struct vmw_private *dev_priv)
342
{
343
	int ret;
344
    ENTER();
345
 
346
	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
347
	if (unlikely(ret != 0)) {
348
		DRM_ERROR("Unable to initialize FIFO.\n");
349
		return ret;
350
	}
351
//   vmw_fence_fifo_up(dev_priv->fman);
352
//   ret = vmw_dummy_query_bo_create(dev_priv);
353
//   if (unlikely(ret != 0))
354
//       goto out_no_query_bo;
355
//   vmw_dummy_query_bo_prepare(dev_priv);
356
 
357
    LEAVE();
358
 
359
	return 0;
360
 
361
out_no_query_bo:
362
	vmw_fence_fifo_down(dev_priv->fman);
363
	vmw_fifo_release(dev_priv, &dev_priv->fifo);
364
	return ret;
365
}
366
 
367
static void vmw_release_device(struct vmw_private *dev_priv)
368
{
369
	/*
370
	 * Previous destructions should've released
371
	 * the pinned bo.
372
	 */
373
 
374
	BUG_ON(dev_priv->pinned_bo != NULL);
375
 
376
	ttm_bo_unref(&dev_priv->dummy_query_bo);
377
	vmw_fence_fifo_down(dev_priv->fman);
378
	vmw_fifo_release(dev_priv, &dev_priv->fifo);
379
}
380
 
4569 Serge 381
 
4075 Serge 382
/**
383
 * Increase the 3d resource refcount.
384
 * If the count was prevously zero, initialize the fifo, switching to svga
385
 * mode. Note that the master holds a ref as well, and may request an
386
 * explicit switch to svga mode if fb is not running, using @unhide_svga.
387
 */
388
int vmw_3d_resource_inc(struct vmw_private *dev_priv,
389
			bool unhide_svga)
390
{
391
	int ret = 0;
392
 
393
    ENTER();
394
 
395
	mutex_lock(&dev_priv->release_mutex);
396
	if (unlikely(dev_priv->num_3d_resources++ == 0)) {
397
        ret = vmw_request_device(dev_priv);
398
		if (unlikely(ret != 0))
399
			--dev_priv->num_3d_resources;
400
	} else if (unhide_svga) {
401
		mutex_lock(&dev_priv->hw_mutex);
402
		vmw_write(dev_priv, SVGA_REG_ENABLE,
403
			  vmw_read(dev_priv, SVGA_REG_ENABLE) &
404
			  ~SVGA_REG_ENABLE_HIDE);
405
		mutex_unlock(&dev_priv->hw_mutex);
406
	}
407
 
408
	mutex_unlock(&dev_priv->release_mutex);
409
    LEAVE();
410
	return ret;
411
}
412
 
413
/**
414
 * Decrease the 3d resource refcount.
415
 * If the count reaches zero, disable the fifo, switching to vga mode.
416
 * Note that the master holds a refcount as well, and may request an
417
 * explicit switch to vga mode when it releases its refcount to account
418
 * for the situation of an X server vt switch to VGA with 3d resources
419
 * active.
420
 */
421
void vmw_3d_resource_dec(struct vmw_private *dev_priv,
422
			 bool hide_svga)
423
{
424
	int32_t n3d;
425
 
426
	mutex_lock(&dev_priv->release_mutex);
427
	if (unlikely(--dev_priv->num_3d_resources == 0))
428
		vmw_release_device(dev_priv);
429
	else if (hide_svga) {
430
		mutex_lock(&dev_priv->hw_mutex);
431
		vmw_write(dev_priv, SVGA_REG_ENABLE,
432
			  vmw_read(dev_priv, SVGA_REG_ENABLE) |
433
			  SVGA_REG_ENABLE_HIDE);
434
		mutex_unlock(&dev_priv->hw_mutex);
435
	}
436
 
437
	n3d = (int32_t) dev_priv->num_3d_resources;
438
	mutex_unlock(&dev_priv->release_mutex);
439
 
440
	BUG_ON(n3d < 0);
441
}
442
 
443
/**
444
 * Sets the initial_[width|height] fields on the given vmw_private.
445
 *
446
 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
447
 * clamping the value to fb_max_[width|height] fields and the
448
 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
449
 * If the values appear to be invalid, set them to
450
 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
451
 */
452
static void vmw_get_initial_size(struct vmw_private *dev_priv)
453
{
454
	uint32_t width;
455
	uint32_t height;
456
 
457
	width = vmw_read(dev_priv, SVGA_REG_WIDTH);
458
	height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
459
 
460
	width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
461
	height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
462
 
463
	if (width > dev_priv->fb_max_width ||
464
	    height > dev_priv->fb_max_height) {
465
 
466
		/*
467
		 * This is a host error and shouldn't occur.
468
		 */
469
 
470
		width = VMW_MIN_INITIAL_WIDTH;
471
		height = VMW_MIN_INITIAL_HEIGHT;
472
	}
473
 
474
	dev_priv->initial_width = width;
475
	dev_priv->initial_height = height;
476
}
477
 
4569 Serge 478
/**
479
 * vmw_dma_masks - set required page- and dma masks
480
 *
481
 * @dev: Pointer to struct drm-device
482
 *
483
 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
484
 * restriction also for 64-bit systems.
485
 */
486
#ifdef CONFIG_INTEL_IOMMU
487
static int vmw_dma_masks(struct vmw_private *dev_priv)
488
{
489
	struct drm_device *dev = dev_priv->dev;
490
 
491
	if (intel_iommu_enabled &&
492
	    (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
493
		DRM_INFO("Restricting DMA addresses to 44 bits.\n");
494
		return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
495
	}
496
	return 0;
497
}
498
#else
499
static int vmw_dma_masks(struct vmw_private *dev_priv)
500
{
501
	return 0;
502
}
503
#endif
504
 
4075 Serge 505
static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
506
{
507
	struct vmw_private *dev_priv;
508
	int ret;
509
	uint32_t svga_id;
510
	enum vmw_res_type i;
4569 Serge 511
	bool refuse_dma = false;
4075 Serge 512
 
4569 Serge 513
 
4075 Serge 514
    ENTER();
515
 
516
	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
517
	if (unlikely(dev_priv == NULL)) {
518
		DRM_ERROR("Failed allocating a device private struct.\n");
519
		return -ENOMEM;
520
	}
521
 
522
	pci_set_master(dev->pdev);
523
 
524
	dev_priv->dev = dev;
525
	dev_priv->vmw_chipset = chipset;
526
	dev_priv->last_read_seqno = (uint32_t) -100;
527
	mutex_init(&dev_priv->hw_mutex);
528
	mutex_init(&dev_priv->cmdbuf_mutex);
529
	mutex_init(&dev_priv->release_mutex);
4569 Serge 530
	mutex_init(&dev_priv->binding_mutex);
4075 Serge 531
	rwlock_init(&dev_priv->resource_lock);
532
 
533
	for (i = vmw_res_context; i < vmw_res_max; ++i) {
534
		idr_init(&dev_priv->res_idr[i]);
535
		INIT_LIST_HEAD(&dev_priv->res_lru[i]);
536
	}
537
 
538
	mutex_init(&dev_priv->init_mutex);
539
	init_waitqueue_head(&dev_priv->fence_queue);
540
	init_waitqueue_head(&dev_priv->fifo_queue);
541
	dev_priv->fence_queue_waiters = 0;
542
	atomic_set(&dev_priv->fifo_queue_waiters, 0);
543
 
544
	dev_priv->used_memory_size = 0;
545
 
546
	dev_priv->io_start = pci_resource_start(dev->pdev, 0);
547
	dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
548
	dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
549
 
550
    printk("io: %x vram: %x mmio: %x\n",dev_priv->io_start,
551
            dev_priv->vram_start,dev_priv->mmio_start);
552
 
553
	dev_priv->enable_fb = enable_fbdev;
554
 
555
	mutex_lock(&dev_priv->hw_mutex);
556
 
557
    vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
558
	svga_id = vmw_read(dev_priv, SVGA_REG_ID);
559
	if (svga_id != SVGA_ID_2) {
560
		ret = -ENOSYS;
561
		DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
562
		mutex_unlock(&dev_priv->hw_mutex);
563
		goto out_err0;
564
	}
565
 
566
	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
4569 Serge 567
//   ret = vmw_dma_select_mode(dev_priv);
568
//   if (unlikely(ret != 0)) {
569
//       DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
570
//       refuse_dma = true;
571
//   }
4075 Serge 572
 
573
	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
574
	dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
575
	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
576
	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
577
 
578
	vmw_get_initial_size(dev_priv);
579
 
4569 Serge 580
	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
4075 Serge 581
		dev_priv->max_gmr_ids =
582
			vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
583
		dev_priv->max_gmr_pages =
584
			vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
585
		dev_priv->memory_size =
586
			vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
587
		dev_priv->memory_size -= dev_priv->vram_size;
588
	} else {
589
		/*
590
		 * An arbitrary limit of 512MiB on surface
591
		 * memory. But all HWV8 hardware supports GMR2.
592
		 */
593
		dev_priv->memory_size = 512*1024*1024;
594
	}
4569 Serge 595
	dev_priv->max_mob_pages = 0;
596
	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
597
		uint64_t mem_size =
598
			vmw_read(dev_priv,
599
				 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
4075 Serge 600
 
4569 Serge 601
		dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
602
		dev_priv->prim_bb_mem =
603
			vmw_read(dev_priv,
604
				 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
605
	} else
606
		dev_priv->prim_bb_mem = dev_priv->vram_size;
607
 
608
	ret = vmw_dma_masks(dev_priv);
609
	if (unlikely(ret != 0)) {
610
		mutex_unlock(&dev_priv->hw_mutex);
611
		goto out_err0;
612
	}
613
 
614
	if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
615
		dev_priv->prim_bb_mem = dev_priv->vram_size;
616
 
4075 Serge 617
	mutex_unlock(&dev_priv->hw_mutex);
618
 
619
	vmw_print_capabilities(dev_priv->capabilities);
620
 
4569 Serge 621
	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
4075 Serge 622
		DRM_INFO("Max GMR ids is %u\n",
623
			 (unsigned)dev_priv->max_gmr_ids);
624
		DRM_INFO("Max number of GMR pages is %u\n",
625
			 (unsigned)dev_priv->max_gmr_pages);
626
		DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
627
			 (unsigned)dev_priv->memory_size / 1024);
628
	}
4569 Serge 629
	DRM_INFO("Maximum display memory size is %u kiB\n",
630
		 dev_priv->prim_bb_mem / 1024);
4075 Serge 631
	DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
632
		 dev_priv->vram_start, dev_priv->vram_size / 1024);
633
	DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
634
		 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
635
 
636
	ret = vmw_ttm_global_init(dev_priv);
637
	if (unlikely(ret != 0))
638
		goto out_err0;
639
 
640
 
4569 Serge 641
	vmw_master_init(&dev_priv->fbdev_master);
642
	dev_priv->active_master = &dev_priv->fbdev_master;
4075 Serge 643
 
644
 
645
	ret = ttm_bo_device_init(&dev_priv->bdev,
646
				 dev_priv->bo_global_ref.ref.object,
647
				 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
648
				 false);
649
	if (unlikely(ret != 0)) {
650
		DRM_ERROR("Failed initializing TTM buffer object driver.\n");
651
		goto out_err1;
652
	}
653
 
654
	ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
655
			     (dev_priv->vram_size >> PAGE_SHIFT));
656
	if (unlikely(ret != 0)) {
657
		DRM_ERROR("Failed initializing memory manager for VRAM.\n");
658
		goto out_err2;
659
	}
660
 
661
	dev_priv->has_gmr = true;
4569 Serge 662
	if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
663
	    refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
664
					 VMW_PL_GMR) != 0) {
4075 Serge 665
		DRM_INFO("No GMR memory available. "
666
			 "Graphics memory resources are very limited.\n");
667
		dev_priv->has_gmr = false;
668
	}
669
 
4569 Serge 670
	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
671
		dev_priv->has_mob = true;
672
		if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
673
				   VMW_PL_MOB) != 0) {
674
			DRM_INFO("No MOB memory available. "
675
				 "3D will be disabled.\n");
676
			dev_priv->has_mob = false;
677
		}
678
	}
4075 Serge 679
	dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
680
					 dev_priv->mmio_size);
681
 
682
	if (unlikely(dev_priv->mmio_virt == NULL)) {
683
		ret = -ENOMEM;
684
		DRM_ERROR("Failed mapping MMIO.\n");
685
		goto out_err3;
686
	}
687
 
688
	/* Need mmio memory to check for fifo pitchlock cap. */
689
	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
690
	    !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
691
	    !vmw_fifo_have_pitchlock(dev_priv)) {
692
		ret = -ENOSYS;
693
		DRM_ERROR("Hardware has no pitchlock\n");
694
		goto out_err4;
695
	}
696
 
4569 Serge 697
//   dev_priv->tdev = ttm_object_device_init
698
//       (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
4075 Serge 699
 
4569 Serge 700
//   if (unlikely(dev_priv->tdev == NULL)) {
701
//       DRM_ERROR("Unable to initialize TTM object management.\n");
702
//       ret = -ENOMEM;
703
//       goto out_err4;
704
//   }
4075 Serge 705
 
706
	dev->dev_private = dev_priv;
707
 
708
#if 0
709
 
710
	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
711
		ret = drm_irq_install(dev);
712
		if (ret != 0) {
713
			DRM_ERROR("Failed installing irq: %d\n", ret);
714
			goto out_no_irq;
715
		}
716
	}
717
 
718
	dev_priv->fman = vmw_fence_manager_init(dev_priv);
4111 Serge 719
	if (unlikely(dev_priv->fman == NULL)) {
720
		ret = -ENOMEM;
4075 Serge 721
		goto out_no_fman;
4111 Serge 722
	}
4075 Serge 723
 
724
	vmw_kms_save_vga(dev_priv);
725
#endif
726
 
727
	/* Start kms and overlay systems, needs fifo. */
728
	ret = vmw_kms_init(dev_priv);
729
	if (unlikely(ret != 0))
730
		goto out_no_kms;
731
 
4080 Serge 732
    if (dev_priv->enable_fb) {
4075 Serge 733
       ret = vmw_3d_resource_inc(dev_priv, true);
734
       if (unlikely(ret != 0))
735
           goto out_no_fifo;
736
//       vmw_fb_init(dev_priv);
4080 Serge 737
    }
4075 Serge 738
 
4111 Serge 739
    main_device = dev;
740
 
4080 Serge 741
    LEAVE();
4075 Serge 742
	return 0;
743
 
744
out_no_fifo:
745
//   vmw_overlay_close(dev_priv);
746
//   vmw_kms_close(dev_priv);
747
out_no_kms:
748
//   vmw_kms_restore_vga(dev_priv);
749
//   vmw_fence_manager_takedown(dev_priv->fman);
750
out_no_fman:
751
//   if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
752
//       drm_irq_uninstall(dev_priv->dev);
753
out_no_irq:
754
//   if (dev_priv->stealth)
755
//       pci_release_region(dev->pdev, 2);
756
//   else
757
//       pci_release_regions(dev->pdev);
758
out_no_device:
759
//   ttm_object_device_release(&dev_priv->tdev);
760
out_err4:
761
//   iounmap(dev_priv->mmio_virt);
762
out_err3:
763
//   arch_phys_wc_del(dev_priv->mmio_mtrr);
764
//   if (dev_priv->has_gmr)
765
//       (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
766
//   (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
767
out_err2:
768
//   (void)ttm_bo_device_release(&dev_priv->bdev);
769
out_err1:
770
//   vmw_ttm_global_release(dev_priv);
771
out_err0:
772
//   for (i = vmw_res_context; i < vmw_res_max; ++i)
773
//       idr_destroy(&dev_priv->res_idr[i]);
774
 
775
	kfree(dev_priv);
776
	return ret;
777
}
778
 
779
#if 0
780
static int vmw_driver_unload(struct drm_device *dev)
781
{
782
	struct vmw_private *dev_priv = vmw_priv(dev);
783
	enum vmw_res_type i;
784
 
785
	unregister_pm_notifier(&dev_priv->pm_nb);
786
 
787
	if (dev_priv->ctx.res_ht_initialized)
788
		drm_ht_remove(&dev_priv->ctx.res_ht);
789
	if (dev_priv->ctx.cmd_bounce)
790
		vfree(dev_priv->ctx.cmd_bounce);
791
	if (dev_priv->enable_fb) {
792
		vmw_fb_close(dev_priv);
793
		vmw_kms_restore_vga(dev_priv);
794
		vmw_3d_resource_dec(dev_priv, false);
795
	}
796
	vmw_kms_close(dev_priv);
797
	vmw_overlay_close(dev_priv);
798
	vmw_fence_manager_takedown(dev_priv->fman);
799
	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
800
		drm_irq_uninstall(dev_priv->dev);
801
	if (dev_priv->stealth)
802
		pci_release_region(dev->pdev, 2);
803
	else
804
		pci_release_regions(dev->pdev);
805
 
806
	ttm_object_device_release(&dev_priv->tdev);
807
	iounmap(dev_priv->mmio_virt);
808
	arch_phys_wc_del(dev_priv->mmio_mtrr);
4569 Serge 809
	if (dev_priv->has_mob)
810
		(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
4075 Serge 811
	if (dev_priv->has_gmr)
812
		(void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
813
	(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
814
	(void)ttm_bo_device_release(&dev_priv->bdev);
815
	vmw_ttm_global_release(dev_priv);
816
 
817
	for (i = vmw_res_context; i < vmw_res_max; ++i)
818
		idr_destroy(&dev_priv->res_idr[i]);
819
 
820
	kfree(dev_priv);
821
 
822
	return 0;
823
}
824
 
825
static void vmw_preclose(struct drm_device *dev,
826
			 struct drm_file *file_priv)
827
{
828
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
829
	struct vmw_private *dev_priv = vmw_priv(dev);
830
 
831
	vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
832
}
833
 
834
static void vmw_postclose(struct drm_device *dev,
835
			 struct drm_file *file_priv)
836
{
837
	struct vmw_fpriv *vmw_fp;
838
 
839
	vmw_fp = vmw_fpriv(file_priv);
4569 Serge 840
 
841
	if (vmw_fp->locked_master) {
842
		struct vmw_master *vmaster =
843
			vmw_master(vmw_fp->locked_master);
844
 
845
		ttm_vt_unlock(&vmaster->lock);
846
		drm_master_put(&vmw_fp->locked_master);
847
	}
848
 
4075 Serge 849
	ttm_object_file_release(&vmw_fp->tfile);
850
	kfree(vmw_fp);
851
}
852
#endif
853
 
854
static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
855
{
856
	struct vmw_private *dev_priv = vmw_priv(dev);
857
	struct vmw_fpriv *vmw_fp;
858
	int ret = -ENOMEM;
859
 
860
	vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
861
	if (unlikely(vmw_fp == NULL))
862
		return ret;
863
 
864
	INIT_LIST_HEAD(&vmw_fp->fence_events);
865
//   vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
866
//   if (unlikely(vmw_fp->tfile == NULL))
867
//       goto out_no_tfile;
868
 
869
	file_priv->driver_priv = vmw_fp;
870
//   dev_priv->bdev.dev_mapping = dev->dev_mapping;
871
 
872
	return 0;
873
 
874
out_no_tfile:
875
	kfree(vmw_fp);
876
	return ret;
877
}
878
 
879
#if 0
880
static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
881
			       unsigned long arg)
882
{
883
	struct drm_file *file_priv = filp->private_data;
884
	struct drm_device *dev = file_priv->minor->dev;
885
	unsigned int nr = DRM_IOCTL_NR(cmd);
886
 
887
	/*
888
	 * Do extra checking on driver private ioctls.
889
	 */
890
 
891
	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
892
	    && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
4111 Serge 893
		const struct drm_ioctl_desc *ioctl =
4075 Serge 894
		    &vmw_ioctls[nr - DRM_COMMAND_BASE];
895
 
896
		if (unlikely(ioctl->cmd_drv != cmd)) {
897
			DRM_ERROR("Invalid command format, ioctl %d\n",
898
				  nr - DRM_COMMAND_BASE);
899
			return -EINVAL;
900
		}
901
	}
902
 
903
	return drm_ioctl(filp, cmd, arg);
904
}
905
 
906
static void vmw_lastclose(struct drm_device *dev)
907
{
908
	struct drm_crtc *crtc;
909
	struct drm_mode_set set;
910
	int ret;
911
 
912
	set.x = 0;
913
	set.y = 0;
914
	set.fb = NULL;
915
	set.mode = NULL;
916
	set.connectors = NULL;
917
	set.num_connectors = 0;
918
 
919
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
920
		set.crtc = crtc;
921
		ret = drm_mode_set_config_internal(&set);
922
		WARN_ON(ret != 0);
923
	}
924
 
925
}
4569 Serge 926
#endif
4075 Serge 927
 
928
static void vmw_master_init(struct vmw_master *vmaster)
929
{
4569 Serge 930
//	ttm_lock_init(&vmaster->lock);
4075 Serge 931
	INIT_LIST_HEAD(&vmaster->fb_surf);
932
	mutex_init(&vmaster->fb_surf_mutex);
933
}
934
 
935
static int vmw_master_create(struct drm_device *dev,
936
			     struct drm_master *master)
937
{
938
	struct vmw_master *vmaster;
939
 
940
	vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
941
	if (unlikely(vmaster == NULL))
942
		return -ENOMEM;
943
 
944
	vmw_master_init(vmaster);
4569 Serge 945
//	ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
4075 Serge 946
	master->driver_priv = vmaster;
947
 
948
	return 0;
949
}
950
 
951
static void vmw_master_destroy(struct drm_device *dev,
952
			       struct drm_master *master)
953
{
954
	struct vmw_master *vmaster = vmw_master(master);
955
 
956
	master->driver_priv = NULL;
957
	kfree(vmaster);
958
}
959
 
4569 Serge 960
#if 0
4075 Serge 961
static int vmw_master_set(struct drm_device *dev,
962
			  struct drm_file *file_priv,
963
			  bool from_open)
964
{
965
	struct vmw_private *dev_priv = vmw_priv(dev);
966
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
967
	struct vmw_master *active = dev_priv->active_master;
968
	struct vmw_master *vmaster = vmw_master(file_priv->master);
969
	int ret = 0;
970
 
971
	if (!dev_priv->enable_fb) {
972
		ret = vmw_3d_resource_inc(dev_priv, true);
973
		if (unlikely(ret != 0))
974
			return ret;
975
		vmw_kms_save_vga(dev_priv);
976
		mutex_lock(&dev_priv->hw_mutex);
977
		vmw_write(dev_priv, SVGA_REG_TRACES, 0);
978
		mutex_unlock(&dev_priv->hw_mutex);
979
	}
980
 
981
	if (active) {
982
		BUG_ON(active != &dev_priv->fbdev_master);
983
		ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
984
		if (unlikely(ret != 0))
985
			goto out_no_active_lock;
986
 
987
		ttm_lock_set_kill(&active->lock, true, SIGTERM);
988
		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
989
		if (unlikely(ret != 0)) {
990
			DRM_ERROR("Unable to clean VRAM on "
991
				  "master drop.\n");
992
		}
993
 
994
		dev_priv->active_master = NULL;
995
	}
996
 
997
	ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
998
	if (!from_open) {
999
		ttm_vt_unlock(&vmaster->lock);
1000
		BUG_ON(vmw_fp->locked_master != file_priv->master);
1001
		drm_master_put(&vmw_fp->locked_master);
1002
	}
1003
 
1004
	dev_priv->active_master = vmaster;
1005
 
1006
	return 0;
1007
 
1008
out_no_active_lock:
1009
	if (!dev_priv->enable_fb) {
1010
		vmw_kms_restore_vga(dev_priv);
1011
		vmw_3d_resource_dec(dev_priv, true);
1012
		mutex_lock(&dev_priv->hw_mutex);
1013
		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1014
		mutex_unlock(&dev_priv->hw_mutex);
1015
	}
1016
	return ret;
1017
}
1018
 
1019
static void vmw_master_drop(struct drm_device *dev,
1020
			    struct drm_file *file_priv,
1021
			    bool from_release)
1022
{
1023
	struct vmw_private *dev_priv = vmw_priv(dev);
1024
	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1025
	struct vmw_master *vmaster = vmw_master(file_priv->master);
1026
	int ret;
1027
 
1028
	/**
1029
	 * Make sure the master doesn't disappear while we have
1030
	 * it locked.
1031
	 */
1032
 
1033
	vmw_fp->locked_master = drm_master_get(file_priv->master);
1034
	ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1035
	if (unlikely((ret != 0))) {
1036
		DRM_ERROR("Unable to lock TTM at VT switch.\n");
1037
		drm_master_put(&vmw_fp->locked_master);
1038
	}
1039
 
4569 Serge 1040
	vmw_execbuf_release_pinned_bo(dev_priv);
4075 Serge 1041
 
1042
	if (!dev_priv->enable_fb) {
1043
		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1044
		if (unlikely(ret != 0))
1045
			DRM_ERROR("Unable to clean VRAM on master drop.\n");
1046
		vmw_kms_restore_vga(dev_priv);
1047
		vmw_3d_resource_dec(dev_priv, true);
1048
		mutex_lock(&dev_priv->hw_mutex);
1049
		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1050
		mutex_unlock(&dev_priv->hw_mutex);
1051
	}
1052
 
1053
	dev_priv->active_master = &dev_priv->fbdev_master;
1054
	ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1055
	ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1056
 
1057
	if (dev_priv->enable_fb)
1058
		vmw_fb_on(dev_priv);
1059
}
1060
 
4080 Serge 1061
 
1062
static void vmw_remove(struct pci_dev *pdev)
1063
{
1064
	struct drm_device *dev = pci_get_drvdata(pdev);
1065
 
1066
	drm_put_dev(dev);
1067
}
1068
 
1069
static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1070
			      void *ptr)
1071
{
1072
	struct vmw_private *dev_priv =
1073
		container_of(nb, struct vmw_private, pm_nb);
1074
	struct vmw_master *vmaster = dev_priv->active_master;
1075
 
1076
	switch (val) {
1077
	case PM_HIBERNATION_PREPARE:
1078
	case PM_SUSPEND_PREPARE:
1079
		ttm_suspend_lock(&vmaster->lock);
1080
 
1081
		/**
1082
		 * This empties VRAM and unbinds all GMR bindings.
1083
		 * Buffer contents is moved to swappable memory.
1084
		 */
1085
		vmw_execbuf_release_pinned_bo(dev_priv);
1086
		vmw_resource_evict_all(dev_priv);
1087
		ttm_bo_swapout_all(&dev_priv->bdev);
1088
 
1089
		break;
1090
	case PM_POST_HIBERNATION:
1091
	case PM_POST_SUSPEND:
1092
	case PM_POST_RESTORE:
1093
		ttm_suspend_unlock(&vmaster->lock);
1094
 
1095
		break;
1096
	case PM_RESTORE_PREPARE:
1097
		break;
1098
	default:
1099
		break;
1100
	}
1101
	return 0;
1102
}
1103
 
1104
/**
1105
 * These might not be needed with the virtual SVGA device.
1106
 */
1107
 
1108
static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1109
{
1110
	struct drm_device *dev = pci_get_drvdata(pdev);
1111
	struct vmw_private *dev_priv = vmw_priv(dev);
1112
 
1113
	if (dev_priv->num_3d_resources != 0) {
1114
		DRM_INFO("Can't suspend or hibernate "
1115
			 "while 3D resources are active.\n");
1116
		return -EBUSY;
1117
	}
1118
 
1119
	pci_save_state(pdev);
1120
	pci_disable_device(pdev);
1121
	pci_set_power_state(pdev, PCI_D3hot);
1122
	return 0;
1123
}
1124
 
1125
static int vmw_pci_resume(struct pci_dev *pdev)
1126
{
1127
	pci_set_power_state(pdev, PCI_D0);
1128
	pci_restore_state(pdev);
1129
	return pci_enable_device(pdev);
1130
}
1131
 
1132
static int vmw_pm_suspend(struct device *kdev)
1133
{
1134
	struct pci_dev *pdev = to_pci_dev(kdev);
1135
	struct pm_message dummy;
1136
 
1137
	dummy.event = 0;
1138
 
1139
	return vmw_pci_suspend(pdev, dummy);
1140
}
1141
 
1142
static int vmw_pm_resume(struct device *kdev)
1143
{
1144
	struct pci_dev *pdev = to_pci_dev(kdev);
1145
 
1146
	return vmw_pci_resume(pdev);
1147
}
1148
 
1149
static int vmw_pm_prepare(struct device *kdev)
1150
{
1151
	struct pci_dev *pdev = to_pci_dev(kdev);
1152
	struct drm_device *dev = pci_get_drvdata(pdev);
1153
	struct vmw_private *dev_priv = vmw_priv(dev);
1154
 
1155
	/**
1156
	 * Release 3d reference held by fbdev and potentially
1157
	 * stop fifo.
1158
	 */
1159
	dev_priv->suspended = true;
1160
	if (dev_priv->enable_fb)
1161
			vmw_3d_resource_dec(dev_priv, true);
1162
 
1163
	if (dev_priv->num_3d_resources != 0) {
1164
 
1165
		DRM_INFO("Can't suspend or hibernate "
1166
			 "while 3D resources are active.\n");
1167
 
1168
		if (dev_priv->enable_fb)
1169
			vmw_3d_resource_inc(dev_priv, true);
1170
		dev_priv->suspended = false;
1171
		return -EBUSY;
1172
	}
1173
 
1174
	return 0;
1175
}
1176
 
4075 Serge 1177
#endif
1178
 
1179
 
1180
static struct drm_driver driver = {
1181
	.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1182
	DRIVER_MODESET,
4111 Serge 1183
   .load = vmw_driver_load,
4075 Serge 1184
//   .unload = vmw_driver_unload,
1185
//   .firstopen = vmw_firstopen,
1186
//   .lastclose = vmw_lastclose,
1187
   .irq_preinstall = vmw_irq_preinstall,
1188
   .irq_postinstall = vmw_irq_postinstall,
1189
//   .irq_uninstall = vmw_irq_uninstall,
1190
   .irq_handler = vmw_irq_handler,
1191
//   .get_vblank_counter = vmw_get_vblank_counter,
1192
//   .enable_vblank = vmw_enable_vblank,
1193
//   .disable_vblank = vmw_disable_vblank,
1194
//   .ioctls = vmw_ioctls,
1195
//   .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1196
//   .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
1197
//   .master_create = vmw_master_create,
1198
//   .master_destroy = vmw_master_destroy,
1199
//   .master_set = vmw_master_set,
1200
//   .master_drop = vmw_master_drop,
1201
     .open = vmw_driver_open,
1202
//   .preclose = vmw_preclose,
1203
//   .postclose = vmw_postclose,
1204
 
1205
//   .dumb_create = vmw_dumb_create,
1206
//   .dumb_map_offset = vmw_dumb_map_offset,
1207
//   .dumb_destroy = vmw_dumb_destroy,
1208
 
1209
//   .fops = &vmwgfx_driver_fops,
1210
//   .name = VMWGFX_DRIVER_NAME,
1211
//   .desc = VMWGFX_DRIVER_DESC,
1212
//   .date = VMWGFX_DRIVER_DATE,
1213
//   .major = VMWGFX_DRIVER_MAJOR,
1214
//   .minor = VMWGFX_DRIVER_MINOR,
1215
//   .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1216
};
1217
 
4111 Serge 1218
#if 0
1219
static struct pci_driver vmw_pci_driver = {
1220
	.name = VMWGFX_DRIVER_NAME,
1221
	.id_table = vmw_pci_id_list,
1222
	.probe = vmw_probe,
1223
	.remove = vmw_remove,
1224
	.driver = {
1225
		.pm = &vmw_pm_ops
1226
	}
1227
};
4080 Serge 1228
 
4111 Serge 1229
static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1230
{
1231
	return drm_get_pci_dev(pdev, ent, &driver);
1232
}
1233
#endif
1234
 
4080 Serge 1235
int vmw_init(void)
1236
{
1237
    static pci_dev_t device;
1238
    const struct pci_device_id  *ent;
1239
    int  err;
1240
 
1241
    ENTER();
1242
 
1243
    ent = find_pci_device(&device, vmw_pci_id_list);
1244
    if( unlikely(ent == NULL) )
1245
    {
1246
        dbgprintf("device not found\n");
1247
        return -ENODEV;
1248
    };
1249
 
4111 Serge 1250
    drm_core_init();
1251
 
4080 Serge 1252
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
1253
                                device.pci_dev.device);
1254
 
4111 Serge 1255
    err = drm_get_pci_dev(&device.pci_dev, ent, &driver);
4080 Serge 1256
    LEAVE();
1257
 
1258
    return err;
1259
}
1260
 
1261
 
1262
MODULE_AUTHOR("VMware Inc. and others");
1263
MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1264
MODULE_LICENSE("GPL and additional rights");
4569 Serge 1265
 
1266
 
1267
void *kmemdup(const void *src, size_t len, gfp_t gfp)
1268
{
1269
    void *p;
1270
 
1271
    p = kmalloc(len, gfp);
1272
    if (p)
1273
        memcpy(p, src, len);
1274
    return p;
1275
}
1276