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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | * Authors: Christian König |
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| 26 | */ |
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| 27 | |||
| 28 | #include |
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| 29 | #include |
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| 30 | #include "radeon.h" |
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| 31 | #include "radeon_asic.h" |
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| 32 | #include "sid.h" |
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| 33 | |||
| 34 | /** |
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| 35 | * vce_v1_0_get_rptr - get read pointer |
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| 36 | * |
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| 37 | * @rdev: radeon_device pointer |
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| 38 | * @ring: radeon_ring pointer |
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| 39 | * |
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| 40 | * Returns the current hardware read pointer |
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| 41 | */ |
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| 42 | uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, |
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| 43 | struct radeon_ring *ring) |
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| 44 | { |
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| 45 | if (ring->idx == TN_RING_TYPE_VCE1_INDEX) |
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| 46 | return RREG32(VCE_RB_RPTR); |
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| 47 | else |
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| 48 | return RREG32(VCE_RB_RPTR2); |
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| 49 | } |
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| 50 | |||
| 51 | /** |
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| 52 | * vce_v1_0_get_wptr - get write pointer |
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| 53 | * |
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| 54 | * @rdev: radeon_device pointer |
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| 55 | * @ring: radeon_ring pointer |
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| 56 | * |
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| 57 | * Returns the current hardware write pointer |
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| 58 | */ |
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| 59 | uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, |
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| 60 | struct radeon_ring *ring) |
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| 61 | { |
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| 62 | if (ring->idx == TN_RING_TYPE_VCE1_INDEX) |
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| 63 | return RREG32(VCE_RB_WPTR); |
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| 64 | else |
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| 65 | return RREG32(VCE_RB_WPTR2); |
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| 66 | } |
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| 67 | |||
| 68 | /** |
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| 69 | * vce_v1_0_set_wptr - set write pointer |
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| 70 | * |
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| 71 | * @rdev: radeon_device pointer |
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| 72 | * @ring: radeon_ring pointer |
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| 73 | * |
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| 74 | * Commits the write pointer to the hardware |
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| 75 | */ |
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| 76 | void vce_v1_0_set_wptr(struct radeon_device *rdev, |
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| 77 | struct radeon_ring *ring) |
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| 78 | { |
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| 79 | if (ring->idx == TN_RING_TYPE_VCE1_INDEX) |
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| 80 | WREG32(VCE_RB_WPTR, ring->wptr); |
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| 81 | else |
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| 82 | WREG32(VCE_RB_WPTR2, ring->wptr); |
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| 83 | } |
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| 84 | |||
| 85 | /** |
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| 86 | * vce_v1_0_start - start VCE block |
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| 87 | * |
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| 88 | * @rdev: radeon_device pointer |
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| 89 | * |
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| 90 | * Setup and start the VCE block |
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| 91 | */ |
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| 92 | int vce_v1_0_start(struct radeon_device *rdev) |
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| 93 | { |
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| 94 | struct radeon_ring *ring; |
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| 95 | int i, j, r; |
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| 96 | |||
| 97 | /* set BUSY flag */ |
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| 98 | WREG32_P(VCE_STATUS, 1, ~1); |
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| 99 | |||
| 100 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
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| 101 | WREG32(VCE_RB_RPTR, ring->wptr); |
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| 102 | WREG32(VCE_RB_WPTR, ring->wptr); |
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| 103 | WREG32(VCE_RB_BASE_LO, ring->gpu_addr); |
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| 104 | WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); |
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| 105 | WREG32(VCE_RB_SIZE, ring->ring_size / 4); |
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| 106 | |||
| 107 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
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| 108 | WREG32(VCE_RB_RPTR2, ring->wptr); |
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| 109 | WREG32(VCE_RB_WPTR2, ring->wptr); |
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| 110 | WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); |
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| 111 | WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); |
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| 112 | WREG32(VCE_RB_SIZE2, ring->ring_size / 4); |
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| 113 | |||
| 114 | WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); |
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| 115 | |||
| 116 | WREG32_P(VCE_SOFT_RESET, |
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| 117 | VCE_ECPU_SOFT_RESET | |
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| 118 | VCE_FME_SOFT_RESET, ~( |
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| 119 | VCE_ECPU_SOFT_RESET | |
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| 120 | VCE_FME_SOFT_RESET)); |
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| 121 | |||
| 122 | mdelay(100); |
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| 123 | |||
| 124 | WREG32_P(VCE_SOFT_RESET, 0, ~( |
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| 125 | VCE_ECPU_SOFT_RESET | |
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| 126 | VCE_FME_SOFT_RESET)); |
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| 127 | |||
| 128 | for (i = 0; i < 10; ++i) { |
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| 129 | uint32_t status; |
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| 130 | for (j = 0; j < 100; ++j) { |
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| 131 | status = RREG32(VCE_STATUS); |
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| 132 | if (status & 2) |
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| 133 | break; |
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| 134 | mdelay(10); |
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| 135 | } |
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| 136 | r = 0; |
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| 137 | if (status & 2) |
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| 138 | break; |
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| 139 | |||
| 140 | DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); |
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| 141 | WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET); |
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| 142 | mdelay(10); |
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| 143 | WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); |
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| 144 | mdelay(10); |
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| 145 | r = -1; |
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| 146 | } |
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| 147 | |||
| 148 | /* clear BUSY flag */ |
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| 149 | WREG32_P(VCE_STATUS, 0, ~1); |
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| 150 | |||
| 151 | if (r) { |
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| 152 | DRM_ERROR("VCE not responding, giving up!!!\n"); |
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| 153 | return r; |
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| 154 | } |
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| 155 | |||
| 156 | return 0; |
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| 157 | } |
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| 158 | |||
| 159 | int vce_v1_0_init(struct radeon_device *rdev) |
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| 160 | { |
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| 161 | struct radeon_ring *ring; |
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| 162 | int r; |
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| 163 | |||
| 164 | r = vce_v1_0_start(rdev); |
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| 165 | if (r) |
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| 166 | return r; |
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| 167 | |||
| 168 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
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| 169 | ring->ready = true; |
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| 170 | r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring); |
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| 171 | if (r) { |
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| 172 | ring->ready = false; |
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| 173 | return r; |
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| 174 | } |
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| 175 | |||
| 176 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
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| 177 | ring->ready = true; |
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| 178 | r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring); |
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| 179 | if (r) { |
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| 180 | ring->ready = false; |
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| 181 | return r; |
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| 182 | } |
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| 183 | |||
| 184 | DRM_INFO("VCE initialized successfully.\n"); |
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| 185 | |||
| 186 | return 0; |
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| 187 | } |