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Rev | Author | Line No. | Line |
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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Christian König |
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23 | */ |
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24 | |||
6104 | serge | 25 | #include |
5078 | serge | 26 | #include |
27 | #include "radeon.h" |
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28 | #include "radeon_asic.h" |
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29 | #include "r600d.h" |
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30 | |||
31 | /** |
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32 | * uvd_v1_0_get_rptr - get read pointer |
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33 | * |
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34 | * @rdev: radeon_device pointer |
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35 | * @ring: radeon_ring pointer |
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36 | * |
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37 | * Returns the current hardware read pointer |
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38 | */ |
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39 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, |
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40 | struct radeon_ring *ring) |
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41 | { |
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42 | return RREG32(UVD_RBC_RB_RPTR); |
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43 | } |
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44 | |||
45 | /** |
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46 | * uvd_v1_0_get_wptr - get write pointer |
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47 | * |
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48 | * @rdev: radeon_device pointer |
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49 | * @ring: radeon_ring pointer |
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50 | * |
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51 | * Returns the current hardware write pointer |
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52 | */ |
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53 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, |
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54 | struct radeon_ring *ring) |
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55 | { |
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56 | return RREG32(UVD_RBC_RB_WPTR); |
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57 | } |
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58 | |||
59 | /** |
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60 | * uvd_v1_0_set_wptr - set write pointer |
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61 | * |
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62 | * @rdev: radeon_device pointer |
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63 | * @ring: radeon_ring pointer |
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64 | * |
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65 | * Commits the write pointer to the hardware |
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66 | */ |
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67 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, |
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68 | struct radeon_ring *ring) |
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69 | { |
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70 | WREG32(UVD_RBC_RB_WPTR, ring->wptr); |
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71 | } |
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72 | |||
73 | /** |
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5271 | serge | 74 | * uvd_v1_0_fence_emit - emit an fence & trap command |
75 | * |
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76 | * @rdev: radeon_device pointer |
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77 | * @fence: fence to emit |
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78 | * |
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79 | * Write a fence and a trap command to the ring. |
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80 | */ |
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81 | void uvd_v1_0_fence_emit(struct radeon_device *rdev, |
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82 | struct radeon_fence *fence) |
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83 | { |
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84 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
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85 | uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; |
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86 | |||
87 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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88 | radeon_ring_write(ring, addr & 0xffffffff); |
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89 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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90 | radeon_ring_write(ring, fence->seq); |
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91 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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92 | radeon_ring_write(ring, 0); |
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93 | |||
94 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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95 | radeon_ring_write(ring, 0); |
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96 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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97 | radeon_ring_write(ring, 0); |
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98 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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99 | radeon_ring_write(ring, 2); |
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100 | return; |
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101 | } |
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102 | |||
103 | /** |
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104 | * uvd_v1_0_resume - memory controller programming |
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105 | * |
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106 | * @rdev: radeon_device pointer |
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107 | * |
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108 | * Let the UVD memory controller know it's offsets |
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109 | */ |
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110 | int uvd_v1_0_resume(struct radeon_device *rdev) |
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111 | { |
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112 | uint64_t addr; |
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113 | uint32_t size; |
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114 | int r; |
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115 | |||
116 | r = radeon_uvd_resume(rdev); |
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117 | if (r) |
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118 | return r; |
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119 | |||
120 | /* programm the VCPU memory controller bits 0-27 */ |
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121 | addr = (rdev->uvd.gpu_addr >> 3) + 16; |
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122 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3; |
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123 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
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124 | WREG32(UVD_VCPU_CACHE_SIZE0, size); |
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125 | |||
126 | addr += size; |
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127 | size = RADEON_UVD_STACK_SIZE >> 3; |
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128 | WREG32(UVD_VCPU_CACHE_OFFSET1, addr); |
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129 | WREG32(UVD_VCPU_CACHE_SIZE1, size); |
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130 | |||
131 | addr += size; |
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132 | size = RADEON_UVD_HEAP_SIZE >> 3; |
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133 | WREG32(UVD_VCPU_CACHE_OFFSET2, addr); |
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134 | WREG32(UVD_VCPU_CACHE_SIZE2, size); |
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135 | |||
136 | /* bits 28-31 */ |
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137 | addr = (rdev->uvd.gpu_addr >> 28) & 0xF; |
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138 | WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); |
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139 | |||
140 | /* bits 32-39 */ |
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141 | addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; |
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142 | WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); |
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143 | |||
144 | WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); |
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145 | |||
146 | return 0; |
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147 | } |
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148 | |||
149 | /** |
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5078 | serge | 150 | * uvd_v1_0_init - start and test UVD block |
151 | * |
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152 | * @rdev: radeon_device pointer |
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153 | * |
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154 | * Initialize the hardware, boot up the VCPU and do some testing |
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155 | */ |
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156 | int uvd_v1_0_init(struct radeon_device *rdev) |
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157 | { |
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158 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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159 | uint32_t tmp; |
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160 | int r; |
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161 | |||
162 | /* raise clocks while booting up the VCPU */ |
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163 | if (rdev->family < CHIP_RV740) |
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164 | radeon_set_uvd_clocks(rdev, 10000, 10000); |
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165 | else |
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166 | radeon_set_uvd_clocks(rdev, 53300, 40000); |
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167 | |||
168 | r = uvd_v1_0_start(rdev); |
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169 | if (r) |
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170 | goto done; |
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171 | |||
172 | ring->ready = true; |
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173 | r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring); |
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174 | if (r) { |
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175 | ring->ready = false; |
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176 | goto done; |
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177 | } |
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178 | |||
179 | r = radeon_ring_lock(rdev, ring, 10); |
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180 | if (r) { |
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181 | DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r); |
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182 | goto done; |
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183 | } |
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184 | |||
185 | tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); |
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186 | radeon_ring_write(ring, tmp); |
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187 | radeon_ring_write(ring, 0xFFFFF); |
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188 | |||
189 | tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); |
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190 | radeon_ring_write(ring, tmp); |
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191 | radeon_ring_write(ring, 0xFFFFF); |
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192 | |||
193 | tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); |
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194 | radeon_ring_write(ring, tmp); |
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195 | radeon_ring_write(ring, 0xFFFFF); |
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196 | |||
197 | /* Clear timeout status bits */ |
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198 | radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); |
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199 | radeon_ring_write(ring, 0x8); |
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200 | |||
201 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); |
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202 | radeon_ring_write(ring, 3); |
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203 | |||
204 | radeon_ring_unlock_commit(rdev, ring, false); |
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205 | |||
206 | done: |
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207 | /* lower clocks again */ |
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208 | radeon_set_uvd_clocks(rdev, 0, 0); |
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209 | |||
5271 | serge | 210 | if (!r) { |
211 | switch (rdev->family) { |
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212 | case CHIP_RV610: |
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213 | case CHIP_RV630: |
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214 | case CHIP_RV620: |
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215 | /* 64byte granularity workaround */ |
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216 | WREG32(MC_CONFIG, 0); |
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217 | WREG32(MC_CONFIG, 1 << 4); |
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218 | WREG32(RS_DQ_RD_RET_CONF, 0x3f); |
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219 | WREG32(MC_CONFIG, 0x1f); |
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220 | |||
221 | /* fall through */ |
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222 | case CHIP_RV670: |
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223 | case CHIP_RV635: |
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224 | |||
225 | /* write clean workaround */ |
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226 | WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); |
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227 | break; |
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228 | |||
229 | default: |
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230 | /* TODO: Do we need more? */ |
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231 | break; |
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232 | } |
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233 | |||
5078 | serge | 234 | DRM_INFO("UVD initialized successfully.\n"); |
5271 | serge | 235 | } |
5078 | serge | 236 | |
237 | return r; |
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238 | } |
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239 | |||
240 | /** |
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241 | * uvd_v1_0_fini - stop the hardware block |
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242 | * |
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243 | * @rdev: radeon_device pointer |
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244 | * |
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245 | * Stop the UVD block, mark ring as not ready any more |
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246 | */ |
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247 | void uvd_v1_0_fini(struct radeon_device *rdev) |
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248 | { |
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249 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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250 | |||
251 | uvd_v1_0_stop(rdev); |
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252 | ring->ready = false; |
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253 | } |
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254 | |||
255 | /** |
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256 | * uvd_v1_0_start - start UVD block |
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257 | * |
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258 | * @rdev: radeon_device pointer |
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259 | * |
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260 | * Setup and start the UVD block |
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261 | */ |
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262 | int uvd_v1_0_start(struct radeon_device *rdev) |
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263 | { |
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264 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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265 | uint32_t rb_bufsz; |
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266 | int i, j, r; |
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267 | |||
268 | /* disable byte swapping */ |
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269 | u32 lmi_swap_cntl = 0; |
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270 | u32 mp_swap_cntl = 0; |
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271 | |||
272 | /* disable clock gating */ |
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273 | WREG32(UVD_CGC_GATE, 0); |
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274 | |||
275 | /* disable interupt */ |
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276 | WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); |
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277 | |||
278 | /* Stall UMC and register bus before resetting VCPU */ |
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279 | WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); |
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280 | WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); |
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281 | mdelay(1); |
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282 | |||
283 | /* put LMI, VCPU, RBC etc... into reset */ |
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284 | WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | |
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285 | LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET | |
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286 | CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET); |
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287 | mdelay(5); |
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288 | |||
289 | /* take UVD block out of reset */ |
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290 | WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); |
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291 | mdelay(5); |
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292 | |||
293 | /* initialize UVD memory controller */ |
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294 | WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | |
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295 | (1 << 21) | (1 << 9) | (1 << 20)); |
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296 | |||
297 | #ifdef __BIG_ENDIAN |
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298 | /* swap (8 in 32) RB and IB */ |
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299 | lmi_swap_cntl = 0xa; |
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300 | mp_swap_cntl = 0; |
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301 | #endif |
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302 | WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); |
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303 | WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); |
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304 | |||
305 | WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); |
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306 | WREG32(UVD_MPC_SET_MUXA1, 0x0); |
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307 | WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); |
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308 | WREG32(UVD_MPC_SET_MUXB1, 0x0); |
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309 | WREG32(UVD_MPC_SET_ALU, 0); |
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310 | WREG32(UVD_MPC_SET_MUX, 0x88); |
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311 | |||
312 | /* take all subblocks out of reset, except VCPU */ |
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313 | WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); |
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314 | mdelay(5); |
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315 | |||
316 | /* enable VCPU clock */ |
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317 | WREG32(UVD_VCPU_CNTL, 1 << 9); |
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318 | |||
319 | /* enable UMC */ |
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320 | WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); |
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321 | |||
5271 | serge | 322 | WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); |
323 | |||
5078 | serge | 324 | /* boot up the VCPU */ |
325 | WREG32(UVD_SOFT_RESET, 0); |
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326 | mdelay(10); |
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327 | |||
328 | for (i = 0; i < 10; ++i) { |
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329 | uint32_t status; |
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330 | for (j = 0; j < 100; ++j) { |
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331 | status = RREG32(UVD_STATUS); |
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332 | if (status & 2) |
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333 | break; |
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334 | mdelay(10); |
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335 | } |
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336 | r = 0; |
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337 | if (status & 2) |
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338 | break; |
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339 | |||
340 | DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); |
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341 | WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); |
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342 | mdelay(10); |
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343 | WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); |
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344 | mdelay(10); |
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345 | r = -1; |
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346 | } |
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347 | |||
348 | if (r) { |
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349 | DRM_ERROR("UVD not responding, giving up!!!\n"); |
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350 | return r; |
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351 | } |
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352 | |||
353 | /* enable interupt */ |
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354 | WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); |
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355 | |||
356 | /* force RBC into idle state */ |
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357 | WREG32(UVD_RBC_RB_CNTL, 0x11010101); |
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358 | |||
359 | /* Set the write pointer delay */ |
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360 | WREG32(UVD_RBC_RB_WPTR_CNTL, 0); |
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361 | |||
362 | /* programm the 4GB memory segment for rptr and ring buffer */ |
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363 | WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | |
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364 | (0x7 << 16) | (0x1 << 31)); |
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365 | |||
366 | /* Initialize the ring buffer's read and write pointers */ |
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367 | WREG32(UVD_RBC_RB_RPTR, 0x0); |
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368 | |||
369 | ring->wptr = RREG32(UVD_RBC_RB_RPTR); |
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370 | WREG32(UVD_RBC_RB_WPTR, ring->wptr); |
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371 | |||
372 | /* set the ring address */ |
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373 | WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); |
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374 | |||
375 | /* Set ring buffer size */ |
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376 | rb_bufsz = order_base_2(ring->ring_size); |
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377 | rb_bufsz = (0x1 << 8) | rb_bufsz; |
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378 | WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); |
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379 | |||
380 | return 0; |
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381 | } |
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382 | |||
383 | /** |
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384 | * uvd_v1_0_stop - stop UVD block |
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385 | * |
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386 | * @rdev: radeon_device pointer |
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387 | * |
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388 | * stop the UVD block |
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389 | */ |
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390 | void uvd_v1_0_stop(struct radeon_device *rdev) |
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391 | { |
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392 | /* force RBC into idle state */ |
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393 | WREG32(UVD_RBC_RB_CNTL, 0x11010101); |
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394 | |||
395 | /* Stall UMC and register bus before resetting VCPU */ |
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396 | WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); |
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397 | WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); |
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398 | mdelay(1); |
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399 | |||
400 | /* put VCPU into reset */ |
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401 | WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); |
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402 | mdelay(5); |
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403 | |||
404 | /* disable VCPU clock */ |
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405 | WREG32(UVD_VCPU_CNTL, 0x0); |
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406 | |||
407 | /* Unstall UMC and register bus */ |
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408 | WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); |
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409 | WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); |
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410 | } |
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411 | |||
412 | /** |
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413 | * uvd_v1_0_ring_test - register write test |
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414 | * |
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415 | * @rdev: radeon_device pointer |
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416 | * @ring: radeon_ring pointer |
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417 | * |
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418 | * Test if we can successfully write to the context register |
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419 | */ |
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420 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
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421 | { |
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422 | uint32_t tmp = 0; |
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423 | unsigned i; |
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424 | int r; |
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425 | |||
426 | WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); |
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427 | r = radeon_ring_lock(rdev, ring, 3); |
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428 | if (r) { |
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429 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", |
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430 | ring->idx, r); |
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431 | return r; |
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432 | } |
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433 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
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434 | radeon_ring_write(ring, 0xDEADBEEF); |
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435 | radeon_ring_unlock_commit(rdev, ring, false); |
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436 | for (i = 0; i < rdev->usec_timeout; i++) { |
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437 | tmp = RREG32(UVD_CONTEXT_ID); |
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438 | if (tmp == 0xDEADBEEF) |
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439 | break; |
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440 | DRM_UDELAY(1); |
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441 | } |
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442 | |||
443 | if (i < rdev->usec_timeout) { |
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444 | DRM_INFO("ring test on %d succeeded in %d usecs\n", |
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445 | ring->idx, i); |
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446 | } else { |
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447 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
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448 | ring->idx, tmp); |
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449 | r = -EINVAL; |
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450 | } |
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451 | return r; |
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452 | } |
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453 | |||
454 | /** |
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455 | * uvd_v1_0_semaphore_emit - emit semaphore command |
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456 | * |
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457 | * @rdev: radeon_device pointer |
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458 | * @ring: radeon_ring pointer |
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459 | * @semaphore: semaphore to emit commands for |
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460 | * @emit_wait: true if we should emit a wait command |
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461 | * |
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462 | * Emit a semaphore command (either wait or signal) to the UVD ring. |
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463 | */ |
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464 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
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465 | struct radeon_ring *ring, |
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466 | struct radeon_semaphore *semaphore, |
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467 | bool emit_wait) |
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468 | { |
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6104 | serge | 469 | /* disable semaphores for UVD V1 hardware */ |
470 | return false; |
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5078 | serge | 471 | } |
472 | |||
473 | /** |
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474 | * uvd_v1_0_ib_execute - execute indirect buffer |
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475 | * |
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476 | * @rdev: radeon_device pointer |
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477 | * @ib: indirect buffer to execute |
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478 | * |
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479 | * Write ring commands to execute the indirect buffer |
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480 | */ |
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481 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
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482 | { |
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483 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
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484 | |||
485 | radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); |
||
486 | radeon_ring_write(ring, ib->gpu_addr); |
||
487 | radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); |
||
488 | radeon_ring_write(ring, ib->length_dw); |
||
489 | } |
||
490 | |||
491 | /** |
||
492 | * uvd_v1_0_ib_test - test ib execution |
||
493 | * |
||
494 | * @rdev: radeon_device pointer |
||
495 | * @ring: radeon_ring pointer |
||
496 | * |
||
497 | * Test if we can successfully execute an IB |
||
498 | */ |
||
499 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
||
500 | { |
||
501 | struct radeon_fence *fence = NULL; |
||
502 | int r; |
||
503 | |||
504 | if (rdev->family < CHIP_RV740) |
||
505 | r = radeon_set_uvd_clocks(rdev, 10000, 10000); |
||
506 | else |
||
507 | r = radeon_set_uvd_clocks(rdev, 53300, 40000); |
||
508 | if (r) { |
||
509 | DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); |
||
510 | return r; |
||
511 | } |
||
512 | |||
513 | r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); |
||
514 | if (r) { |
||
515 | DRM_ERROR("radeon: failed to get create msg (%d).\n", r); |
||
516 | goto error; |
||
517 | } |
||
518 | |||
519 | r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); |
||
520 | if (r) { |
||
521 | DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); |
||
522 | goto error; |
||
523 | } |
||
524 | |||
525 | r = radeon_fence_wait(fence, false); |
||
526 | if (r) { |
||
527 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
||
528 | goto error; |
||
529 | } |
||
530 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); |
||
531 | error: |
||
532 | radeon_fence_unref(&fence); |
||
533 | radeon_set_uvd_clocks(rdev, 0, 0); |
||
534 | return r; |
||
535 | }>>>><>><>><>><>><>><>><>><>><>><>1,><1,>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><> |