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Rev | Author | Line No. | Line |
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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Christian König |
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23 | */ |
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24 | |||
25 | #include |
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26 | #include "radeon.h" |
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27 | #include "radeon_asic.h" |
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28 | #include "r600d.h" |
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29 | |||
30 | /** |
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31 | * uvd_v1_0_get_rptr - get read pointer |
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32 | * |
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33 | * @rdev: radeon_device pointer |
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34 | * @ring: radeon_ring pointer |
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35 | * |
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36 | * Returns the current hardware read pointer |
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37 | */ |
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38 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, |
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39 | struct radeon_ring *ring) |
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40 | { |
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41 | return RREG32(UVD_RBC_RB_RPTR); |
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42 | } |
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43 | |||
44 | /** |
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45 | * uvd_v1_0_get_wptr - get write pointer |
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46 | * |
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47 | * @rdev: radeon_device pointer |
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48 | * @ring: radeon_ring pointer |
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49 | * |
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50 | * Returns the current hardware write pointer |
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51 | */ |
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52 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, |
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53 | struct radeon_ring *ring) |
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54 | { |
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55 | return RREG32(UVD_RBC_RB_WPTR); |
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56 | } |
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57 | |||
58 | /** |
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59 | * uvd_v1_0_set_wptr - set write pointer |
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60 | * |
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61 | * @rdev: radeon_device pointer |
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62 | * @ring: radeon_ring pointer |
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63 | * |
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64 | * Commits the write pointer to the hardware |
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65 | */ |
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66 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, |
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67 | struct radeon_ring *ring) |
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68 | { |
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69 | WREG32(UVD_RBC_RB_WPTR, ring->wptr); |
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70 | } |
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71 | |||
72 | /** |
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5271 | serge | 73 | * uvd_v1_0_fence_emit - emit an fence & trap command |
74 | * |
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75 | * @rdev: radeon_device pointer |
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76 | * @fence: fence to emit |
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77 | * |
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78 | * Write a fence and a trap command to the ring. |
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79 | */ |
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80 | void uvd_v1_0_fence_emit(struct radeon_device *rdev, |
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81 | struct radeon_fence *fence) |
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82 | { |
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83 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
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84 | uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; |
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85 | |||
86 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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87 | radeon_ring_write(ring, addr & 0xffffffff); |
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88 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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89 | radeon_ring_write(ring, fence->seq); |
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90 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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91 | radeon_ring_write(ring, 0); |
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92 | |||
93 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
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94 | radeon_ring_write(ring, 0); |
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95 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
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96 | radeon_ring_write(ring, 0); |
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97 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
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98 | radeon_ring_write(ring, 2); |
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99 | return; |
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100 | } |
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101 | |||
102 | /** |
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103 | * uvd_v1_0_resume - memory controller programming |
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104 | * |
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105 | * @rdev: radeon_device pointer |
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106 | * |
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107 | * Let the UVD memory controller know it's offsets |
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108 | */ |
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109 | int uvd_v1_0_resume(struct radeon_device *rdev) |
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110 | { |
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111 | uint64_t addr; |
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112 | uint32_t size; |
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113 | int r; |
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114 | |||
115 | r = radeon_uvd_resume(rdev); |
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116 | if (r) |
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117 | return r; |
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118 | |||
119 | /* programm the VCPU memory controller bits 0-27 */ |
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120 | addr = (rdev->uvd.gpu_addr >> 3) + 16; |
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121 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3; |
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122 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
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123 | WREG32(UVD_VCPU_CACHE_SIZE0, size); |
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124 | |||
125 | addr += size; |
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126 | size = RADEON_UVD_STACK_SIZE >> 3; |
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127 | WREG32(UVD_VCPU_CACHE_OFFSET1, addr); |
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128 | WREG32(UVD_VCPU_CACHE_SIZE1, size); |
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129 | |||
130 | addr += size; |
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131 | size = RADEON_UVD_HEAP_SIZE >> 3; |
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132 | WREG32(UVD_VCPU_CACHE_OFFSET2, addr); |
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133 | WREG32(UVD_VCPU_CACHE_SIZE2, size); |
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134 | |||
135 | /* bits 28-31 */ |
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136 | addr = (rdev->uvd.gpu_addr >> 28) & 0xF; |
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137 | WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); |
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138 | |||
139 | /* bits 32-39 */ |
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140 | addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; |
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141 | WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); |
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142 | |||
143 | WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); |
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144 | |||
145 | return 0; |
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146 | } |
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147 | |||
148 | /** |
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5078 | serge | 149 | * uvd_v1_0_init - start and test UVD block |
150 | * |
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151 | * @rdev: radeon_device pointer |
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152 | * |
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153 | * Initialize the hardware, boot up the VCPU and do some testing |
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154 | */ |
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155 | int uvd_v1_0_init(struct radeon_device *rdev) |
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156 | { |
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157 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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158 | uint32_t tmp; |
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159 | int r; |
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160 | |||
161 | /* raise clocks while booting up the VCPU */ |
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162 | if (rdev->family < CHIP_RV740) |
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163 | radeon_set_uvd_clocks(rdev, 10000, 10000); |
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164 | else |
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165 | radeon_set_uvd_clocks(rdev, 53300, 40000); |
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166 | |||
167 | r = uvd_v1_0_start(rdev); |
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168 | if (r) |
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169 | goto done; |
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170 | |||
171 | ring->ready = true; |
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172 | r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring); |
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173 | if (r) { |
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174 | ring->ready = false; |
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175 | goto done; |
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176 | } |
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177 | |||
178 | r = radeon_ring_lock(rdev, ring, 10); |
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179 | if (r) { |
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180 | DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r); |
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181 | goto done; |
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182 | } |
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183 | |||
184 | tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); |
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185 | radeon_ring_write(ring, tmp); |
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186 | radeon_ring_write(ring, 0xFFFFF); |
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187 | |||
188 | tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); |
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189 | radeon_ring_write(ring, tmp); |
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190 | radeon_ring_write(ring, 0xFFFFF); |
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191 | |||
192 | tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); |
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193 | radeon_ring_write(ring, tmp); |
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194 | radeon_ring_write(ring, 0xFFFFF); |
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195 | |||
196 | /* Clear timeout status bits */ |
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197 | radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); |
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198 | radeon_ring_write(ring, 0x8); |
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199 | |||
200 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); |
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201 | radeon_ring_write(ring, 3); |
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202 | |||
203 | radeon_ring_unlock_commit(rdev, ring, false); |
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204 | |||
205 | done: |
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206 | /* lower clocks again */ |
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207 | radeon_set_uvd_clocks(rdev, 0, 0); |
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208 | |||
5271 | serge | 209 | if (!r) { |
210 | switch (rdev->family) { |
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211 | case CHIP_RV610: |
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212 | case CHIP_RV630: |
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213 | case CHIP_RV620: |
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214 | /* 64byte granularity workaround */ |
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215 | WREG32(MC_CONFIG, 0); |
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216 | WREG32(MC_CONFIG, 1 << 4); |
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217 | WREG32(RS_DQ_RD_RET_CONF, 0x3f); |
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218 | WREG32(MC_CONFIG, 0x1f); |
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219 | |||
220 | /* fall through */ |
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221 | case CHIP_RV670: |
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222 | case CHIP_RV635: |
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223 | |||
224 | /* write clean workaround */ |
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225 | WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); |
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226 | break; |
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227 | |||
228 | default: |
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229 | /* TODO: Do we need more? */ |
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230 | break; |
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231 | } |
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232 | |||
5078 | serge | 233 | DRM_INFO("UVD initialized successfully.\n"); |
5271 | serge | 234 | } |
5078 | serge | 235 | |
236 | return r; |
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237 | } |
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238 | |||
239 | /** |
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240 | * uvd_v1_0_fini - stop the hardware block |
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241 | * |
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242 | * @rdev: radeon_device pointer |
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243 | * |
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244 | * Stop the UVD block, mark ring as not ready any more |
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245 | */ |
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246 | void uvd_v1_0_fini(struct radeon_device *rdev) |
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247 | { |
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248 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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249 | |||
250 | uvd_v1_0_stop(rdev); |
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251 | ring->ready = false; |
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252 | } |
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253 | |||
254 | /** |
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255 | * uvd_v1_0_start - start UVD block |
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256 | * |
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257 | * @rdev: radeon_device pointer |
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258 | * |
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259 | * Setup and start the UVD block |
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260 | */ |
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261 | int uvd_v1_0_start(struct radeon_device *rdev) |
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262 | { |
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263 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
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264 | uint32_t rb_bufsz; |
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265 | int i, j, r; |
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266 | |||
267 | /* disable byte swapping */ |
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268 | u32 lmi_swap_cntl = 0; |
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269 | u32 mp_swap_cntl = 0; |
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270 | |||
271 | /* disable clock gating */ |
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272 | WREG32(UVD_CGC_GATE, 0); |
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273 | |||
274 | /* disable interupt */ |
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275 | WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); |
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276 | |||
277 | /* Stall UMC and register bus before resetting VCPU */ |
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278 | WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); |
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279 | WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); |
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280 | mdelay(1); |
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281 | |||
282 | /* put LMI, VCPU, RBC etc... into reset */ |
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283 | WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | |
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284 | LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET | |
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285 | CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET); |
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286 | mdelay(5); |
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287 | |||
288 | /* take UVD block out of reset */ |
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289 | WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); |
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290 | mdelay(5); |
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291 | |||
292 | /* initialize UVD memory controller */ |
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293 | WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | |
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294 | (1 << 21) | (1 << 9) | (1 << 20)); |
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295 | |||
296 | #ifdef __BIG_ENDIAN |
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297 | /* swap (8 in 32) RB and IB */ |
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298 | lmi_swap_cntl = 0xa; |
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299 | mp_swap_cntl = 0; |
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300 | #endif |
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301 | WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); |
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302 | WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); |
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303 | |||
304 | WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); |
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305 | WREG32(UVD_MPC_SET_MUXA1, 0x0); |
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306 | WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); |
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307 | WREG32(UVD_MPC_SET_MUXB1, 0x0); |
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308 | WREG32(UVD_MPC_SET_ALU, 0); |
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309 | WREG32(UVD_MPC_SET_MUX, 0x88); |
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310 | |||
311 | /* take all subblocks out of reset, except VCPU */ |
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312 | WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); |
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313 | mdelay(5); |
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314 | |||
315 | /* enable VCPU clock */ |
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316 | WREG32(UVD_VCPU_CNTL, 1 << 9); |
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317 | |||
318 | /* enable UMC */ |
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319 | WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); |
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320 | |||
5271 | serge | 321 | WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); |
322 | |||
5078 | serge | 323 | /* boot up the VCPU */ |
324 | WREG32(UVD_SOFT_RESET, 0); |
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325 | mdelay(10); |
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326 | |||
327 | for (i = 0; i < 10; ++i) { |
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328 | uint32_t status; |
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329 | for (j = 0; j < 100; ++j) { |
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330 | status = RREG32(UVD_STATUS); |
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331 | if (status & 2) |
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332 | break; |
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333 | mdelay(10); |
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334 | } |
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335 | r = 0; |
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336 | if (status & 2) |
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337 | break; |
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338 | |||
339 | DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); |
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340 | WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); |
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341 | mdelay(10); |
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342 | WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); |
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343 | mdelay(10); |
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344 | r = -1; |
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345 | } |
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346 | |||
347 | if (r) { |
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348 | DRM_ERROR("UVD not responding, giving up!!!\n"); |
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349 | return r; |
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350 | } |
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351 | |||
352 | /* enable interupt */ |
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353 | WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); |
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354 | |||
355 | /* force RBC into idle state */ |
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356 | WREG32(UVD_RBC_RB_CNTL, 0x11010101); |
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357 | |||
358 | /* Set the write pointer delay */ |
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359 | WREG32(UVD_RBC_RB_WPTR_CNTL, 0); |
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360 | |||
361 | /* programm the 4GB memory segment for rptr and ring buffer */ |
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362 | WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | |
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363 | (0x7 << 16) | (0x1 << 31)); |
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364 | |||
365 | /* Initialize the ring buffer's read and write pointers */ |
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366 | WREG32(UVD_RBC_RB_RPTR, 0x0); |
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367 | |||
368 | ring->wptr = RREG32(UVD_RBC_RB_RPTR); |
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369 | WREG32(UVD_RBC_RB_WPTR, ring->wptr); |
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370 | |||
371 | /* set the ring address */ |
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372 | WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); |
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373 | |||
374 | /* Set ring buffer size */ |
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375 | rb_bufsz = order_base_2(ring->ring_size); |
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376 | rb_bufsz = (0x1 << 8) | rb_bufsz; |
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377 | WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); |
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378 | |||
379 | return 0; |
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380 | } |
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381 | |||
382 | /** |
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383 | * uvd_v1_0_stop - stop UVD block |
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384 | * |
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385 | * @rdev: radeon_device pointer |
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386 | * |
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387 | * stop the UVD block |
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388 | */ |
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389 | void uvd_v1_0_stop(struct radeon_device *rdev) |
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390 | { |
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391 | /* force RBC into idle state */ |
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392 | WREG32(UVD_RBC_RB_CNTL, 0x11010101); |
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393 | |||
394 | /* Stall UMC and register bus before resetting VCPU */ |
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395 | WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); |
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396 | WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); |
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397 | mdelay(1); |
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398 | |||
399 | /* put VCPU into reset */ |
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400 | WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); |
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401 | mdelay(5); |
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402 | |||
403 | /* disable VCPU clock */ |
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404 | WREG32(UVD_VCPU_CNTL, 0x0); |
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405 | |||
406 | /* Unstall UMC and register bus */ |
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407 | WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); |
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408 | WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); |
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409 | } |
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410 | |||
411 | /** |
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412 | * uvd_v1_0_ring_test - register write test |
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413 | * |
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414 | * @rdev: radeon_device pointer |
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415 | * @ring: radeon_ring pointer |
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416 | * |
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417 | * Test if we can successfully write to the context register |
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418 | */ |
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419 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
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420 | { |
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421 | uint32_t tmp = 0; |
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422 | unsigned i; |
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423 | int r; |
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424 | |||
425 | WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); |
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426 | r = radeon_ring_lock(rdev, ring, 3); |
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427 | if (r) { |
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428 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", |
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429 | ring->idx, r); |
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430 | return r; |
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431 | } |
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432 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
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433 | radeon_ring_write(ring, 0xDEADBEEF); |
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434 | radeon_ring_unlock_commit(rdev, ring, false); |
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435 | for (i = 0; i < rdev->usec_timeout; i++) { |
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436 | tmp = RREG32(UVD_CONTEXT_ID); |
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437 | if (tmp == 0xDEADBEEF) |
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438 | break; |
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439 | DRM_UDELAY(1); |
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440 | } |
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441 | |||
442 | if (i < rdev->usec_timeout) { |
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443 | DRM_INFO("ring test on %d succeeded in %d usecs\n", |
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444 | ring->idx, i); |
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445 | } else { |
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446 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
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447 | ring->idx, tmp); |
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448 | r = -EINVAL; |
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449 | } |
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450 | return r; |
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451 | } |
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452 | |||
453 | /** |
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454 | * uvd_v1_0_semaphore_emit - emit semaphore command |
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455 | * |
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456 | * @rdev: radeon_device pointer |
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457 | * @ring: radeon_ring pointer |
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458 | * @semaphore: semaphore to emit commands for |
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459 | * @emit_wait: true if we should emit a wait command |
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460 | * |
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461 | * Emit a semaphore command (either wait or signal) to the UVD ring. |
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462 | */ |
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463 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
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464 | struct radeon_ring *ring, |
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465 | struct radeon_semaphore *semaphore, |
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466 | bool emit_wait) |
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467 | { |
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468 | uint64_t addr = semaphore->gpu_addr; |
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469 | |||
470 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); |
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471 | radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); |
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472 | |||
473 | radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); |
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474 | radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); |
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475 | |||
476 | radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); |
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477 | radeon_ring_write(ring, emit_wait ? 1 : 0); |
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478 | |||
479 | return true; |
||
480 | } |
||
481 | |||
482 | /** |
||
483 | * uvd_v1_0_ib_execute - execute indirect buffer |
||
484 | * |
||
485 | * @rdev: radeon_device pointer |
||
486 | * @ib: indirect buffer to execute |
||
487 | * |
||
488 | * Write ring commands to execute the indirect buffer |
||
489 | */ |
||
490 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
||
491 | { |
||
492 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
||
493 | |||
494 | radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); |
||
495 | radeon_ring_write(ring, ib->gpu_addr); |
||
496 | radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); |
||
497 | radeon_ring_write(ring, ib->length_dw); |
||
498 | } |
||
499 | |||
500 | /** |
||
501 | * uvd_v1_0_ib_test - test ib execution |
||
502 | * |
||
503 | * @rdev: radeon_device pointer |
||
504 | * @ring: radeon_ring pointer |
||
505 | * |
||
506 | * Test if we can successfully execute an IB |
||
507 | */ |
||
508 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
||
509 | { |
||
510 | struct radeon_fence *fence = NULL; |
||
511 | int r; |
||
512 | |||
513 | if (rdev->family < CHIP_RV740) |
||
514 | r = radeon_set_uvd_clocks(rdev, 10000, 10000); |
||
515 | else |
||
516 | r = radeon_set_uvd_clocks(rdev, 53300, 40000); |
||
517 | if (r) { |
||
518 | DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); |
||
519 | return r; |
||
520 | } |
||
521 | |||
522 | r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); |
||
523 | if (r) { |
||
524 | DRM_ERROR("radeon: failed to get create msg (%d).\n", r); |
||
525 | goto error; |
||
526 | } |
||
527 | |||
528 | r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); |
||
529 | if (r) { |
||
530 | DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); |
||
531 | goto error; |
||
532 | } |
||
533 | |||
534 | r = radeon_fence_wait(fence, false); |
||
535 | if (r) { |
||
536 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
||
537 | goto error; |
||
538 | } |
||
539 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); |
||
540 | error: |
||
541 | radeon_fence_unref(&fence); |
||
542 | radeon_set_uvd_clocks(rdev, 0, 0); |
||
543 | return r; |
||
544 | }>>>><>><>><>><>><>><>><>><>><>><>1,><1,>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><> |