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5078 | serge | 1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #ifndef _SUMOD_H_ |
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25 | #define _SUMOD_H_ |
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26 | |||
27 | /* pm registers */ |
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28 | |||
29 | /* rcu */ |
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30 | #define RCU_FW_VERSION 0x30c |
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31 | |||
32 | #define RCU_PWR_GATING_SEQ0 0x408 |
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33 | #define RCU_PWR_GATING_SEQ1 0x40c |
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34 | #define RCU_PWR_GATING_CNTL 0x410 |
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35 | # define PWR_GATING_EN (1 << 0) |
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36 | # define RSVD_MASK (0x3 << 1) |
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37 | # define PCV(x) ((x) << 3) |
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38 | # define PCV_MASK (0x1f << 3) |
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39 | # define PCV_SHIFT 3 |
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40 | # define PCP(x) ((x) << 8) |
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41 | # define PCP_MASK (0xf << 8) |
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42 | # define PCP_SHIFT 8 |
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43 | # define RPW(x) ((x) << 16) |
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44 | # define RPW_MASK (0xf << 16) |
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45 | # define RPW_SHIFT 16 |
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46 | # define ID(x) ((x) << 24) |
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47 | # define ID_MASK (0xf << 24) |
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48 | # define ID_SHIFT 24 |
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49 | # define PGS(x) ((x) << 28) |
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50 | # define PGS_MASK (0xf << 28) |
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51 | # define PGS_SHIFT 28 |
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52 | |||
53 | #define RCU_ALTVDDNB_NOTIFY 0x430 |
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54 | #define RCU_LCLK_SCALING_CNTL 0x434 |
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55 | # define LCLK_SCALING_EN (1 << 0) |
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56 | # define LCLK_SCALING_TYPE (1 << 1) |
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57 | # define LCLK_SCALING_TIMER_PRESCALER(x) ((x) << 4) |
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58 | # define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4) |
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59 | # define LCLK_SCALING_TIMER_PRESCALER_SHIFT 4 |
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60 | # define LCLK_SCALING_TIMER_PERIOD(x) ((x) << 16) |
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61 | # define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16) |
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62 | # define LCLK_SCALING_TIMER_PERIOD_SHIFT 16 |
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63 | |||
64 | #define RCU_PWR_GATING_CNTL_2 0x4a0 |
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65 | # define MPPU(x) ((x) << 0) |
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66 | # define MPPU_MASK (0xffff << 0) |
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67 | # define MPPU_SHIFT 0 |
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68 | # define MPPD(x) ((x) << 16) |
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69 | # define MPPD_MASK (0xffff << 16) |
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70 | # define MPPD_SHIFT 16 |
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71 | #define RCU_PWR_GATING_CNTL_3 0x4a4 |
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72 | # define DPPU(x) ((x) << 0) |
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73 | # define DPPU_MASK (0xffff << 0) |
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74 | # define DPPU_SHIFT 0 |
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75 | # define DPPD(x) ((x) << 16) |
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76 | # define DPPD_MASK (0xffff << 16) |
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77 | # define DPPD_SHIFT 16 |
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78 | #define RCU_PWR_GATING_CNTL_4 0x4a8 |
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79 | # define RT(x) ((x) << 0) |
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80 | # define RT_MASK (0xffff << 0) |
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81 | # define RT_SHIFT 0 |
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82 | # define IT(x) ((x) << 16) |
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83 | # define IT_MASK (0xffff << 16) |
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84 | # define IT_SHIFT 16 |
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85 | |||
86 | /* yes these two have the same address */ |
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87 | #define RCU_PWR_GATING_CNTL_5 0x504 |
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88 | #define RCU_GPU_BOOST_DISABLE 0x508 |
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89 | |||
90 | #define MCU_M3ARB_INDEX 0x504 |
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91 | #define MCU_M3ARB_PARAMS 0x508 |
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92 | |||
93 | #define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C |
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94 | |||
95 | #define RCU_SclkDpmTdpLimit01 0x514 |
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96 | #define RCU_SclkDpmTdpLimit23 0x518 |
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97 | #define RCU_SclkDpmTdpLimit47 0x51C |
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98 | #define RCU_SclkDpmTdpLimitPG 0x520 |
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99 | |||
100 | #define GNB_TDP_LIMIT 0x540 |
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101 | #define RCU_BOOST_MARGIN 0x544 |
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102 | #define RCU_THROTTLE_MARGIN 0x548 |
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103 | |||
104 | #define SMU_PCIE_PG_ARGS 0x58C |
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105 | #define SMU_PCIE_PG_ARGS_2 0x598 |
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106 | #define SMU_PCIE_PG_ARGS_3 0x59C |
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107 | |||
108 | /* mmio */ |
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109 | #define RCU_STATUS 0x11c |
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110 | # define GMC_PWR_GATER_BUSY (1 << 8) |
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111 | # define GFX_PWR_GATER_BUSY (1 << 9) |
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112 | # define UVD_PWR_GATER_BUSY (1 << 10) |
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113 | # define PCIE_PWR_GATER_BUSY (1 << 11) |
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114 | # define GMC_PWR_GATER_STATE (1 << 12) |
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115 | # define GFX_PWR_GATER_STATE (1 << 13) |
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116 | # define UVD_PWR_GATER_STATE (1 << 14) |
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117 | # define PCIE_PWR_GATER_STATE (1 << 15) |
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118 | # define GFX1_PWR_GATER_BUSY (1 << 16) |
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119 | # define GFX2_PWR_GATER_BUSY (1 << 17) |
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120 | # define GFX1_PWR_GATER_STATE (1 << 18) |
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121 | # define GFX2_PWR_GATER_STATE (1 << 19) |
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122 | |||
123 | #define GFX_INT_REQ 0x120 |
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124 | # define INT_REQ (1 << 0) |
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125 | # define SERV_INDEX(x) ((x) << 1) |
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126 | # define SERV_INDEX_MASK (0xff << 1) |
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127 | # define SERV_INDEX_SHIFT 1 |
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128 | #define GFX_INT_STATUS 0x124 |
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129 | # define INT_ACK (1 << 0) |
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130 | # define INT_DONE (1 << 1) |
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131 | |||
132 | #define CG_SCLK_CNTL 0x600 |
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133 | # define SCLK_DIVIDER(x) ((x) << 0) |
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134 | # define SCLK_DIVIDER_MASK (0x7f << 0) |
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135 | # define SCLK_DIVIDER_SHIFT 0 |
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136 | #define CG_SCLK_STATUS 0x604 |
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137 | # define SCLK_OVERCLK_DETECT (1 << 2) |
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138 | |||
139 | #define CG_DCLK_CNTL 0x610 |
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140 | # define DCLK_DIVIDER_MASK 0x7f |
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141 | # define DCLK_DIR_CNTL_EN (1 << 8) |
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142 | #define CG_DCLK_STATUS 0x614 |
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143 | # define DCLK_STATUS (1 << 0) |
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144 | #define CG_VCLK_CNTL 0x618 |
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145 | # define VCLK_DIVIDER_MASK 0x7f |
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146 | # define VCLK_DIR_CNTL_EN (1 << 8) |
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147 | #define CG_VCLK_STATUS 0x61c |
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148 | |||
149 | #define GENERAL_PWRMGT 0x63c |
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150 | # define STATIC_PM_EN (1 << 1) |
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151 | |||
152 | #define SCLK_PWRMGT_CNTL 0x644 |
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153 | # define SCLK_PWRMGT_OFF (1 << 0) |
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154 | # define SCLK_LOW_D1 (1 << 1) |
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155 | # define FIR_RESET (1 << 4) |
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156 | # define FIR_FORCE_TREND_SEL (1 << 5) |
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157 | # define FIR_TREND_MODE (1 << 6) |
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158 | # define DYN_GFX_CLK_OFF_EN (1 << 7) |
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159 | # define GFX_CLK_FORCE_ON (1 << 8) |
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160 | # define GFX_CLK_REQUEST_OFF (1 << 9) |
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161 | # define GFX_CLK_FORCE_OFF (1 << 10) |
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162 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) |
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163 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) |
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164 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) |
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165 | # define GFX_VOLTAGE_CHANGE_EN (1 << 16) |
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166 | # define GFX_VOLTAGE_CHANGE_MODE (1 << 17) |
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167 | |||
168 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c |
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169 | # define TARG_SCLK_INDEX(x) ((x) << 6) |
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170 | # define TARG_SCLK_INDEX_MASK (0x7 << 6) |
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171 | # define TARG_SCLK_INDEX_SHIFT 6 |
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172 | # define CURR_SCLK_INDEX(x) ((x) << 9) |
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173 | # define CURR_SCLK_INDEX_MASK (0x7 << 9) |
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174 | # define CURR_SCLK_INDEX_SHIFT 9 |
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175 | # define TARG_INDEX(x) ((x) << 12) |
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176 | # define TARG_INDEX_MASK (0x7 << 12) |
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177 | # define TARG_INDEX_SHIFT 12 |
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178 | # define CURR_INDEX(x) ((x) << 15) |
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179 | # define CURR_INDEX_MASK (0x7 << 15) |
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180 | # define CURR_INDEX_SHIFT 15 |
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181 | |||
182 | #define CG_SCLK_DPM_CTRL 0x684 |
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183 | # define SCLK_FSTATE_0_DIV(x) ((x) << 0) |
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184 | # define SCLK_FSTATE_0_DIV_MASK (0x7f << 0) |
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185 | # define SCLK_FSTATE_0_DIV_SHIFT 0 |
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186 | # define SCLK_FSTATE_0_VLD (1 << 7) |
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187 | # define SCLK_FSTATE_1_DIV(x) ((x) << 8) |
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188 | # define SCLK_FSTATE_1_DIV_MASK (0x7f << 8) |
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189 | # define SCLK_FSTATE_1_DIV_SHIFT 8 |
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190 | # define SCLK_FSTATE_1_VLD (1 << 15) |
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191 | # define SCLK_FSTATE_2_DIV(x) ((x) << 16) |
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192 | # define SCLK_FSTATE_2_DIV_MASK (0x7f << 16) |
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193 | # define SCLK_FSTATE_2_DIV_SHIFT 16 |
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194 | # define SCLK_FSTATE_2_VLD (1 << 23) |
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195 | # define SCLK_FSTATE_3_DIV(x) ((x) << 24) |
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196 | # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24) |
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197 | # define SCLK_FSTATE_3_DIV_SHIFT 24 |
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198 | # define SCLK_FSTATE_3_VLD (1 << 31) |
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199 | #define CG_SCLK_DPM_CTRL_2 0x688 |
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200 | #define CG_GCOOR 0x68c |
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201 | # define PHC(x) ((x) << 0) |
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202 | # define PHC_MASK (0x1f << 0) |
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203 | # define PHC_SHIFT 0 |
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204 | # define SDC(x) ((x) << 9) |
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205 | # define SDC_MASK (0x3ff << 9) |
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206 | # define SDC_SHIFT 9 |
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207 | # define SU(x) ((x) << 23) |
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208 | # define SU_MASK (0xf << 23) |
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209 | # define SU_SHIFT 23 |
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210 | # define DIV_ID(x) ((x) << 28) |
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211 | # define DIV_ID_MASK (0x7 << 28) |
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212 | # define DIV_ID_SHIFT 28 |
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213 | |||
214 | #define CG_FTV 0x690 |
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215 | #define CG_FFCT_0 0x694 |
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216 | # define UTC_0(x) ((x) << 0) |
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217 | # define UTC_0_MASK (0x3ff << 0) |
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218 | # define UTC_0_SHIFT 0 |
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219 | # define DTC_0(x) ((x) << 10) |
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220 | # define DTC_0_MASK (0x3ff << 10) |
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221 | # define DTC_0_SHIFT 10 |
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222 | |||
223 | #define CG_GIT 0x6d8 |
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224 | # define CG_GICST(x) ((x) << 0) |
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225 | # define CG_GICST_MASK (0xffff << 0) |
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226 | # define CG_GICST_SHIFT 0 |
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227 | # define CG_GIPOT(x) ((x) << 16) |
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228 | # define CG_GIPOT_MASK (0xffff << 16) |
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229 | # define CG_GIPOT_SHIFT 16 |
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230 | |||
231 | #define CG_SCLK_DPM_CTRL_3 0x6e0 |
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232 | # define FORCE_SCLK_STATE(x) ((x) << 0) |
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233 | # define FORCE_SCLK_STATE_MASK (0x7 << 0) |
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234 | # define FORCE_SCLK_STATE_SHIFT 0 |
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235 | # define FORCE_SCLK_STATE_EN (1 << 3) |
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236 | # define GNB_TT(x) ((x) << 8) |
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237 | # define GNB_TT_MASK (0xff << 8) |
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238 | # define GNB_TT_SHIFT 8 |
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239 | # define GNB_THERMTHRO_MASK (1 << 16) |
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240 | # define CNB_THERMTHRO_MASK_SCLK (1 << 17) |
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241 | # define DPM_SCLK_ENABLE (1 << 18) |
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242 | # define GNB_SLOW_FSTATE_0_MASK (1 << 23) |
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243 | # define GNB_SLOW_FSTATE_0_SHIFT 23 |
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244 | # define FORCE_NB_PSTATE_1 (1 << 31) |
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245 | |||
246 | #define CG_SSP 0x6e8 |
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247 | # define SST(x) ((x) << 0) |
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248 | # define SST_MASK (0xffff << 0) |
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249 | # define SST_SHIFT 0 |
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250 | # define SSTU(x) ((x) << 16) |
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251 | # define SSTU_MASK (0xffff << 16) |
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252 | # define SSTU_SHIFT 16 |
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253 | |||
254 | #define CG_ACPI_CNTL 0x70c |
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255 | # define SCLK_ACPI_DIV(x) ((x) << 0) |
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256 | # define SCLK_ACPI_DIV_MASK (0x7f << 0) |
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257 | # define SCLK_ACPI_DIV_SHIFT 0 |
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258 | |||
259 | #define CG_SCLK_DPM_CTRL_4 0x71c |
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260 | # define DC_HDC(x) ((x) << 14) |
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261 | # define DC_HDC_MASK (0x3fff << 14) |
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262 | # define DC_HDC_SHIFT 14 |
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263 | # define DC_HU(x) ((x) << 28) |
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264 | # define DC_HU_MASK (0xf << 28) |
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265 | # define DC_HU_SHIFT 28 |
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266 | #define CG_SCLK_DPM_CTRL_5 0x720 |
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267 | # define SCLK_FSTATE_BOOTUP(x) ((x) << 0) |
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268 | # define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0) |
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269 | # define SCLK_FSTATE_BOOTUP_SHIFT 0 |
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270 | # define TT_TP(x) ((x) << 3) |
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271 | # define TT_TP_MASK (0xffff << 3) |
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272 | # define TT_TP_SHIFT 3 |
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273 | # define TT_TU(x) ((x) << 19) |
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274 | # define TT_TU_MASK (0xff << 19) |
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275 | # define TT_TU_SHIFT 19 |
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276 | #define CG_SCLK_DPM_CTRL_6 0x724 |
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277 | #define CG_AT_0 0x728 |
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278 | # define CG_R(x) ((x) << 0) |
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279 | # define CG_R_MASK (0xffff << 0) |
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280 | # define CG_R_SHIFT 0 |
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281 | # define CG_L(x) ((x) << 16) |
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282 | # define CG_L_MASK (0xffff << 16) |
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283 | # define CG_L_SHIFT 16 |
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284 | #define CG_AT_1 0x72c |
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285 | #define CG_AT_2 0x730 |
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286 | #define CG_THERMAL_INT 0x734 |
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287 | #define DIG_THERM_INTH(x) ((x) << 8) |
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288 | #define DIG_THERM_INTH_MASK 0x0000FF00 |
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289 | #define DIG_THERM_INTH_SHIFT 8 |
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290 | #define DIG_THERM_INTL(x) ((x) << 16) |
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291 | #define DIG_THERM_INTL_MASK 0x00FF0000 |
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292 | #define DIG_THERM_INTL_SHIFT 16 |
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293 | #define THERM_INT_MASK_HIGH (1 << 24) |
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294 | #define THERM_INT_MASK_LOW (1 << 25) |
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295 | #define CG_AT_3 0x738 |
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296 | #define CG_AT_4 0x73c |
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297 | #define CG_AT_5 0x740 |
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298 | #define CG_AT_6 0x744 |
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299 | #define CG_AT_7 0x748 |
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300 | |||
301 | #define CG_BSP_0 0x750 |
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302 | # define BSP(x) ((x) << 0) |
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303 | # define BSP_MASK (0xffff << 0) |
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304 | # define BSP_SHIFT 0 |
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305 | # define BSU(x) ((x) << 16) |
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306 | # define BSU_MASK (0xf << 16) |
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307 | # define BSU_SHIFT 16 |
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308 | |||
309 | #define CG_CG_VOLTAGE_CNTL 0x770 |
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310 | # define REQ (1 << 0) |
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311 | # define LEVEL(x) ((x) << 1) |
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312 | # define LEVEL_MASK (0x3 << 1) |
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313 | # define LEVEL_SHIFT 1 |
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314 | # define CG_VOLTAGE_EN (1 << 3) |
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315 | # define FORCE (1 << 4) |
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316 | # define PERIOD(x) ((x) << 8) |
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317 | # define PERIOD_MASK (0xffff << 8) |
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318 | # define PERIOD_SHIFT 8 |
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319 | # define UNIT(x) ((x) << 24) |
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320 | # define UNIT_MASK (0xf << 24) |
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321 | # define UNIT_SHIFT 24 |
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322 | |||
323 | #define CG_ACPI_VOLTAGE_CNTL 0x780 |
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324 | # define ACPI_VOLTAGE_EN (1 << 8) |
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325 | |||
326 | #define CG_DPM_VOLTAGE_CNTL 0x788 |
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327 | # define DPM_STATE0_LEVEL_MASK (0x3 << 0) |
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328 | # define DPM_STATE0_LEVEL_SHIFT 0 |
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329 | # define DPM_VOLTAGE_EN (1 << 16) |
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330 | |||
331 | #define CG_PWR_GATING_CNTL 0x7ac |
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332 | # define DYN_PWR_DOWN_EN (1 << 0) |
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333 | # define ACPI_PWR_DOWN_EN (1 << 1) |
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334 | # define GFX_CLK_OFF_PWR_DOWN_EN (1 << 2) |
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335 | # define IOC_DISGPU_PWR_DOWN_EN (1 << 3) |
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336 | # define FORCE_POWR_ON (1 << 4) |
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337 | # define PGP(x) ((x) << 8) |
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338 | # define PGP_MASK (0xffff << 8) |
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339 | # define PGP_SHIFT 8 |
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340 | # define PGU(x) ((x) << 24) |
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341 | # define PGU_MASK (0xf << 24) |
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342 | # define PGU_SHIFT 24 |
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343 | |||
344 | #define CG_CGTT_LOCAL_0 0x7d0 |
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345 | #define CG_CGTT_LOCAL_1 0x7d4 |
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346 | |||
347 | #define DEEP_SLEEP_CNTL 0x818 |
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348 | # define R_DIS (1 << 3) |
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349 | # define HS(x) ((x) << 4) |
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350 | # define HS_MASK (0xfff << 4) |
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351 | # define HS_SHIFT 4 |
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352 | # define ENABLE_DS (1 << 31) |
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353 | #define DEEP_SLEEP_CNTL2 0x81c |
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354 | # define LB_UFP_EN (1 << 0) |
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355 | # define INOUT_C(x) ((x) << 4) |
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356 | # define INOUT_C_MASK (0xff << 4) |
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357 | # define INOUT_C_SHIFT 4 |
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358 | |||
359 | #define CG_SCRATCH2 0x824 |
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360 | |||
361 | #define CG_SCLK_DPM_CTRL_11 0x830 |
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362 | |||
363 | #define HW_REV 0x5564 |
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364 | # define ATI_REV_ID_MASK (0xf << 28) |
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365 | # define ATI_REV_ID_SHIFT 28 |
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366 | /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ |
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367 | |||
368 | #define DOUT_SCRATCH3 0x611c |
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369 | |||
370 | #define GB_ADDR_CONFIG 0x98f8 |
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371 | |||
372 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |