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5078 | serge | 1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #ifndef __SUMO_DPM_H__ |
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24 | #define __SUMO_DPM_H__ |
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25 | |||
26 | #include "atom.h" |
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27 | |||
28 | #define SUMO_MAX_HARDWARE_POWERLEVELS 5 |
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29 | #define SUMO_PM_NUMBER_OF_TC 15 |
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30 | |||
31 | struct sumo_pl { |
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32 | u32 sclk; |
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33 | u32 vddc_index; |
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34 | u32 ds_divider_index; |
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35 | u32 ss_divider_index; |
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36 | u32 allow_gnb_slow; |
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37 | u32 sclk_dpm_tdp_limit; |
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38 | }; |
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39 | |||
40 | /* used for the flags field */ |
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41 | #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0) |
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42 | #define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1) |
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43 | |||
44 | struct sumo_ps { |
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45 | struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; |
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46 | u32 num_levels; |
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47 | /* flags */ |
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48 | u32 flags; |
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49 | }; |
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50 | |||
51 | #define NUMBER_OF_M3ARB_PARAM_SETS 10 |
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52 | #define SUMO_MAX_NUMBER_VOLTAGES 4 |
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53 | |||
54 | struct sumo_disp_clock_voltage_mapping_table { |
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55 | u32 num_max_voltage_levels; |
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56 | u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES]; |
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57 | }; |
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58 | |||
59 | struct sumo_vid_mapping_entry { |
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60 | u16 vid_2bit; |
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61 | u16 vid_7bit; |
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62 | }; |
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63 | |||
64 | struct sumo_vid_mapping_table { |
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65 | u32 num_entries; |
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66 | struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; |
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67 | }; |
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68 | |||
69 | struct sumo_sclk_voltage_mapping_entry { |
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70 | u32 sclk_frequency; |
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71 | u16 vid_2bit; |
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72 | u16 rsv; |
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73 | }; |
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74 | |||
75 | struct sumo_sclk_voltage_mapping_table { |
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76 | u32 num_max_dpm_entries; |
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77 | struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; |
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78 | }; |
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79 | |||
80 | struct sumo_sys_info { |
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81 | u32 bootup_sclk; |
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82 | u32 min_sclk; |
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83 | u32 bootup_uma_clk; |
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84 | u16 bootup_nb_voltage_index; |
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85 | u8 htc_tmp_lmt; |
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86 | u8 htc_hyst_lmt; |
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87 | struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; |
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88 | struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table; |
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89 | struct sumo_vid_mapping_table vid_mapping_table; |
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90 | u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS]; |
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91 | u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS]; |
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92 | u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS]; |
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93 | u32 sclk_dpm_boost_margin; |
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94 | u32 sclk_dpm_throttle_margin; |
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95 | u32 sclk_dpm_tdp_limit_pg; |
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96 | u32 gnb_tdp_limit; |
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97 | u32 sclk_dpm_tdp_limit_boost; |
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98 | u32 boost_sclk; |
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99 | u32 boost_vid_2bit; |
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100 | bool enable_boost; |
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101 | }; |
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102 | |||
103 | struct sumo_power_info { |
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104 | u32 asi; |
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105 | u32 pasi; |
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106 | u32 bsp; |
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107 | u32 bsu; |
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108 | u32 pbsp; |
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109 | u32 pbsu; |
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110 | u32 dsp; |
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111 | u32 psp; |
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112 | u32 thermal_auto_throttling; |
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113 | u32 uvd_m3_arbiter; |
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114 | u32 fw_version; |
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115 | struct sumo_sys_info sys_info; |
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116 | struct sumo_pl acpi_pl; |
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117 | struct sumo_pl boot_pl; |
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118 | struct sumo_pl boost_pl; |
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119 | bool disable_gfx_power_gating_in_uvd; |
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120 | bool driver_nbps_policy_disable; |
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121 | bool enable_alt_vddnb; |
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122 | bool enable_dynamic_m3_arbiter; |
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123 | bool enable_gfx_clock_gating; |
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124 | bool enable_gfx_power_gating; |
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125 | bool enable_mg_clock_gating; |
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126 | bool enable_sclk_ds; |
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127 | bool enable_auto_thermal_throttling; |
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128 | bool enable_dynamic_patch_ps; |
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129 | bool enable_dpm; |
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130 | bool enable_boost; |
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131 | struct radeon_ps current_rps; |
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132 | struct sumo_ps current_ps; |
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133 | struct radeon_ps requested_rps; |
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134 | struct sumo_ps requested_ps; |
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135 | }; |
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136 | |||
137 | #define SUMO_UTC_DFLT_00 0x48 |
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138 | #define SUMO_UTC_DFLT_01 0x44 |
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139 | #define SUMO_UTC_DFLT_02 0x44 |
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140 | #define SUMO_UTC_DFLT_03 0x44 |
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141 | #define SUMO_UTC_DFLT_04 0x44 |
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142 | #define SUMO_UTC_DFLT_05 0x44 |
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143 | #define SUMO_UTC_DFLT_06 0x44 |
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144 | #define SUMO_UTC_DFLT_07 0x44 |
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145 | #define SUMO_UTC_DFLT_08 0x44 |
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146 | #define SUMO_UTC_DFLT_09 0x44 |
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147 | #define SUMO_UTC_DFLT_10 0x44 |
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148 | #define SUMO_UTC_DFLT_11 0x44 |
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149 | #define SUMO_UTC_DFLT_12 0x44 |
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150 | #define SUMO_UTC_DFLT_13 0x44 |
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151 | #define SUMO_UTC_DFLT_14 0x44 |
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152 | |||
153 | #define SUMO_DTC_DFLT_00 0x48 |
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154 | #define SUMO_DTC_DFLT_01 0x44 |
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155 | #define SUMO_DTC_DFLT_02 0x44 |
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156 | #define SUMO_DTC_DFLT_03 0x44 |
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157 | #define SUMO_DTC_DFLT_04 0x44 |
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158 | #define SUMO_DTC_DFLT_05 0x44 |
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159 | #define SUMO_DTC_DFLT_06 0x44 |
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160 | #define SUMO_DTC_DFLT_07 0x44 |
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161 | #define SUMO_DTC_DFLT_08 0x44 |
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162 | #define SUMO_DTC_DFLT_09 0x44 |
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163 | #define SUMO_DTC_DFLT_10 0x44 |
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164 | #define SUMO_DTC_DFLT_11 0x44 |
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165 | #define SUMO_DTC_DFLT_12 0x44 |
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166 | #define SUMO_DTC_DFLT_13 0x44 |
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167 | #define SUMO_DTC_DFLT_14 0x44 |
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168 | |||
169 | #define SUMO_AH_DFLT 5 |
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170 | |||
171 | #define SUMO_R_DFLT0 70 |
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172 | #define SUMO_R_DFLT1 70 |
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173 | #define SUMO_R_DFLT2 70 |
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174 | #define SUMO_R_DFLT3 70 |
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175 | #define SUMO_R_DFLT4 100 |
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176 | |||
177 | #define SUMO_L_DFLT0 0 |
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178 | #define SUMO_L_DFLT1 20 |
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179 | #define SUMO_L_DFLT2 20 |
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180 | #define SUMO_L_DFLT3 20 |
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181 | #define SUMO_L_DFLT4 20 |
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182 | #define SUMO_VRC_DFLT 0x30033 |
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183 | #define SUMO_MGCGTTLOCAL0_DFLT 0 |
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184 | #define SUMO_MGCGTTLOCAL1_DFLT 0 |
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185 | #define SUMO_GICST_DFLT 19 |
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186 | #define SUMO_SST_DFLT 8 |
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187 | #define SUMO_VOLTAGEDROPT_DFLT 1 |
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188 | #define SUMO_GFXPOWERGATINGT_DFLT 100 |
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189 | |||
190 | /* sumo_dpm.c */ |
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191 | void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); |
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192 | void sumo_program_vc(struct radeon_device *rdev, u32 vrc); |
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193 | void sumo_clear_vc(struct radeon_device *rdev); |
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194 | void sumo_program_sstp(struct radeon_device *rdev); |
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195 | void sumo_take_smu_control(struct radeon_device *rdev, bool enable); |
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196 | void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, |
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197 | struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, |
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198 | ATOM_AVAILABLE_SCLK_LIST *table); |
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199 | void sumo_construct_vid_mapping_table(struct radeon_device *rdev, |
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200 | struct sumo_vid_mapping_table *vid_mapping_table, |
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201 | ATOM_AVAILABLE_SCLK_LIST *table); |
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202 | u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, |
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203 | struct sumo_vid_mapping_table *vid_mapping_table, |
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204 | u32 vid_2bit); |
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205 | u32 sumo_get_sleep_divider_from_id(u32 id); |
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206 | u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, |
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207 | u32 sclk, |
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208 | u32 min_sclk_in_sr); |
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209 | |||
210 | /* sumo_smc.c */ |
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211 | void sumo_initialize_m3_arb(struct radeon_device *rdev); |
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212 | void sumo_smu_pg_init(struct radeon_device *rdev); |
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213 | void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit); |
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214 | void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, |
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215 | bool powersaving, bool force_nbps1); |
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216 | void sumo_boost_state_enable(struct radeon_device *rdev, bool enable); |
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217 | void sumo_enable_boost_timer(struct radeon_device *rdev); |
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218 | u32 sumo_get_running_fw_version(struct radeon_device *rdev); |
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219 | |||
220 | #endif><>><> |