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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |||
| 24 | #ifndef SMU7_DISCRETE_H |
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| 25 | #define SMU7_DISCRETE_H |
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| 26 | |||
| 27 | #include "smu7.h" |
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| 28 | |||
| 29 | #pragma pack(push, 1) |
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| 30 | |||
| 31 | #define SMU7_DTE_ITERATIONS 5 |
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| 32 | #define SMU7_DTE_SOURCES 3 |
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| 33 | #define SMU7_DTE_SINKS 1 |
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| 34 | #define SMU7_NUM_CPU_TES 0 |
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| 35 | #define SMU7_NUM_GPU_TES 1 |
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| 36 | #define SMU7_NUM_NON_TES 2 |
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| 37 | |||
| 38 | struct SMU7_SoftRegisters |
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| 39 | { |
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| 40 | uint32_t RefClockFrequency; |
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| 41 | uint32_t PmTimerP; |
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| 42 | uint32_t FeatureEnables; |
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| 43 | uint32_t PreVBlankGap; |
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| 44 | uint32_t VBlankTimeout; |
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| 45 | uint32_t TrainTimeGap; |
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| 46 | |||
| 47 | uint32_t MvddSwitchTime; |
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| 48 | uint32_t LongestAcpiTrainTime; |
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| 49 | uint32_t AcpiDelay; |
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| 50 | uint32_t G5TrainTime; |
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| 51 | uint32_t DelayMpllPwron; |
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| 52 | uint32_t VoltageChangeTimeout; |
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| 53 | uint32_t HandshakeDisables; |
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| 54 | |||
| 55 | uint8_t DisplayPhy1Config; |
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| 56 | uint8_t DisplayPhy2Config; |
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| 57 | uint8_t DisplayPhy3Config; |
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| 58 | uint8_t DisplayPhy4Config; |
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| 59 | |||
| 60 | uint8_t DisplayPhy5Config; |
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| 61 | uint8_t DisplayPhy6Config; |
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| 62 | uint8_t DisplayPhy7Config; |
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| 63 | uint8_t DisplayPhy8Config; |
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| 64 | |||
| 65 | uint32_t AverageGraphicsA; |
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| 66 | uint32_t AverageMemoryA; |
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| 67 | uint32_t AverageGioA; |
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| 68 | |||
| 69 | uint8_t SClkDpmEnabledLevels; |
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| 70 | uint8_t MClkDpmEnabledLevels; |
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| 71 | uint8_t LClkDpmEnabledLevels; |
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| 72 | uint8_t PCIeDpmEnabledLevels; |
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| 73 | |||
| 74 | uint8_t UVDDpmEnabledLevels; |
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| 75 | uint8_t SAMUDpmEnabledLevels; |
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| 76 | uint8_t ACPDpmEnabledLevels; |
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| 77 | uint8_t VCEDpmEnabledLevels; |
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| 78 | |||
| 79 | uint32_t DRAM_LOG_ADDR_H; |
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| 80 | uint32_t DRAM_LOG_ADDR_L; |
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| 81 | uint32_t DRAM_LOG_PHY_ADDR_H; |
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| 82 | uint32_t DRAM_LOG_PHY_ADDR_L; |
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| 83 | uint32_t DRAM_LOG_BUFF_SIZE; |
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| 84 | uint32_t UlvEnterC; |
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| 85 | uint32_t UlvTime; |
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| 86 | uint32_t Reserved[3]; |
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| 87 | |||
| 88 | }; |
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| 89 | |||
| 90 | typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; |
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| 91 | |||
| 92 | struct SMU7_Discrete_VoltageLevel |
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| 93 | { |
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| 94 | uint16_t Voltage; |
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| 95 | uint16_t StdVoltageHiSidd; |
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| 96 | uint16_t StdVoltageLoSidd; |
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| 97 | uint8_t Smio; |
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| 98 | uint8_t padding; |
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| 99 | }; |
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| 100 | |||
| 101 | typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; |
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| 102 | |||
| 103 | struct SMU7_Discrete_GraphicsLevel |
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| 104 | { |
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| 105 | uint32_t Flags; |
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| 106 | uint32_t MinVddc; |
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| 107 | uint32_t MinVddcPhases; |
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| 108 | |||
| 109 | uint32_t SclkFrequency; |
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| 110 | |||
| 111 | uint8_t padding1[2]; |
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| 112 | uint16_t ActivityLevel; |
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| 113 | |||
| 114 | uint32_t CgSpllFuncCntl3; |
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| 115 | uint32_t CgSpllFuncCntl4; |
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| 116 | uint32_t SpllSpreadSpectrum; |
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| 117 | uint32_t SpllSpreadSpectrum2; |
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| 118 | uint32_t CcPwrDynRm; |
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| 119 | uint32_t CcPwrDynRm1; |
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| 120 | uint8_t SclkDid; |
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| 121 | uint8_t DisplayWatermark; |
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| 122 | uint8_t EnabledForActivity; |
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| 123 | uint8_t EnabledForThrottle; |
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| 124 | uint8_t UpH; |
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| 125 | uint8_t DownH; |
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| 126 | uint8_t VoltageDownH; |
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| 127 | uint8_t PowerThrottle; |
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| 128 | uint8_t DeepSleepDivId; |
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| 129 | uint8_t padding[3]; |
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| 130 | }; |
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| 131 | |||
| 132 | typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; |
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| 133 | |||
| 134 | struct SMU7_Discrete_ACPILevel |
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| 135 | { |
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| 136 | uint32_t Flags; |
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| 137 | uint32_t MinVddc; |
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| 138 | uint32_t MinVddcPhases; |
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| 139 | uint32_t SclkFrequency; |
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| 140 | uint8_t SclkDid; |
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| 141 | uint8_t DisplayWatermark; |
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| 142 | uint8_t DeepSleepDivId; |
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| 143 | uint8_t padding; |
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| 144 | uint32_t CgSpllFuncCntl; |
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| 145 | uint32_t CgSpllFuncCntl2; |
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| 146 | uint32_t CgSpllFuncCntl3; |
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| 147 | uint32_t CgSpllFuncCntl4; |
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| 148 | uint32_t SpllSpreadSpectrum; |
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| 149 | uint32_t SpllSpreadSpectrum2; |
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| 150 | uint32_t CcPwrDynRm; |
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| 151 | uint32_t CcPwrDynRm1; |
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| 152 | }; |
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| 153 | |||
| 154 | typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; |
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| 155 | |||
| 156 | struct SMU7_Discrete_Ulv |
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| 157 | { |
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| 158 | uint32_t CcPwrDynRm; |
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| 159 | uint32_t CcPwrDynRm1; |
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| 160 | uint16_t VddcOffset; |
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| 161 | uint8_t VddcOffsetVid; |
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| 162 | uint8_t VddcPhase; |
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| 163 | uint32_t Reserved; |
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| 164 | }; |
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| 165 | |||
| 166 | typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; |
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| 167 | |||
| 168 | struct SMU7_Discrete_MemoryLevel |
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| 169 | { |
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| 170 | uint32_t MinVddc; |
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| 171 | uint32_t MinVddcPhases; |
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| 172 | uint32_t MinVddci; |
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| 173 | uint32_t MinMvdd; |
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| 174 | |||
| 175 | uint32_t MclkFrequency; |
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| 176 | |||
| 177 | uint8_t EdcReadEnable; |
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| 178 | uint8_t EdcWriteEnable; |
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| 179 | uint8_t RttEnable; |
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| 180 | uint8_t StutterEnable; |
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| 181 | |||
| 182 | uint8_t StrobeEnable; |
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| 183 | uint8_t StrobeRatio; |
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| 184 | uint8_t EnabledForThrottle; |
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| 185 | uint8_t EnabledForActivity; |
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| 186 | |||
| 187 | uint8_t UpH; |
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| 188 | uint8_t DownH; |
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| 189 | uint8_t VoltageDownH; |
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| 190 | uint8_t padding; |
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| 191 | |||
| 192 | uint16_t ActivityLevel; |
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| 193 | uint8_t DisplayWatermark; |
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| 194 | uint8_t padding1; |
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| 195 | |||
| 196 | uint32_t MpllFuncCntl; |
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| 197 | uint32_t MpllFuncCntl_1; |
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| 198 | uint32_t MpllFuncCntl_2; |
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| 199 | uint32_t MpllAdFuncCntl; |
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| 200 | uint32_t MpllDqFuncCntl; |
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| 201 | uint32_t MclkPwrmgtCntl; |
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| 202 | uint32_t DllCntl; |
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| 203 | uint32_t MpllSs1; |
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| 204 | uint32_t MpllSs2; |
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| 205 | }; |
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| 206 | |||
| 207 | typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; |
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| 208 | |||
| 209 | struct SMU7_Discrete_LinkLevel |
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| 210 | { |
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| 211 | uint8_t PcieGenSpeed; |
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| 212 | uint8_t PcieLaneCount; |
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| 213 | uint8_t EnabledForActivity; |
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| 214 | uint8_t Padding; |
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| 215 | uint32_t DownT; |
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| 216 | uint32_t UpT; |
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| 217 | uint32_t Reserved; |
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| 218 | }; |
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| 219 | |||
| 220 | typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; |
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| 221 | |||
| 222 | |||
| 223 | struct SMU7_Discrete_MCArbDramTimingTableEntry |
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| 224 | { |
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| 225 | uint32_t McArbDramTiming; |
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| 226 | uint32_t McArbDramTiming2; |
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| 227 | uint8_t McArbBurstTime; |
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| 228 | uint8_t padding[3]; |
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| 229 | }; |
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| 230 | |||
| 231 | typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; |
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| 232 | |||
| 233 | struct SMU7_Discrete_MCArbDramTimingTable |
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| 234 | { |
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| 235 | SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; |
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| 236 | }; |
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| 237 | |||
| 238 | typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; |
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| 239 | |||
| 240 | struct SMU7_Discrete_UvdLevel |
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| 241 | { |
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| 242 | uint32_t VclkFrequency; |
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| 243 | uint32_t DclkFrequency; |
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| 244 | uint16_t MinVddc; |
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| 245 | uint8_t MinVddcPhases; |
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| 246 | uint8_t VclkDivider; |
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| 247 | uint8_t DclkDivider; |
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| 248 | uint8_t padding[3]; |
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| 249 | }; |
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| 250 | |||
| 251 | typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; |
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| 252 | |||
| 253 | struct SMU7_Discrete_ExtClkLevel |
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| 254 | { |
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| 255 | uint32_t Frequency; |
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| 256 | uint16_t MinVoltage; |
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| 257 | uint8_t MinPhases; |
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| 258 | uint8_t Divider; |
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| 259 | }; |
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| 260 | |||
| 261 | typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; |
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| 262 | |||
| 263 | struct SMU7_Discrete_StateInfo |
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| 264 | { |
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| 265 | uint32_t SclkFrequency; |
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| 266 | uint32_t MclkFrequency; |
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| 267 | uint32_t VclkFrequency; |
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| 268 | uint32_t DclkFrequency; |
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| 269 | uint32_t SamclkFrequency; |
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| 270 | uint32_t AclkFrequency; |
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| 271 | uint32_t EclkFrequency; |
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| 272 | uint16_t MvddVoltage; |
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| 273 | uint16_t padding16; |
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| 274 | uint8_t DisplayWatermark; |
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| 275 | uint8_t McArbIndex; |
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| 276 | uint8_t McRegIndex; |
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| 277 | uint8_t SeqIndex; |
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| 278 | uint8_t SclkDid; |
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| 279 | int8_t SclkIndex; |
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| 280 | int8_t MclkIndex; |
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| 281 | uint8_t PCIeGen; |
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| 282 | |||
| 283 | }; |
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| 284 | |||
| 285 | typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; |
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| 286 | |||
| 287 | |||
| 288 | struct SMU7_Discrete_DpmTable |
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| 289 | { |
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| 290 | SMU7_PIDController GraphicsPIDController; |
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| 291 | SMU7_PIDController MemoryPIDController; |
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| 292 | SMU7_PIDController LinkPIDController; |
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| 293 | |||
| 294 | uint32_t SystemFlags; |
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| 295 | |||
| 296 | |||
| 297 | uint32_t SmioMaskVddcVid; |
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| 298 | uint32_t SmioMaskVddcPhase; |
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| 299 | uint32_t SmioMaskVddciVid; |
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| 300 | uint32_t SmioMaskMvddVid; |
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| 301 | |||
| 302 | uint32_t VddcLevelCount; |
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| 303 | uint32_t VddciLevelCount; |
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| 304 | uint32_t MvddLevelCount; |
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| 305 | |||
| 306 | SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; |
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| 307 | // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; |
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| 308 | SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; |
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| 309 | SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; |
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| 310 | |||
| 311 | uint8_t GraphicsDpmLevelCount; |
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| 312 | uint8_t MemoryDpmLevelCount; |
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| 313 | uint8_t LinkLevelCount; |
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| 314 | uint8_t UvdLevelCount; |
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| 315 | uint8_t VceLevelCount; |
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| 316 | uint8_t AcpLevelCount; |
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| 317 | uint8_t SamuLevelCount; |
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| 318 | uint8_t MasterDeepSleepControl; |
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| 319 | uint32_t Reserved[5]; |
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| 320 | // uint32_t SamuDefaultLevel; |
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| 321 | |||
| 322 | SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; |
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| 323 | SMU7_Discrete_MemoryLevel MemoryACPILevel; |
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| 324 | SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; |
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| 325 | SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; |
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| 326 | SMU7_Discrete_ACPILevel ACPILevel; |
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| 327 | SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; |
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| 328 | SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; |
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| 329 | SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; |
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| 330 | SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; |
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| 331 | SMU7_Discrete_Ulv Ulv; |
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| 332 | |||
| 333 | uint32_t SclkStepSize; |
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| 334 | uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; |
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| 335 | |||
| 336 | uint8_t UvdBootLevel; |
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| 337 | uint8_t VceBootLevel; |
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| 338 | uint8_t AcpBootLevel; |
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| 339 | uint8_t SamuBootLevel; |
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| 340 | |||
| 341 | uint8_t UVDInterval; |
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| 342 | uint8_t VCEInterval; |
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| 343 | uint8_t ACPInterval; |
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| 344 | uint8_t SAMUInterval; |
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| 345 | |||
| 346 | uint8_t GraphicsBootLevel; |
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| 347 | uint8_t GraphicsVoltageChangeEnable; |
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| 348 | uint8_t GraphicsThermThrottleEnable; |
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| 349 | uint8_t GraphicsInterval; |
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| 350 | |||
| 351 | uint8_t VoltageInterval; |
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| 352 | uint8_t ThermalInterval; |
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| 353 | uint16_t TemperatureLimitHigh; |
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| 354 | |||
| 355 | uint16_t TemperatureLimitLow; |
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| 356 | uint8_t MemoryBootLevel; |
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| 357 | uint8_t MemoryVoltageChangeEnable; |
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| 358 | |||
| 359 | uint8_t MemoryInterval; |
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| 360 | uint8_t MemoryThermThrottleEnable; |
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| 361 | uint16_t VddcVddciDelta; |
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| 362 | |||
| 363 | uint16_t VoltageResponseTime; |
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| 364 | uint16_t PhaseResponseTime; |
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| 365 | |||
| 366 | uint8_t PCIeBootLinkLevel; |
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| 367 | uint8_t PCIeGenInterval; |
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| 368 | uint8_t DTEInterval; |
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| 369 | uint8_t DTEMode; |
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| 370 | |||
| 371 | uint8_t SVI2Enable; |
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| 372 | uint8_t VRHotGpio; |
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| 373 | uint8_t AcDcGpio; |
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| 374 | uint8_t ThermGpio; |
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| 375 | |||
| 376 | uint16_t PPM_PkgPwrLimit; |
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| 377 | uint16_t PPM_TemperatureLimit; |
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| 378 | |||
| 379 | uint16_t DefaultTdp; |
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| 380 | uint16_t TargetTdp; |
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| 381 | |||
| 382 | uint16_t FpsHighT; |
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| 383 | uint16_t FpsLowT; |
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| 384 | |||
| 385 | uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; |
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| 386 | uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; |
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| 387 | |||
| 388 | uint8_t DTEAmbientTempBase; |
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| 389 | uint8_t DTETjOffset; |
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| 390 | uint8_t GpuTjMax; |
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| 391 | uint8_t GpuTjHyst; |
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| 392 | |||
| 393 | uint16_t BootVddc; |
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| 394 | uint16_t BootVddci; |
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| 395 | |||
| 396 | uint16_t BootMVdd; |
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| 397 | uint16_t padding; |
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| 398 | |||
| 399 | uint32_t BAPM_TEMP_GRADIENT; |
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| 400 | |||
| 401 | uint32_t LowSclkInterruptT; |
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| 402 | }; |
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| 403 | |||
| 404 | typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; |
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| 405 | |||
| 406 | #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 |
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| 407 | #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY |
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| 408 | |||
| 409 | struct SMU7_Discrete_MCRegisterAddress |
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| 410 | { |
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| 411 | uint16_t s0; |
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| 412 | uint16_t s1; |
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| 413 | }; |
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| 414 | |||
| 415 | typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; |
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| 416 | |||
| 417 | struct SMU7_Discrete_MCRegisterSet |
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| 418 | { |
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| 419 | uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
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| 420 | }; |
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| 421 | |||
| 422 | typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; |
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| 423 | |||
| 424 | struct SMU7_Discrete_MCRegisters |
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| 425 | { |
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| 426 | uint8_t last; |
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| 427 | uint8_t reserved[3]; |
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| 428 | SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
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| 429 | SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; |
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| 430 | }; |
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| 431 | |||
| 432 | typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; |
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| 433 | |||
| 5271 | serge | 434 | struct SMU7_Discrete_FanTable |
| 435 | { |
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| 436 | uint16_t FdoMode; |
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| 437 | int16_t TempMin; |
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| 438 | int16_t TempMed; |
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| 439 | int16_t TempMax; |
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| 440 | int16_t Slope1; |
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| 441 | int16_t Slope2; |
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| 442 | int16_t FdoMin; |
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| 443 | int16_t HystUp; |
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| 444 | int16_t HystDown; |
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| 445 | int16_t HystSlope; |
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| 446 | int16_t TempRespLim; |
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| 447 | int16_t TempCurr; |
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| 448 | int16_t SlopeCurr; |
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| 449 | int16_t PwmCurr; |
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| 450 | uint32_t RefreshPeriod; |
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| 451 | int16_t FdoMax; |
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| 452 | uint8_t TempSrc; |
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| 453 | int8_t Padding; |
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| 454 | }; |
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| 455 | |||
| 456 | typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; |
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| 457 | |||
| 458 | |||
| 5078 | serge | 459 | struct SMU7_Discrete_PmFuses { |
| 460 | // dw0-dw1 |
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| 461 | uint8_t BapmVddCVidHiSidd[8]; |
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| 462 | |||
| 463 | // dw2-dw3 |
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| 464 | uint8_t BapmVddCVidLoSidd[8]; |
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| 465 | |||
| 466 | // dw4-dw5 |
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| 467 | uint8_t VddCVid[8]; |
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| 468 | |||
| 469 | // dw6 |
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| 470 | uint8_t SviLoadLineEn; |
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| 471 | uint8_t SviLoadLineVddC; |
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| 472 | uint8_t SviLoadLineTrimVddC; |
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| 473 | uint8_t SviLoadLineOffsetVddC; |
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| 474 | |||
| 475 | // dw7 |
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| 476 | uint16_t TDC_VDDC_PkgLimit; |
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| 477 | uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; |
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| 478 | uint8_t TDC_MAWt; |
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| 479 | |||
| 480 | // dw8 |
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| 481 | uint8_t TdcWaterfallCtl; |
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| 482 | uint8_t LPMLTemperatureMin; |
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| 483 | uint8_t LPMLTemperatureMax; |
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| 484 | uint8_t Reserved; |
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| 485 | |||
| 486 | // dw9-dw10 |
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| 487 | uint8_t BapmVddCVidHiSidd2[8]; |
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| 488 | |||
| 489 | // dw11-dw12 |
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| 5271 | serge | 490 | int16_t FuzzyFan_ErrorSetDelta; |
| 491 | int16_t FuzzyFan_ErrorRateSetDelta; |
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| 492 | int16_t FuzzyFan_PwmSetDelta; |
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| 493 | uint16_t CalcMeasPowerBlend; |
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| 5078 | serge | 494 | |
| 495 | // dw13-dw16 |
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| 496 | uint8_t GnbLPML[16]; |
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| 497 | |||
| 498 | // dw17 |
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| 499 | uint8_t GnbLPMLMaxVid; |
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| 500 | uint8_t GnbLPMLMinVid; |
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| 501 | uint8_t Reserved1[2]; |
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| 502 | |||
| 503 | // dw18 |
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| 504 | uint16_t BapmVddCBaseLeakageHiSidd; |
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| 505 | uint16_t BapmVddCBaseLeakageLoSidd; |
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| 506 | }; |
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| 507 | |||
| 508 | typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; |
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| 509 | |||
| 510 | |||
| 511 | #pragma pack(pop) |
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| 512 | |||
| 513 | #endif |
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| 514 |