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2997 Serge 1
/*
2
 * Copyright 2011 Advanced Micro Devices, Inc.
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice shall be included in
12
 * all copies or substantial portions of the Software.
13
 *
14
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
 * OTHER DEALINGS IN THE SOFTWARE.
21
 *
22
 * Authors: Alex Deucher
23
 */
24
#ifndef SI_H
25
#define SI_H
26
 
27
#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
28
 
29
#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
30
#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
3764 Serge 31
#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001
2997 Serge 32
 
5078 serge 33
#define SI_MAX_SH_GPRS           256
34
#define SI_MAX_TEMP_GPRS         16
35
#define SI_MAX_SH_THREADS        256
36
#define SI_MAX_SH_STACK_ENTRIES  4096
37
#define SI_MAX_FRC_EOV_CNT       16384
38
#define SI_MAX_BACKENDS          8
39
#define SI_MAX_BACKENDS_MASK     0xFF
40
#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
41
#define SI_MAX_SIMDS             12
42
#define SI_MAX_SIMDS_MASK        0x0FFF
43
#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
44
#define SI_MAX_PIPES             8
45
#define SI_MAX_PIPES_MASK        0xFF
46
#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
47
#define SI_MAX_LDS_NUM           0xFFFF
48
#define SI_MAX_TCC               16
49
#define SI_MAX_TCC_MASK          0xFFFF
50
 
51
/* SMC IND accessor regs */
52
#define SMC_IND_INDEX_0                              0x200
53
#define SMC_IND_DATA_0                               0x204
54
 
55
#define SMC_IND_ACCESS_CNTL                          0x228
56
#       define AUTO_INCREMENT_IND_0                  (1 << 0)
57
#define SMC_MESSAGE_0                                0x22c
58
#define SMC_RESP_0                                   0x230
59
 
60
/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
61
#define SMC_CG_IND_START                    0xc0030000
62
#define SMC_CG_IND_END                      0xc0040000
63
 
64
#define	CG_CGTT_LOCAL_0				0x400
65
#define	CG_CGTT_LOCAL_1				0x401
66
 
67
/* SMC IND registers */
68
#define	SMC_SYSCON_RESET_CNTL				0x80000000
69
#       define RST_REG                                  (1 << 0)
70
#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
71
#       define CK_DISABLE                               (1 << 0)
72
#       define CKEN                                     (1 << 24)
73
 
74
#define VGA_HDP_CONTROL  				0x328
75
#define		VGA_MEMORY_DISABLE				(1 << 4)
76
 
77
#define DCCG_DISP_SLOW_SELECT_REG                       0x4fc
78
#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)
79
#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)
80
#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0
81
#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)
82
#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)
83
#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4
84
 
85
#define	CG_SPLL_FUNC_CNTL				0x600
86
#define		SPLL_RESET				(1 << 0)
87
#define		SPLL_SLEEP				(1 << 1)
88
#define		SPLL_BYPASS_EN				(1 << 3)
89
#define		SPLL_REF_DIV(x)				((x) << 4)
90
#define		SPLL_REF_DIV_MASK			(0x3f << 4)
91
#define		SPLL_PDIV_A(x)				((x) << 20)
92
#define		SPLL_PDIV_A_MASK			(0x7f << 20)
93
#define		SPLL_PDIV_A_SHIFT			20
94
#define	CG_SPLL_FUNC_CNTL_2				0x604
95
#define		SCLK_MUX_SEL(x)				((x) << 0)
96
#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
97
#define		SPLL_CTLREQ_CHG				(1 << 23)
98
#define		SCLK_MUX_UPDATE				(1 << 26)
99
#define	CG_SPLL_FUNC_CNTL_3				0x608
100
#define		SPLL_FB_DIV(x)				((x) << 0)
101
#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
102
#define		SPLL_FB_DIV_SHIFT			0
103
#define		SPLL_DITHEN				(1 << 28)
104
#define	CG_SPLL_FUNC_CNTL_4				0x60c
105
 
106
#define	SPLL_STATUS					0x614
107
#define		SPLL_CHG_STATUS				(1 << 1)
108
#define	SPLL_CNTL_MODE					0x618
109
#define		SPLL_SW_DIR_CONTROL			(1 << 0)
110
#	define SPLL_REFCLK_SEL(x)			((x) << 26)
111
#	define SPLL_REFCLK_SEL_MASK			(3 << 26)
112
 
113
#define	CG_SPLL_SPREAD_SPECTRUM				0x620
114
#define		SSEN					(1 << 0)
115
#define		CLK_S(x)				((x) << 4)
116
#define		CLK_S_MASK				(0xfff << 4)
117
#define		CLK_S_SHIFT				4
118
#define	CG_SPLL_SPREAD_SPECTRUM_2			0x624
119
#define		CLK_V(x)				((x) << 0)
120
#define		CLK_V_MASK				(0x3ffffff << 0)
121
#define		CLK_V_SHIFT				0
122
 
123
#define	CG_SPLL_AUTOSCALE_CNTL				0x62c
124
#       define AUTOSCALE_ON_SS_CLEAR                    (1 << 9)
125
 
3764 Serge 126
/* discrete uvd clocks */
127
#define	CG_UPLL_FUNC_CNTL				0x634
128
#	define UPLL_RESET_MASK				0x00000001
129
#	define UPLL_SLEEP_MASK				0x00000002
130
#	define UPLL_BYPASS_EN_MASK			0x00000004
131
#	define UPLL_CTLREQ_MASK				0x00000008
132
#	define UPLL_VCO_MODE_MASK			0x00000600
133
#	define UPLL_REF_DIV_MASK			0x003F0000
134
#	define UPLL_CTLACK_MASK				0x40000000
135
#	define UPLL_CTLACK2_MASK			0x80000000
136
#define	CG_UPLL_FUNC_CNTL_2				0x638
137
#	define UPLL_PDIV_A(x)				((x) << 0)
138
#	define UPLL_PDIV_A_MASK				0x0000007F
139
#	define UPLL_PDIV_B(x)				((x) << 8)
140
#	define UPLL_PDIV_B_MASK				0x00007F00
141
#	define VCLK_SRC_SEL(x)				((x) << 20)
142
#	define VCLK_SRC_SEL_MASK			0x01F00000
143
#	define DCLK_SRC_SEL(x)				((x) << 25)
144
#	define DCLK_SRC_SEL_MASK			0x3E000000
145
#define	CG_UPLL_FUNC_CNTL_3				0x63C
146
#	define UPLL_FB_DIV(x)				((x) << 0)
147
#	define UPLL_FB_DIV_MASK				0x01FFFFFF
148
#define	CG_UPLL_FUNC_CNTL_4                             0x644
149
#	define UPLL_SPARE_ISPARE9			0x00020000
150
#define	CG_UPLL_FUNC_CNTL_5				0x648
151
#	define RESET_ANTI_MUX_MASK			0x00000200
152
#define	CG_UPLL_SPREAD_SPECTRUM				0x650
153
#	define SSEN_MASK				0x00000001
154
 
5078 serge 155
#define	MPLL_BYPASSCLK_SEL				0x65c
156
#	define MPLL_CLKOUT_SEL(x)			((x) << 8)
157
#	define MPLL_CLKOUT_SEL_MASK			0xFF00
158
 
159
#define CG_CLKPIN_CNTL                                    0x660
160
#       define XTALIN_DIVIDE                              (1 << 1)
161
#       define BCLK_AS_XCLK                               (1 << 2)
162
#define CG_CLKPIN_CNTL_2                                  0x664
163
#       define FORCE_BIF_REFCLK_EN                        (1 << 3)
164
#       define MUX_TCLK_TO_XCLK                           (1 << 8)
165
 
166
#define	THM_CLK_CNTL					0x66c
167
#	define CMON_CLK_SEL(x)				((x) << 0)
168
#	define CMON_CLK_SEL_MASK			0xFF
169
#	define TMON_CLK_SEL(x)				((x) << 8)
170
#	define TMON_CLK_SEL_MASK			0xFF00
171
#define	MISC_CLK_CNTL					0x670
172
#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)
173
#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF
174
#	define ZCLK_SEL(x)				((x) << 8)
175
#	define ZCLK_SEL_MASK				0xFF00
176
 
177
#define	CG_THERMAL_CTRL					0x700
178
#define 	DPM_EVENT_SRC(x)			((x) << 0)
179
#define 	DPM_EVENT_SRC_MASK			(7 << 0)
180
#define		DIG_THERM_DPM(x)			((x) << 14)
181
#define		DIG_THERM_DPM_MASK			0x003FC000
182
#define		DIG_THERM_DPM_SHIFT			14
183
 
184
#define	CG_THERMAL_INT					0x708
185
#define		DIG_THERM_INTH(x)			((x) << 8)
186
#define		DIG_THERM_INTH_MASK			0x0000FF00
187
#define		DIG_THERM_INTH_SHIFT			8
188
#define		DIG_THERM_INTL(x)			((x) << 16)
189
#define		DIG_THERM_INTL_MASK			0x00FF0000
190
#define		DIG_THERM_INTL_SHIFT			16
191
#define 	THERM_INT_MASK_HIGH			(1 << 24)
192
#define 	THERM_INT_MASK_LOW			(1 << 25)
193
 
2997 Serge 194
#define	CG_MULT_THERMAL_STATUS					0x714
195
#define		ASIC_MAX_TEMP(x)				((x) << 0)
196
#define		ASIC_MAX_TEMP_MASK				0x000001ff
197
#define		ASIC_MAX_TEMP_SHIFT				0
198
#define		CTF_TEMP(x)					((x) << 9)
199
#define		CTF_TEMP_MASK					0x0003fe00
200
#define		CTF_TEMP_SHIFT					9
201
 
5078 serge 202
#define GENERAL_PWRMGT                                  0x780
203
#       define GLOBAL_PWRMGT_EN                         (1 << 0)
204
#       define STATIC_PM_EN                             (1 << 1)
205
#       define THERMAL_PROTECTION_DIS                   (1 << 2)
206
#       define THERMAL_PROTECTION_TYPE                  (1 << 3)
207
#       define SW_SMIO_INDEX(x)                         ((x) << 6)
208
#       define SW_SMIO_INDEX_MASK                       (1 << 6)
209
#       define SW_SMIO_INDEX_SHIFT                      6
210
#       define VOLT_PWRMGT_EN                           (1 << 10)
211
#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
212
#define CG_TPC                                            0x784
213
#define SCLK_PWRMGT_CNTL                                  0x788
214
#       define SCLK_PWRMGT_OFF                            (1 << 0)
215
#       define SCLK_LOW_D1                                (1 << 1)
216
#       define FIR_RESET                                  (1 << 4)
217
#       define FIR_FORCE_TREND_SEL                        (1 << 5)
218
#       define FIR_TREND_MODE                             (1 << 6)
219
#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
220
#       define GFX_CLK_FORCE_ON                           (1 << 8)
221
#       define GFX_CLK_REQUEST_OFF                        (1 << 9)
222
#       define GFX_CLK_FORCE_OFF                          (1 << 10)
223
#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
224
#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
225
#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
226
#       define DYN_LIGHT_SLEEP_EN                         (1 << 14)
2997 Serge 227
 
5078 serge 228
#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x798
229
#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
230
#       define CURRENT_STATE_INDEX_SHIFT                  4
2997 Serge 231
 
5078 serge 232
#define CG_FTV                                            0x7bc
3764 Serge 233
 
5078 serge 234
#define CG_FFCT_0                                         0x7c0
235
#       define UTC_0(x)                                   ((x) << 0)
236
#       define UTC_0_MASK                                 (0x3ff << 0)
237
#       define DTC_0(x)                                   ((x) << 10)
238
#       define DTC_0_MASK                                 (0x3ff << 10)
239
 
240
#define CG_BSP                                          0x7fc
241
#       define BSP(x)					((x) << 0)
242
#       define BSP_MASK					(0xffff << 0)
243
#       define BSU(x)					((x) << 16)
244
#       define BSU_MASK					(0xf << 16)
245
#define CG_AT                                           0x800
246
#       define CG_R(x)					((x) << 0)
247
#       define CG_R_MASK				(0xffff << 0)
248
#       define CG_L(x)					((x) << 16)
249
#       define CG_L_MASK				(0xffff << 16)
250
 
251
#define CG_GIT                                          0x804
252
#       define CG_GICST(x)                              ((x) << 0)
253
#       define CG_GICST_MASK                            (0xffff << 0)
254
#       define CG_GIPOT(x)                              ((x) << 16)
255
#       define CG_GIPOT_MASK                            (0xffff << 16)
256
 
257
#define CG_SSP                                            0x80c
258
#       define SST(x)                                     ((x) << 0)
259
#       define SST_MASK                                   (0xffff << 0)
260
#       define SSTU(x)                                    ((x) << 16)
261
#       define SSTU_MASK                                  (0xf << 16)
262
 
263
#define CG_DISPLAY_GAP_CNTL                               0x828
264
#       define DISP1_GAP(x)                               ((x) << 0)
265
#       define DISP1_GAP_MASK                             (3 << 0)
266
#       define DISP2_GAP(x)                               ((x) << 2)
267
#       define DISP2_GAP_MASK                             (3 << 2)
268
#       define VBI_TIMER_COUNT(x)                         ((x) << 4)
269
#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
270
#       define VBI_TIMER_UNIT(x)                          ((x) << 20)
271
#       define VBI_TIMER_UNIT_MASK                        (7 << 20)
272
#       define DISP1_GAP_MCHG(x)                          ((x) << 24)
273
#       define DISP1_GAP_MCHG_MASK                        (3 << 24)
274
#       define DISP2_GAP_MCHG(x)                          ((x) << 26)
275
#       define DISP2_GAP_MCHG_MASK                        (3 << 26)
276
 
277
#define	CG_ULV_CONTROL					0x878
278
#define	CG_ULV_PARAMETER				0x87c
279
 
280
#define	SMC_SCRATCH0					0x884
281
 
282
#define	CG_CAC_CTRL					0x8b8
283
#	define CAC_WINDOW(x)				((x) << 0)
284
#	define CAC_WINDOW_MASK				0x00ffffff
285
 
2997 Serge 286
#define DMIF_ADDR_CONFIG  				0xBD4
287
 
3764 Serge 288
#define DMIF_ADDR_CALC  				0xC00
289
 
5078 serge 290
#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0
291
#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
292
#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
293
 
2997 Serge 294
#define	SRBM_STATUS				        0xE50
3764 Serge 295
#define		GRBM_RQ_PENDING 			(1 << 5)
296
#define		VMC_BUSY 				(1 << 8)
297
#define		MCB_BUSY 				(1 << 9)
298
#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
299
#define		MCC_BUSY 				(1 << 11)
300
#define		MCD_BUSY 				(1 << 12)
301
#define		SEM_BUSY 				(1 << 14)
302
#define		IH_BUSY 				(1 << 17)
2997 Serge 303
 
3192 Serge 304
#define	SRBM_SOFT_RESET				        0x0E60
305
#define		SOFT_RESET_BIF				(1 << 1)
306
#define		SOFT_RESET_DC				(1 << 5)
307
#define		SOFT_RESET_DMA1				(1 << 6)
308
#define		SOFT_RESET_GRBM				(1 << 8)
309
#define		SOFT_RESET_HDP				(1 << 9)
310
#define		SOFT_RESET_IH				(1 << 10)
311
#define		SOFT_RESET_MC				(1 << 11)
312
#define		SOFT_RESET_ROM				(1 << 14)
313
#define		SOFT_RESET_SEM				(1 << 15)
314
#define		SOFT_RESET_VMC				(1 << 17)
315
#define		SOFT_RESET_DMA				(1 << 20)
316
#define		SOFT_RESET_TST				(1 << 21)
317
#define		SOFT_RESET_REGBB			(1 << 22)
318
#define		SOFT_RESET_ORB				(1 << 23)
319
 
2997 Serge 320
#define	CC_SYS_RB_BACKEND_DISABLE			0xe80
321
#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84
322
 
3764 Serge 323
#define	SRBM_STATUS2				        0x0EC4
324
#define		DMA_BUSY 				(1 << 5)
325
#define		DMA1_BUSY 				(1 << 6)
326
 
2997 Serge 327
#define VM_L2_CNTL					0x1400
328
#define		ENABLE_L2_CACHE					(1 << 0)
329
#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
330
#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)
331
#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)
332
#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
333
#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
334
#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)
335
#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)
336
#define VM_L2_CNTL2					0x1404
337
#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
338
#define		INVALIDATE_L2_CACHE				(1 << 1)
339
#define		INVALIDATE_CACHE_MODE(x)			((x) << 26)
340
#define			INVALIDATE_PTE_AND_PDE_CACHES		0
341
#define			INVALIDATE_ONLY_PTE_CACHES		1
342
#define			INVALIDATE_ONLY_PDE_CACHES		2
343
#define VM_L2_CNTL3					0x1408
344
#define		BANK_SELECT(x)					((x) << 0)
345
#define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)
346
#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
347
#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
348
#define	VM_L2_STATUS					0x140C
349
#define		L2_BUSY						(1 << 0)
350
#define VM_CONTEXT0_CNTL				0x1410
351
#define		ENABLE_CONTEXT					(1 << 0)
352
#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
3192 Serge 353
#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
2997 Serge 354
#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
3192 Serge 355
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
356
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
357
#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
358
#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
359
#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
360
#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
361
#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
362
#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
363
#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
364
#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
5078 serge 365
#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)
2997 Serge 366
#define VM_CONTEXT1_CNTL				0x1414
367
#define VM_CONTEXT0_CNTL2				0x1430
368
#define VM_CONTEXT1_CNTL2				0x1434
369
#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x1438
370
#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x143c
371
#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x1440
372
#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x1444
373
#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x1448
374
#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x144c
375
#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x1450
376
#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x1454
377
 
3192 Serge 378
#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC
379
#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
5078 serge 380
#define		PROTECTIONS_MASK			(0xf << 0)
381
#define		PROTECTIONS_SHIFT			0
382
		/* bit 0: range
383
		 * bit 1: pde0
384
		 * bit 2: valid
385
		 * bit 3: read
386
		 * bit 4: write
387
		 */
388
#define		MEMORY_CLIENT_ID_MASK			(0xff << 12)
389
#define		MEMORY_CLIENT_ID_SHIFT			12
390
#define		MEMORY_CLIENT_RW_MASK			(1 << 24)
391
#define		MEMORY_CLIENT_RW_SHIFT			24
392
#define		FAULT_VMID_MASK				(0xf << 25)
393
#define		FAULT_VMID_SHIFT			25
3192 Serge 394
 
2997 Serge 395
#define VM_INVALIDATE_REQUEST				0x1478
396
#define VM_INVALIDATE_RESPONSE				0x147c
397
 
398
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
399
#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c
400
 
401
#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153c
402
#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x1540
403
#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x1544
404
#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x1548
405
#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x154c
406
#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x1550
407
#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x1554
408
#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x1558
409
#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155c
410
#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x1560
411
 
412
#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
413
#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x1580
414
 
5078 serge 415
#define VM_L2_CG           				0x15c0
416
#define		MC_CG_ENABLE				(1 << 18)
417
#define		MC_LS_ENABLE				(1 << 19)
418
 
2997 Serge 419
#define MC_SHARED_CHMAP						0x2004
420
#define		NOOFCHAN_SHIFT					12
421
#define		NOOFCHAN_MASK					0x0000f000
422
#define MC_SHARED_CHREMAP					0x2008
423
 
424
#define	MC_VM_FB_LOCATION				0x2024
425
#define	MC_VM_AGP_TOP					0x2028
426
#define	MC_VM_AGP_BOT					0x202C
427
#define	MC_VM_AGP_BASE					0x2030
428
#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
429
#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
430
#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
431
 
432
#define	MC_VM_MX_L1_TLB_CNTL				0x2064
433
#define		ENABLE_L1_TLB					(1 << 0)
434
#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
435
#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
436
#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
437
#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
438
#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
439
#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
440
#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
441
 
442
#define MC_SHARED_BLACKOUT_CNTL           		0x20ac
443
 
5078 serge 444
#define MC_HUB_MISC_HUB_CG           			0x20b8
445
#define MC_HUB_MISC_VM_CG           			0x20bc
446
 
447
#define MC_HUB_MISC_SIP_CG           			0x20c0
448
 
449
#define MC_XPB_CLK_GAT           			0x2478
450
 
451
#define MC_CITF_MISC_RD_CG           			0x2648
452
#define MC_CITF_MISC_WR_CG           			0x264c
453
#define MC_CITF_MISC_VM_CG           			0x2650
454
 
2997 Serge 455
#define	MC_ARB_RAMCFG					0x2760
456
#define		NOOFBANK_SHIFT					0
457
#define		NOOFBANK_MASK					0x00000003
458
#define		NOOFRANK_SHIFT					2
459
#define		NOOFRANK_MASK					0x00000004
460
#define		NOOFROWS_SHIFT					3
461
#define		NOOFROWS_MASK					0x00000038
462
#define		NOOFCOLS_SHIFT					6
463
#define		NOOFCOLS_MASK					0x000000C0
464
#define		CHANSIZE_SHIFT					8
465
#define		CHANSIZE_MASK					0x00000100
466
#define		CHANSIZE_OVERRIDE				(1 << 11)
467
#define		NOOFGROUPS_SHIFT				12
468
#define		NOOFGROUPS_MASK					0x00001000
469
 
5078 serge 470
#define	MC_ARB_DRAM_TIMING				0x2774
471
#define	MC_ARB_DRAM_TIMING2				0x2778
472
 
473
#define MC_ARB_BURST_TIME                               0x2808
474
#define		STATE0(x)				((x) << 0)
475
#define		STATE0_MASK				(0x1f << 0)
476
#define		STATE0_SHIFT				0
477
#define		STATE1(x)				((x) << 5)
478
#define		STATE1_MASK				(0x1f << 5)
479
#define		STATE1_SHIFT				5
480
#define		STATE2(x)				((x) << 10)
481
#define		STATE2_MASK				(0x1f << 10)
482
#define		STATE2_SHIFT				10
483
#define		STATE3(x)				((x) << 15)
484
#define		STATE3_MASK				(0x1f << 15)
485
#define		STATE3_SHIFT				15
486
 
487
#define	MC_SEQ_TRAIN_WAKEUP_CNTL			0x28e8
2997 Serge 488
#define		TRAIN_DONE_D0      			(1 << 30)
489
#define		TRAIN_DONE_D1      			(1 << 31)
490
 
491
#define MC_SEQ_SUP_CNTL           			0x28c8
492
#define		RUN_MASK      				(1 << 0)
493
#define MC_SEQ_SUP_PGM           			0x28cc
5078 serge 494
#define MC_PMG_AUTO_CMD           			0x28d0
2997 Serge 495
 
496
#define MC_IO_PAD_CNTL_D0           			0x29d0
497
#define		MEM_FALL_OUT_CMD      			(1 << 8)
498
 
5078 serge 499
#define MC_SEQ_RAS_TIMING                               0x28a0
500
#define MC_SEQ_CAS_TIMING                               0x28a4
501
#define MC_SEQ_MISC_TIMING                              0x28a8
502
#define MC_SEQ_MISC_TIMING2                             0x28ac
503
#define MC_SEQ_PMG_TIMING                               0x28b0
504
#define MC_SEQ_RD_CTL_D0                                0x28b4
505
#define MC_SEQ_RD_CTL_D1                                0x28b8
506
#define MC_SEQ_WR_CTL_D0                                0x28bc
507
#define MC_SEQ_WR_CTL_D1                                0x28c0
508
 
509
#define MC_SEQ_MISC0           				0x2a00
510
#define 	MC_SEQ_MISC0_VEN_ID_SHIFT               8
511
#define 	MC_SEQ_MISC0_VEN_ID_MASK                0x00000f00
512
#define 	MC_SEQ_MISC0_VEN_ID_VALUE               3
513
#define 	MC_SEQ_MISC0_REV_ID_SHIFT               12
514
#define 	MC_SEQ_MISC0_REV_ID_MASK                0x0000f000
515
#define 	MC_SEQ_MISC0_REV_ID_VALUE               1
516
#define 	MC_SEQ_MISC0_GDDR5_SHIFT                28
517
#define 	MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
518
#define 	MC_SEQ_MISC0_GDDR5_VALUE                5
519
#define MC_SEQ_MISC1                                    0x2a04
520
#define MC_SEQ_RESERVE_M                                0x2a08
521
#define MC_PMG_CMD_EMRS                                 0x2a0c
522
 
2997 Serge 523
#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44
524
#define MC_SEQ_IO_DEBUG_DATA           			0x2a48
525
 
5078 serge 526
#define MC_SEQ_MISC5                                    0x2a54
527
#define MC_SEQ_MISC6                                    0x2a58
528
 
529
#define MC_SEQ_MISC7                                    0x2a64
530
 
531
#define MC_SEQ_RAS_TIMING_LP                            0x2a6c
532
#define MC_SEQ_CAS_TIMING_LP                            0x2a70
533
#define MC_SEQ_MISC_TIMING_LP                           0x2a74
534
#define MC_SEQ_MISC_TIMING2_LP                          0x2a78
535
#define MC_SEQ_WR_CTL_D0_LP                             0x2a7c
536
#define MC_SEQ_WR_CTL_D1_LP                             0x2a80
537
#define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84
538
#define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88
539
 
540
#define MC_PMG_CMD_MRS                                  0x2aac
541
 
542
#define MC_SEQ_RD_CTL_D0_LP                             0x2b1c
543
#define MC_SEQ_RD_CTL_D1_LP                             0x2b20
544
 
545
#define MC_PMG_CMD_MRS1                                 0x2b44
546
#define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48
547
#define MC_SEQ_PMG_TIMING_LP                            0x2b4c
548
 
549
#define MC_SEQ_WR_CTL_2                                 0x2b54
550
#define MC_SEQ_WR_CTL_2_LP                              0x2b58
551
#define MC_PMG_CMD_MRS2                                 0x2b5c
552
#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
553
 
554
#define	MCLK_PWRMGT_CNTL				0x2ba0
555
#       define DLL_SPEED(x)				((x) << 0)
556
#       define DLL_SPEED_MASK				(0x1f << 0)
557
#       define DLL_READY                                (1 << 6)
558
#       define MC_INT_CNTL                              (1 << 7)
559
#       define MRDCK0_PDNB                              (1 << 8)
560
#       define MRDCK1_PDNB                              (1 << 9)
561
#       define MRDCK0_RESET                             (1 << 16)
562
#       define MRDCK1_RESET                             (1 << 17)
563
#       define DLL_READY_READ                           (1 << 24)
564
#define	DLL_CNTL					0x2ba4
565
#       define MRDCK0_BYPASS                            (1 << 24)
566
#       define MRDCK1_BYPASS                            (1 << 25)
567
 
568
#define	MPLL_CNTL_MODE					0x2bb0
569
#       define MPLL_MCLK_SEL                            (1 << 11)
570
#define	MPLL_FUNC_CNTL					0x2bb4
571
#define		BWCTRL(x)				((x) << 20)
572
#define		BWCTRL_MASK				(0xff << 20)
573
#define	MPLL_FUNC_CNTL_1				0x2bb8
574
#define		VCO_MODE(x)				((x) << 0)
575
#define		VCO_MODE_MASK				(3 << 0)
576
#define		CLKFRAC(x)				((x) << 4)
577
#define		CLKFRAC_MASK				(0xfff << 4)
578
#define		CLKF(x)					((x) << 16)
579
#define		CLKF_MASK				(0xfff << 16)
580
#define	MPLL_FUNC_CNTL_2				0x2bbc
581
#define	MPLL_AD_FUNC_CNTL				0x2bc0
582
#define		YCLK_POST_DIV(x)			((x) << 0)
583
#define		YCLK_POST_DIV_MASK			(7 << 0)
584
#define	MPLL_DQ_FUNC_CNTL				0x2bc4
585
#define		YCLK_SEL(x)				((x) << 4)
586
#define		YCLK_SEL_MASK				(1 << 4)
587
 
588
#define	MPLL_SS1					0x2bcc
589
#define		CLKV(x)					((x) << 0)
590
#define		CLKV_MASK				(0x3ffffff << 0)
591
#define	MPLL_SS2					0x2bd0
592
#define		CLKS(x)					((x) << 0)
593
#define		CLKS_MASK				(0xfff << 0)
594
 
2997 Serge 595
#define	HDP_HOST_PATH_CNTL				0x2C00
5078 serge 596
#define 	CLOCK_GATING_DIS			(1 << 23)
2997 Serge 597
#define	HDP_NONSURFACE_BASE				0x2C04
598
#define	HDP_NONSURFACE_INFO				0x2C08
599
#define	HDP_NONSURFACE_SIZE				0x2C0C
600
 
601
#define HDP_ADDR_CONFIG  				0x2F48
602
#define HDP_MISC_CNTL					0x2F4C
603
#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
5078 serge 604
#define HDP_MEM_POWER_LS				0x2F50
605
#define 	HDP_LS_ENABLE				(1 << 0)
2997 Serge 606
 
5078 serge 607
#define ATC_MISC_CG           				0x3350
608
 
2997 Serge 609
#define IH_RB_CNTL                                        0x3e00
610
#       define IH_RB_ENABLE                               (1 << 0)
611
#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
612
#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
613
#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
614
#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
615
#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
616
#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
617
#define IH_RB_BASE                                        0x3e04
618
#define IH_RB_RPTR                                        0x3e08
619
#define IH_RB_WPTR                                        0x3e0c
620
#       define RB_OVERFLOW                                (1 << 0)
621
#       define WPTR_OFFSET_MASK                           0x3fffc
622
#define IH_RB_WPTR_ADDR_HI                                0x3e10
623
#define IH_RB_WPTR_ADDR_LO                                0x3e14
624
#define IH_CNTL                                           0x3e18
625
#       define ENABLE_INTR                                (1 << 0)
626
#       define IH_MC_SWAP(x)                              ((x) << 1)
627
#       define IH_MC_SWAP_NONE                            0
628
#       define IH_MC_SWAP_16BIT                           1
629
#       define IH_MC_SWAP_32BIT                           2
630
#       define IH_MC_SWAP_64BIT                           3
631
#       define RPTR_REARM                                 (1 << 4)
632
#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
633
#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
634
#       define MC_VMID(x)                                 ((x) << 25)
635
 
636
#define	CONFIG_MEMSIZE					0x5428
637
 
638
#define INTERRUPT_CNTL                                    0x5468
639
#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
640
#       define IH_DUMMY_RD_EN                             (1 << 1)
641
#       define IH_REQ_NONSNOOP_EN                         (1 << 3)
642
#       define GEN_IH_INT_EN                              (1 << 8)
643
#define INTERRUPT_CNTL2                                   0x546c
644
 
645
#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
646
 
647
#define	BIF_FB_EN						0x5490
648
#define		FB_READ_EN					(1 << 0)
649
#define		FB_WRITE_EN					(1 << 1)
650
 
651
#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
652
 
5078 serge 653
/* DCE6 ELD audio interface */
654
#define AZ_F0_CODEC_ENDPOINT_INDEX                       0x5E00
655
#       define AZ_ENDPOINT_REG_INDEX(x)                  (((x) & 0xff) << 0)
656
#       define AZ_ENDPOINT_REG_WRITE_EN                  (1 << 8)
657
#define AZ_F0_CODEC_ENDPOINT_DATA                        0x5E04
658
 
659
#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER          0x25
660
#define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)
661
#define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)
662
#define		SPEAKER_ALLOCATION_SHIFT		0
663
#define		HDMI_CONNECTION				(1 << 16)
664
#define		DP_CONNECTION				(1 << 17)
665
 
666
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0        0x28 /* LPCM */
667
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1        0x29 /* AC3 */
668
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2        0x2A /* MPEG1 */
669
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3        0x2B /* MP3 */
670
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4        0x2C /* MPEG2 */
671
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5        0x2D /* AAC */
672
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6        0x2E /* DTS */
673
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7        0x2F /* ATRAC */
674
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8        0x30 /* one bit audio - leave at 0 (default) */
675
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9        0x31 /* Dolby Digital */
676
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10       0x32 /* DTS-HD */
677
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11       0x33 /* MAT-MLP */
678
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12       0x34 /* DTS */
679
#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13       0x35 /* WMA Pro */
680
#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
681
/* max channels minus one.  7 = 8 channels */
682
#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
683
#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
684
#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
685
/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
686
 * bit0 = 32 kHz
687
 * bit1 = 44.1 kHz
688
 * bit2 = 48 kHz
689
 * bit3 = 88.2 kHz
690
 * bit4 = 96 kHz
691
 * bit5 = 176.4 kHz
692
 * bit6 = 192 kHz
693
 */
694
 
695
#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37
696
#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)
697
#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)
698
/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
699
 * 0   = invalid
700
 * x   = legal delay value
701
 * 255 = sync not supported
702
 */
703
#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38
704
#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */
705
 
706
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a
707
#       define MANUFACTURER_ID(x)                        (((x) & 0xffff) << 0)
708
#       define PRODUCT_ID(x)                             (((x) & 0xffff) << 16)
709
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b
710
#       define SINK_DESCRIPTION_LEN(x)                   (((x) & 0xff) << 0)
711
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c
712
#       define PORT_ID0(x)                               (((x) & 0xffffffff) << 0)
713
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d
714
#       define PORT_ID1(x)                               (((x) & 0xffffffff) << 0)
715
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e
716
#       define DESCRIPTION0(x)                           (((x) & 0xff) << 0)
717
#       define DESCRIPTION1(x)                           (((x) & 0xff) << 8)
718
#       define DESCRIPTION2(x)                           (((x) & 0xff) << 16)
719
#       define DESCRIPTION3(x)                           (((x) & 0xff) << 24)
720
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f
721
#       define DESCRIPTION4(x)                           (((x) & 0xff) << 0)
722
#       define DESCRIPTION5(x)                           (((x) & 0xff) << 8)
723
#       define DESCRIPTION6(x)                           (((x) & 0xff) << 16)
724
#       define DESCRIPTION7(x)                           (((x) & 0xff) << 24)
725
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40
726
#       define DESCRIPTION8(x)                           (((x) & 0xff) << 0)
727
#       define DESCRIPTION9(x)                           (((x) & 0xff) << 8)
728
#       define DESCRIPTION10(x)                          (((x) & 0xff) << 16)
729
#       define DESCRIPTION11(x)                          (((x) & 0xff) << 24)
730
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41
731
#       define DESCRIPTION12(x)                          (((x) & 0xff) << 0)
732
#       define DESCRIPTION13(x)                          (((x) & 0xff) << 8)
733
#       define DESCRIPTION14(x)                          (((x) & 0xff) << 16)
734
#       define DESCRIPTION15(x)                          (((x) & 0xff) << 24)
735
#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42
736
#       define DESCRIPTION16(x)                          (((x) & 0xff) << 0)
737
#       define DESCRIPTION17(x)                          (((x) & 0xff) << 8)
738
 
739
#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL          0x54
740
#       define AUDIO_ENABLED                             (1 << 31)
741
 
742
#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT  0x56
743
#define		PORT_CONNECTIVITY_MASK				(3 << 30)
744
#define		PORT_CONNECTIVITY_SHIFT				30
745
 
2997 Serge 746
#define	DC_LB_MEMORY_SPLIT					0x6b0c
747
#define		DC_LB_MEMORY_CONFIG(x)				((x) << 20)
748
 
749
#define	PRIORITY_A_CNT						0x6b18
750
#define		PRIORITY_MARK_MASK				0x7fff
751
#define		PRIORITY_OFF					(1 << 16)
752
#define		PRIORITY_ALWAYS_ON				(1 << 20)
753
#define	PRIORITY_B_CNT						0x6b1c
754
 
755
#define	DPG_PIPE_ARBITRATION_CONTROL3				0x6cc8
756
#       define LATENCY_WATERMARK_MASK(x)			((x) << 16)
757
#define	DPG_PIPE_LATENCY_CONTROL				0x6ccc
758
#       define LATENCY_LOW_WATERMARK(x)				((x) << 0)
759
#       define LATENCY_HIGH_WATERMARK(x)			((x) << 16)
760
 
761
/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
762
#define VLINE_STATUS                                    0x6bb8
763
#       define VLINE_OCCURRED                           (1 << 0)
764
#       define VLINE_ACK                                (1 << 4)
765
#       define VLINE_STAT                               (1 << 12)
766
#       define VLINE_INTERRUPT                          (1 << 16)
767
#       define VLINE_INTERRUPT_TYPE                     (1 << 17)
768
/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
769
#define VBLANK_STATUS                                   0x6bbc
770
#       define VBLANK_OCCURRED                          (1 << 0)
771
#       define VBLANK_ACK                               (1 << 4)
772
#       define VBLANK_STAT                              (1 << 12)
773
#       define VBLANK_INTERRUPT                         (1 << 16)
774
#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
775
 
776
/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
777
#define INT_MASK                                        0x6b40
778
#       define VBLANK_INT_MASK                          (1 << 0)
779
#       define VLINE_INT_MASK                           (1 << 4)
780
 
781
#define DISP_INTERRUPT_STATUS                           0x60f4
782
#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
783
#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
784
#       define DC_HPD1_INTERRUPT                        (1 << 17)
785
#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
786
#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
787
#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
788
#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
789
#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
790
#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
791
#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
792
#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
793
#       define DC_HPD2_INTERRUPT                        (1 << 17)
794
#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
795
#       define DISP_TIMER_INTERRUPT                     (1 << 24)
796
#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
797
#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
798
#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
799
#       define DC_HPD3_INTERRUPT                        (1 << 17)
800
#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
801
#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
802
#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
803
#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
804
#       define DC_HPD4_INTERRUPT                        (1 << 17)
805
#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
806
#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
807
#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
808
#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
809
#       define DC_HPD5_INTERRUPT                        (1 << 17)
810
#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
811
#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
812
#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
813
#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
814
#       define DC_HPD6_INTERRUPT                        (1 << 17)
815
#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
816
 
817
/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
818
#define GRPH_INT_STATUS                                 0x6858
819
#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
820
#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
821
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
822
#define	GRPH_INT_CONTROL			        0x685c
823
#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
824
#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
825
 
5078 serge 826
#define	DAC_AUTODETECT_INT_CONTROL			0x67c8
2997 Serge 827
 
828
#define DC_HPD1_INT_STATUS                              0x601c
829
#define DC_HPD2_INT_STATUS                              0x6028
830
#define DC_HPD3_INT_STATUS                              0x6034
831
#define DC_HPD4_INT_STATUS                              0x6040
832
#define DC_HPD5_INT_STATUS                              0x604c
833
#define DC_HPD6_INT_STATUS                              0x6058
834
#       define DC_HPDx_INT_STATUS                       (1 << 0)
835
#       define DC_HPDx_SENSE                            (1 << 1)
836
#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
837
 
838
#define DC_HPD1_INT_CONTROL                             0x6020
839
#define DC_HPD2_INT_CONTROL                             0x602c
840
#define DC_HPD3_INT_CONTROL                             0x6038
841
#define DC_HPD4_INT_CONTROL                             0x6044
842
#define DC_HPD5_INT_CONTROL                             0x6050
843
#define DC_HPD6_INT_CONTROL                             0x605c
844
#       define DC_HPDx_INT_ACK                          (1 << 0)
845
#       define DC_HPDx_INT_POLARITY                     (1 << 8)
846
#       define DC_HPDx_INT_EN                           (1 << 16)
847
#       define DC_HPDx_RX_INT_ACK                       (1 << 20)
848
#       define DC_HPDx_RX_INT_EN                        (1 << 24)
849
 
850
#define DC_HPD1_CONTROL                                   0x6024
851
#define DC_HPD2_CONTROL                                   0x6030
852
#define DC_HPD3_CONTROL                                   0x603c
853
#define DC_HPD4_CONTROL                                   0x6048
854
#define DC_HPD5_CONTROL                                   0x6054
855
#define DC_HPD6_CONTROL                                   0x6060
856
#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
857
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
858
#       define DC_HPDx_EN                                 (1 << 28)
859
 
5078 serge 860
#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4
861
#       define STUTTER_ENABLE                             (1 << 0)
862
 
2997 Serge 863
/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
864
#define CRTC_STATUS_FRAME_COUNT                         0x6e98
865
 
5078 serge 866
#define AFMT_AUDIO_SRC_CONTROL                          0x713c
867
#define		AFMT_AUDIO_SRC_SELECT(x)		(((x) & 7) << 0)
868
/* AFMT_AUDIO_SRC_SELECT
869
 * 0 = stream0
870
 * 1 = stream1
871
 * 2 = stream2
872
 * 3 = stream3
873
 * 4 = stream4
874
 * 5 = stream5
875
 */
876
 
2997 Serge 877
#define	GRBM_CNTL					0x8000
878
#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
879
 
880
#define	GRBM_STATUS2					0x8008
881
#define		RLC_RQ_PENDING 					(1 << 0)
882
#define		RLC_BUSY 					(1 << 8)
883
#define		TC_BUSY 					(1 << 9)
884
 
885
#define	GRBM_STATUS					0x8010
886
#define		CMDFIFO_AVAIL_MASK				0x0000000F
887
#define		RING2_RQ_PENDING				(1 << 4)
888
#define		SRBM_RQ_PENDING					(1 << 5)
889
#define		RING1_RQ_PENDING				(1 << 6)
890
#define		CF_RQ_PENDING					(1 << 7)
891
#define		PF_RQ_PENDING					(1 << 8)
892
#define		GDS_DMA_RQ_PENDING				(1 << 9)
893
#define		GRBM_EE_BUSY					(1 << 10)
894
#define		DB_CLEAN					(1 << 12)
895
#define		CB_CLEAN					(1 << 13)
896
#define		TA_BUSY 					(1 << 14)
897
#define		GDS_BUSY 					(1 << 15)
898
#define		VGT_BUSY					(1 << 17)
899
#define		IA_BUSY_NO_DMA					(1 << 18)
900
#define		IA_BUSY						(1 << 19)
901
#define		SX_BUSY 					(1 << 20)
902
#define		SPI_BUSY					(1 << 22)
903
#define		BCI_BUSY					(1 << 23)
904
#define		SC_BUSY 					(1 << 24)
905
#define		PA_BUSY 					(1 << 25)
906
#define		DB_BUSY 					(1 << 26)
907
#define		CP_COHERENCY_BUSY      				(1 << 28)
908
#define		CP_BUSY 					(1 << 29)
909
#define		CB_BUSY 					(1 << 30)
910
#define		GUI_ACTIVE					(1 << 31)
911
#define	GRBM_STATUS_SE0					0x8014
912
#define	GRBM_STATUS_SE1					0x8018
913
#define		SE_DB_CLEAN					(1 << 1)
914
#define		SE_CB_CLEAN					(1 << 2)
915
#define		SE_BCI_BUSY					(1 << 22)
916
#define		SE_VGT_BUSY					(1 << 23)
917
#define		SE_PA_BUSY					(1 << 24)
918
#define		SE_TA_BUSY					(1 << 25)
919
#define		SE_SX_BUSY					(1 << 26)
920
#define		SE_SPI_BUSY					(1 << 27)
921
#define		SE_SC_BUSY					(1 << 29)
922
#define		SE_DB_BUSY					(1 << 30)
923
#define		SE_CB_BUSY					(1 << 31)
924
 
925
#define	GRBM_SOFT_RESET					0x8020
926
#define		SOFT_RESET_CP					(1 << 0)
927
#define		SOFT_RESET_CB					(1 << 1)
928
#define		SOFT_RESET_RLC					(1 << 2)
929
#define		SOFT_RESET_DB					(1 << 3)
930
#define		SOFT_RESET_GDS					(1 << 4)
931
#define		SOFT_RESET_PA					(1 << 5)
932
#define		SOFT_RESET_SC					(1 << 6)
933
#define		SOFT_RESET_BCI					(1 << 7)
934
#define		SOFT_RESET_SPI					(1 << 8)
935
#define		SOFT_RESET_SX					(1 << 10)
936
#define		SOFT_RESET_TC					(1 << 11)
937
#define		SOFT_RESET_TA					(1 << 12)
938
#define		SOFT_RESET_VGT					(1 << 14)
939
#define		SOFT_RESET_IA					(1 << 15)
940
 
941
#define GRBM_GFX_INDEX          			0x802C
942
#define		INSTANCE_INDEX(x)			((x) << 0)
943
#define		SH_INDEX(x)     			((x) << 8)
944
#define		SE_INDEX(x)     			((x) << 16)
945
#define		SH_BROADCAST_WRITES      		(1 << 29)
946
#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
947
#define		SE_BROADCAST_WRITES      		(1 << 31)
948
 
949
#define GRBM_INT_CNTL                                   0x8060
950
#       define RDERR_INT_ENABLE                         (1 << 0)
951
#       define GUI_IDLE_INT_ENABLE                      (1 << 19)
952
 
3031 serge 953
#define	CP_STRMOUT_CNTL					0x84FC
2997 Serge 954
#define	SCRATCH_REG0					0x8500
955
#define	SCRATCH_REG1					0x8504
956
#define	SCRATCH_REG2					0x8508
957
#define	SCRATCH_REG3					0x850C
958
#define	SCRATCH_REG4					0x8510
959
#define	SCRATCH_REG5					0x8514
960
#define	SCRATCH_REG6					0x8518
961
#define	SCRATCH_REG7					0x851C
962
 
963
#define	SCRATCH_UMSK					0x8540
964
#define	SCRATCH_ADDR					0x8544
965
 
966
#define	CP_SEM_WAIT_TIMER				0x85BC
967
 
968
#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8
969
 
970
#define CP_ME_CNTL					0x86D8
971
#define		CP_CE_HALT					(1 << 24)
972
#define		CP_PFP_HALT					(1 << 26)
973
#define		CP_ME_HALT					(1 << 28)
974
 
975
#define	CP_COHER_CNTL2					0x85E8
976
 
977
#define	CP_RB2_RPTR					0x86f8
978
#define	CP_RB1_RPTR					0x86fc
979
#define	CP_RB0_RPTR					0x8700
980
#define	CP_RB_WPTR_DELAY				0x8704
981
 
982
#define	CP_QUEUE_THRESHOLDS				0x8760
983
#define		ROQ_IB1_START(x)				((x) << 0)
984
#define		ROQ_IB2_START(x)				((x) << 8)
985
#define CP_MEQ_THRESHOLDS				0x8764
986
#define		MEQ1_START(x)				((x) << 0)
987
#define		MEQ2_START(x)				((x) << 8)
988
 
989
#define	CP_PERFMON_CNTL					0x87FC
990
 
991
#define	VGT_VTX_VECT_EJECT_REG				0x88B0
992
 
993
#define	VGT_CACHE_INVALIDATION				0x88C4
994
#define		CACHE_INVALIDATION(x)				((x) << 0)
995
#define			VC_ONLY						0
996
#define			TC_ONLY						1
997
#define			VC_AND_TC					2
998
#define		AUTO_INVLD_EN(x)				((x) << 6)
999
#define			NO_AUTO						0
1000
#define			ES_AUTO						1
1001
#define			GS_AUTO						2
1002
#define			ES_AND_GS_AUTO					3
1003
#define	VGT_ESGS_RING_SIZE				0x88C8
1004
#define	VGT_GSVS_RING_SIZE				0x88CC
1005
 
1006
#define	VGT_GS_VERTEX_REUSE				0x88D4
1007
 
1008
#define	VGT_PRIMITIVE_TYPE				0x8958
1009
#define	VGT_INDEX_TYPE					0x895C
1010
 
1011
#define	VGT_NUM_INDICES					0x8970
1012
#define	VGT_NUM_INSTANCES				0x8974
1013
 
1014
#define	VGT_TF_RING_SIZE				0x8988
1015
 
1016
#define	VGT_HS_OFFCHIP_PARAM				0x89B0
1017
 
1018
#define	VGT_TF_MEMORY_BASE				0x89B8
1019
 
1020
#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc
1021
#define		INACTIVE_CUS_MASK			0xFFFF0000
1022
#define		INACTIVE_CUS_SHIFT			16
1023
#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0
1024
 
1025
#define	PA_CL_ENHANCE					0x8A14
1026
#define		CLIP_VTX_REORDER_ENA				(1 << 0)
1027
#define		NUM_CLIP_SEQ(x)					((x) << 1)
1028
 
1029
#define	PA_SU_LINE_STIPPLE_VALUE			0x8A60
1030
 
1031
#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
1032
 
1033
#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
1034
#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
1035
#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
1036
 
1037
#define	PA_SC_FIFO_SIZE					0x8BCC
1038
#define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) << 0)
1039
#define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) << 6)
1040
#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 15)
1041
#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 23)
1042
 
1043
#define	PA_SC_ENHANCE					0x8BF0
1044
 
1045
#define	SQ_CONFIG					0x8C00
1046
 
1047
#define	SQC_CACHES					0x8C08
1048
 
5078 serge 1049
#define SQ_POWER_THROTTLE                               0x8e58
1050
#define		MIN_POWER(x)				((x) << 0)
1051
#define		MIN_POWER_MASK				(0x3fff << 0)
1052
#define		MIN_POWER_SHIFT				0
1053
#define		MAX_POWER(x)				((x) << 16)
1054
#define		MAX_POWER_MASK				(0x3fff << 16)
1055
#define		MAX_POWER_SHIFT				0
1056
#define SQ_POWER_THROTTLE2                              0x8e5c
1057
#define		MAX_POWER_DELTA(x)			((x) << 0)
1058
#define		MAX_POWER_DELTA_MASK			(0x3fff << 0)
1059
#define		MAX_POWER_DELTA_SHIFT			0
1060
#define		STI_SIZE(x)				((x) << 16)
1061
#define		STI_SIZE_MASK				(0x3ff << 16)
1062
#define		STI_SIZE_SHIFT				16
1063
#define		LTI_RATIO(x)				((x) << 27)
1064
#define		LTI_RATIO_MASK				(0xf << 27)
1065
#define		LTI_RATIO_SHIFT				27
1066
 
2997 Serge 1067
#define	SX_DEBUG_1					0x9060
1068
 
1069
#define	SPI_STATIC_THREAD_MGMT_1			0x90E0
1070
#define	SPI_STATIC_THREAD_MGMT_2			0x90E4
1071
#define	SPI_STATIC_THREAD_MGMT_3			0x90E8
1072
#define	SPI_PS_MAX_WAVE_ID				0x90EC
1073
 
1074
#define	SPI_CONFIG_CNTL					0x9100
1075
 
1076
#define	SPI_CONFIG_CNTL_1				0x913C
1077
#define		VTX_DONE_DELAY(x)				((x) << 0)
1078
#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
1079
 
1080
#define	CGTS_TCC_DISABLE				0x9148
1081
#define	CGTS_USER_TCC_DISABLE				0x914C
1082
#define		TCC_DISABLE_MASK				0xFFFF0000
1083
#define		TCC_DISABLE_SHIFT				16
5078 serge 1084
#define	CGTS_SM_CTRL_REG				0x9150
1085
#define		OVERRIDE				(1 << 21)
1086
#define		LS_OVERRIDE				(1 << 22)
2997 Serge 1087
 
5078 serge 1088
#define	SPI_LB_CU_MASK					0x9354
1089
 
2997 Serge 1090
#define	TA_CNTL_AUX					0x9508
1091
 
1092
#define CC_RB_BACKEND_DISABLE				0x98F4
1093
#define		BACKEND_DISABLE(x)     			((x) << 16)
1094
#define GB_ADDR_CONFIG  				0x98F8
1095
#define		NUM_PIPES(x)				((x) << 0)
1096
#define		NUM_PIPES_MASK				0x00000007
1097
#define		NUM_PIPES_SHIFT				0
1098
#define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
1099
#define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
1100
#define		PIPE_INTERLEAVE_SIZE_SHIFT		4
1101
#define		NUM_SHADER_ENGINES(x)			((x) << 12)
1102
#define		NUM_SHADER_ENGINES_MASK			0x00003000
1103
#define		NUM_SHADER_ENGINES_SHIFT		12
1104
#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
1105
#define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
1106
#define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
1107
#define		NUM_GPUS(x)     			((x) << 20)
1108
#define		NUM_GPUS_MASK				0x00700000
1109
#define		NUM_GPUS_SHIFT				20
1110
#define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)
1111
#define		MULTI_GPU_TILE_SIZE_MASK		0x03000000
1112
#define		MULTI_GPU_TILE_SIZE_SHIFT		24
1113
#define		ROW_SIZE(x)             		((x) << 28)
1114
#define		ROW_SIZE_MASK				0x30000000
1115
#define		ROW_SIZE_SHIFT				28
1116
 
1117
#define	GB_TILE_MODE0					0x9910
1118
#       define MICRO_TILE_MODE(x)				((x) << 0)
1119
#              define	ADDR_SURF_DISPLAY_MICRO_TILING		0
1120
#              define	ADDR_SURF_THIN_MICRO_TILING		1
1121
#              define	ADDR_SURF_DEPTH_MICRO_TILING		2
1122
#       define ARRAY_MODE(x)					((x) << 2)
1123
#              define	ARRAY_LINEAR_GENERAL			0
1124
#              define	ARRAY_LINEAR_ALIGNED			1
1125
#              define	ARRAY_1D_TILED_THIN1			2
1126
#              define	ARRAY_2D_TILED_THIN1			4
1127
#       define PIPE_CONFIG(x)					((x) << 6)
1128
#              define	ADDR_SURF_P2				0
1129
#              define	ADDR_SURF_P4_8x16			4
1130
#              define	ADDR_SURF_P4_16x16			5
1131
#              define	ADDR_SURF_P4_16x32			6
1132
#              define	ADDR_SURF_P4_32x32			7
1133
#              define	ADDR_SURF_P8_16x16_8x16			8
1134
#              define	ADDR_SURF_P8_16x32_8x16			9
1135
#              define	ADDR_SURF_P8_32x32_8x16			10
1136
#              define	ADDR_SURF_P8_16x32_16x16		11
1137
#              define	ADDR_SURF_P8_32x32_16x16		12
1138
#              define	ADDR_SURF_P8_32x32_16x32		13
1139
#              define	ADDR_SURF_P8_32x64_32x32		14
1140
#       define TILE_SPLIT(x)					((x) << 11)
1141
#              define	ADDR_SURF_TILE_SPLIT_64B		0
1142
#              define	ADDR_SURF_TILE_SPLIT_128B		1
1143
#              define	ADDR_SURF_TILE_SPLIT_256B		2
1144
#              define	ADDR_SURF_TILE_SPLIT_512B		3
1145
#              define	ADDR_SURF_TILE_SPLIT_1KB		4
1146
#              define	ADDR_SURF_TILE_SPLIT_2KB		5
1147
#              define	ADDR_SURF_TILE_SPLIT_4KB		6
1148
#       define BANK_WIDTH(x)					((x) << 14)
1149
#              define	ADDR_SURF_BANK_WIDTH_1			0
1150
#              define	ADDR_SURF_BANK_WIDTH_2			1
1151
#              define	ADDR_SURF_BANK_WIDTH_4			2
1152
#              define	ADDR_SURF_BANK_WIDTH_8			3
1153
#       define BANK_HEIGHT(x)					((x) << 16)
1154
#              define	ADDR_SURF_BANK_HEIGHT_1			0
1155
#              define	ADDR_SURF_BANK_HEIGHT_2			1
1156
#              define	ADDR_SURF_BANK_HEIGHT_4			2
1157
#              define	ADDR_SURF_BANK_HEIGHT_8			3
1158
#       define MACRO_TILE_ASPECT(x)				((x) << 18)
1159
#              define	ADDR_SURF_MACRO_ASPECT_1		0
1160
#              define	ADDR_SURF_MACRO_ASPECT_2		1
1161
#              define	ADDR_SURF_MACRO_ASPECT_4		2
1162
#              define	ADDR_SURF_MACRO_ASPECT_8		3
1163
#       define NUM_BANKS(x)					((x) << 20)
1164
#              define	ADDR_SURF_2_BANK			0
1165
#              define	ADDR_SURF_4_BANK			1
1166
#              define	ADDR_SURF_8_BANK			2
1167
#              define	ADDR_SURF_16_BANK			3
1168
 
1169
#define	CB_PERFCOUNTER0_SELECT0				0x9a20
1170
#define	CB_PERFCOUNTER0_SELECT1				0x9a24
1171
#define	CB_PERFCOUNTER1_SELECT0				0x9a28
1172
#define	CB_PERFCOUNTER1_SELECT1				0x9a2c
1173
#define	CB_PERFCOUNTER2_SELECT0				0x9a30
1174
#define	CB_PERFCOUNTER2_SELECT1				0x9a34
1175
#define	CB_PERFCOUNTER3_SELECT0				0x9a38
1176
#define	CB_PERFCOUNTER3_SELECT1				0x9a3c
1177
 
5078 serge 1178
#define	CB_CGTT_SCLK_CTRL				0x9a60
1179
 
2997 Serge 1180
#define	GC_USER_RB_BACKEND_DISABLE			0x9B7C
1181
#define		BACKEND_DISABLE_MASK			0x00FF0000
1182
#define		BACKEND_DISABLE_SHIFT			16
1183
 
1184
#define	TCP_CHAN_STEER_LO				0xac0c
1185
#define	TCP_CHAN_STEER_HI				0xac10
1186
 
1187
#define	CP_RB0_BASE					0xC100
1188
#define	CP_RB0_CNTL					0xC104
1189
#define		RB_BUFSZ(x)					((x) << 0)
1190
#define		RB_BLKSZ(x)					((x) << 8)
1191
#define		BUF_SWAP_32BIT					(2 << 16)
1192
#define		RB_NO_UPDATE					(1 << 27)
1193
#define		RB_RPTR_WR_ENA					(1 << 31)
1194
 
1195
#define	CP_RB0_RPTR_ADDR				0xC10C
1196
#define	CP_RB0_RPTR_ADDR_HI				0xC110
1197
#define	CP_RB0_WPTR					0xC114
1198
 
1199
#define	CP_PFP_UCODE_ADDR				0xC150
1200
#define	CP_PFP_UCODE_DATA				0xC154
1201
#define	CP_ME_RAM_RADDR					0xC158
1202
#define	CP_ME_RAM_WADDR					0xC15C
1203
#define	CP_ME_RAM_DATA					0xC160
1204
 
1205
#define	CP_CE_UCODE_ADDR				0xC168
1206
#define	CP_CE_UCODE_DATA				0xC16C
1207
 
1208
#define	CP_RB1_BASE					0xC180
1209
#define	CP_RB1_CNTL					0xC184
1210
#define	CP_RB1_RPTR_ADDR				0xC188
1211
#define	CP_RB1_RPTR_ADDR_HI				0xC18C
1212
#define	CP_RB1_WPTR					0xC190
1213
#define	CP_RB2_BASE					0xC194
1214
#define	CP_RB2_CNTL					0xC198
1215
#define	CP_RB2_RPTR_ADDR				0xC19C
1216
#define	CP_RB2_RPTR_ADDR_HI				0xC1A0
1217
#define	CP_RB2_WPTR					0xC1A4
1218
#define CP_INT_CNTL_RING0                               0xC1A8
1219
#define CP_INT_CNTL_RING1                               0xC1AC
1220
#define CP_INT_CNTL_RING2                               0xC1B0
1221
#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
1222
#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
1223
#       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
1224
#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
1225
#       define CP_RINGID2_INT_ENABLE                    (1 << 29)
1226
#       define CP_RINGID1_INT_ENABLE                    (1 << 30)
1227
#       define CP_RINGID0_INT_ENABLE                    (1 << 31)
1228
#define CP_INT_STATUS_RING0                             0xC1B4
1229
#define CP_INT_STATUS_RING1                             0xC1B8
1230
#define CP_INT_STATUS_RING2                             0xC1BC
1231
#       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
1232
#       define TIME_STAMP_INT_STAT                      (1 << 26)
1233
#       define CP_RINGID2_INT_STAT                      (1 << 29)
1234
#       define CP_RINGID1_INT_STAT                      (1 << 30)
1235
#       define CP_RINGID0_INT_STAT                      (1 << 31)
1236
 
5078 serge 1237
#define	CP_MEM_SLP_CNTL					0xC1E4
1238
#       define CP_MEM_LS_EN                             (1 << 0)
1239
 
2997 Serge 1240
#define	CP_DEBUG					0xC1FC
1241
 
1242
#define RLC_CNTL                                          0xC300
1243
#       define RLC_ENABLE                                 (1 << 0)
1244
#define RLC_RL_BASE                                       0xC304
1245
#define RLC_RL_SIZE                                       0xC308
1246
#define RLC_LB_CNTL                                       0xC30C
5078 serge 1247
#       define LOAD_BALANCE_ENABLE                        (1 << 0)
2997 Serge 1248
#define RLC_SAVE_AND_RESTORE_BASE                         0xC310
1249
#define RLC_LB_CNTR_MAX                                   0xC314
1250
#define RLC_LB_CNTR_INIT                                  0xC318
1251
 
1252
#define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320
1253
 
1254
#define RLC_UCODE_ADDR                                    0xC32C
1255
#define RLC_UCODE_DATA                                    0xC330
1256
 
1257
#define RLC_GPU_CLOCK_COUNT_LSB                           0xC338
1258
#define RLC_GPU_CLOCK_COUNT_MSB                           0xC33C
1259
#define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC340
1260
#define RLC_MC_CNTL                                       0xC344
1261
#define RLC_UCODE_CNTL                                    0xC348
5078 serge 1262
#define RLC_STAT                                          0xC34C
1263
#       define RLC_BUSY_STATUS                            (1 << 0)
1264
#       define GFX_POWER_STATUS                           (1 << 1)
1265
#       define GFX_CLOCK_STATUS                           (1 << 2)
1266
#       define GFX_LS_STATUS                              (1 << 3)
2997 Serge 1267
 
5078 serge 1268
#define	RLC_PG_CNTL					0xC35C
1269
#	define GFX_PG_ENABLE				(1 << 0)
1270
#	define GFX_PG_SRC				(1 << 1)
1271
 
1272
#define	RLC_CGTT_MGCG_OVERRIDE				0xC400
1273
#define	RLC_CGCG_CGLS_CTRL				0xC404
1274
#	define CGCG_EN					(1 << 0)
1275
#	define CGLS_EN					(1 << 1)
1276
 
1277
#define	RLC_TTOP_D					0xC414
1278
#	define RLC_PUD(x)				((x) << 0)
1279
#	define RLC_PUD_MASK				(0xff << 0)
1280
#	define RLC_PDD(x)				((x) << 8)
1281
#	define RLC_PDD_MASK				(0xff << 8)
1282
#	define RLC_TTPD(x)				((x) << 16)
1283
#	define RLC_TTPD_MASK				(0xff << 16)
1284
#	define RLC_MSD(x)				((x) << 24)
1285
#	define RLC_MSD_MASK				(0xff << 24)
1286
 
1287
#define RLC_LB_INIT_CU_MASK                               0xC41C
1288
 
1289
#define	RLC_PG_AO_CU_MASK				0xC42C
1290
#define	RLC_MAX_PG_CU					0xC430
1291
#	define MAX_PU_CU(x)				((x) << 0)
1292
#	define MAX_PU_CU_MASK				(0xff << 0)
1293
#define	RLC_AUTO_PG_CTRL				0xC434
1294
#	define AUTO_PG_EN				(1 << 0)
1295
#	define GRBM_REG_SGIT(x)				((x) << 3)
1296
#	define GRBM_REG_SGIT_MASK			(0xffff << 3)
1297
#	define PG_AFTER_GRBM_REG_ST(x)			((x) << 19)
1298
#	define PG_AFTER_GRBM_REG_ST_MASK		(0x1fff << 19)
1299
 
1300
#define RLC_SERDES_WR_MASTER_MASK_0                       0xC454
1301
#define RLC_SERDES_WR_MASTER_MASK_1                       0xC458
1302
#define RLC_SERDES_WR_CTRL                                0xC45C
1303
 
1304
#define RLC_SERDES_MASTER_BUSY_0                          0xC464
1305
#define RLC_SERDES_MASTER_BUSY_1                          0xC468
1306
 
1307
#define RLC_GCPM_GENERAL_3                                0xC478
1308
 
1309
#define	DB_RENDER_CONTROL				0x28000
1310
 
1311
#define DB_DEPTH_INFO                                   0x2803c
1312
 
2997 Serge 1313
#define PA_SC_RASTER_CONFIG                             0x28350
1314
#       define RASTER_CONFIG_RB_MAP_0                   0
1315
#       define RASTER_CONFIG_RB_MAP_1                   1
1316
#       define RASTER_CONFIG_RB_MAP_2                   2
1317
#       define RASTER_CONFIG_RB_MAP_3                   3
1318
 
1319
#define VGT_EVENT_INITIATOR                             0x28a90
1320
#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
1321
#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
1322
#       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
1323
#       define CACHE_FLUSH_TS                           (4 << 0)
1324
#       define CACHE_FLUSH                              (6 << 0)
1325
#       define CS_PARTIAL_FLUSH                         (7 << 0)
1326
#       define VGT_STREAMOUT_RESET                      (10 << 0)
1327
#       define END_OF_PIPE_INCR_DE                      (11 << 0)
1328
#       define END_OF_PIPE_IB_END                       (12 << 0)
1329
#       define RST_PIX_CNT                              (13 << 0)
1330
#       define VS_PARTIAL_FLUSH                         (15 << 0)
1331
#       define PS_PARTIAL_FLUSH                         (16 << 0)
1332
#       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
1333
#       define ZPASS_DONE                               (21 << 0)
1334
#       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
1335
#       define PERFCOUNTER_START                        (23 << 0)
1336
#       define PERFCOUNTER_STOP                         (24 << 0)
1337
#       define PIPELINESTAT_START                       (25 << 0)
1338
#       define PIPELINESTAT_STOP                        (26 << 0)
1339
#       define PERFCOUNTER_SAMPLE                       (27 << 0)
1340
#       define SAMPLE_PIPELINESTAT                      (30 << 0)
1341
#       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
1342
#       define RESET_VTX_CNT                            (33 << 0)
1343
#       define VGT_FLUSH                                (36 << 0)
1344
#       define BOTTOM_OF_PIPE_TS                        (40 << 0)
1345
#       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
1346
#       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
1347
#       define FLUSH_AND_INV_DB_META                    (44 << 0)
1348
#       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
1349
#       define FLUSH_AND_INV_CB_META                    (46 << 0)
1350
#       define CS_DONE                                  (47 << 0)
1351
#       define PS_DONE                                  (48 << 0)
1352
#       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
1353
#       define THREAD_TRACE_START                       (51 << 0)
1354
#       define THREAD_TRACE_STOP                        (52 << 0)
1355
#       define THREAD_TRACE_FLUSH                       (54 << 0)
1356
#       define THREAD_TRACE_FINISH                      (55 << 0)
1357
 
5078 serge 1358
/* PIF PHY0 registers idx/data 0x8/0xc */
1359
#define PB0_PIF_CNTL                                      0x10
1360
#       define LS2_EXIT_TIME(x)                           ((x) << 17)
1361
#       define LS2_EXIT_TIME_MASK                         (0x7 << 17)
1362
#       define LS2_EXIT_TIME_SHIFT                        17
1363
#define PB0_PIF_PAIRING                                   0x11
1364
#       define MULTI_PIF                                  (1 << 25)
1365
#define PB0_PIF_PWRDOWN_0                                 0x12
1366
#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)
1367
#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)
1368
#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7
1369
#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)
1370
#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)
1371
#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10
1372
#       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)
1373
#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)
1374
#       define PLL_RAMP_UP_TIME_0_SHIFT                   24
1375
#define PB0_PIF_PWRDOWN_1                                 0x13
1376
#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)
1377
#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)
1378
#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7
1379
#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)
1380
#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)
1381
#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10
1382
#       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)
1383
#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)
1384
#       define PLL_RAMP_UP_TIME_1_SHIFT                   24
1385
 
1386
#define PB0_PIF_PWRDOWN_2                                 0x17
1387
#       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) << 7)
1388
#       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 << 7)
1389
#       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7
1390
#       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) << 10)
1391
#       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 << 10)
1392
#       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10
1393
#       define PLL_RAMP_UP_TIME_2(x)                      ((x) << 24)
1394
#       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 << 24)
1395
#       define PLL_RAMP_UP_TIME_2_SHIFT                   24
1396
#define PB0_PIF_PWRDOWN_3                                 0x18
1397
#       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) << 7)
1398
#       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 << 7)
1399
#       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7
1400
#       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) << 10)
1401
#       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 << 10)
1402
#       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10
1403
#       define PLL_RAMP_UP_TIME_3(x)                      ((x) << 24)
1404
#       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 << 24)
1405
#       define PLL_RAMP_UP_TIME_3_SHIFT                   24
1406
/* PIF PHY1 registers idx/data 0x10/0x14 */
1407
#define PB1_PIF_CNTL                                      0x10
1408
#define PB1_PIF_PAIRING                                   0x11
1409
#define PB1_PIF_PWRDOWN_0                                 0x12
1410
#define PB1_PIF_PWRDOWN_1                                 0x13
1411
 
1412
#define PB1_PIF_PWRDOWN_2                                 0x17
1413
#define PB1_PIF_PWRDOWN_3                                 0x18
1414
/* PCIE registers idx/data 0x30/0x34 */
1415
#define PCIE_CNTL2                                        0x1c /* PCIE */
1416
#       define SLV_MEM_LS_EN                              (1 << 16)
1417
#       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 << 17)
1418
#       define MST_MEM_LS_EN                              (1 << 18)
1419
#       define REPLAY_MEM_LS_EN                           (1 << 19)
1420
#define PCIE_LC_STATUS1                                   0x28 /* PCIE */
1421
#       define LC_REVERSE_RCVR                            (1 << 0)
1422
#       define LC_REVERSE_XMIT                            (1 << 1)
1423
#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)
1424
#       define LC_OPERATING_LINK_WIDTH_SHIFT              2
1425
#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)
1426
#       define LC_DETECTED_LINK_WIDTH_SHIFT               5
1427
 
1428
#define PCIE_P_CNTL                                       0x40 /* PCIE */
1429
#       define P_IGNORE_EDB_ERR                           (1 << 6)
1430
 
1431
/* PCIE PORT registers idx/data 0x38/0x3c */
1432
#define PCIE_LC_CNTL                                      0xa0
1433
#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
1434
#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
1435
#       define LC_L0S_INACTIVITY_SHIFT                    8
1436
#       define LC_L1_INACTIVITY(x)                        ((x) << 12)
1437
#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
1438
#       define LC_L1_INACTIVITY_SHIFT                     12
1439
#       define LC_PMI_TO_L1_DIS                           (1 << 16)
1440
#       define LC_ASPM_TO_L1_DIS                          (1 << 24)
1441
#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
1442
#       define LC_LINK_WIDTH_SHIFT                        0
1443
#       define LC_LINK_WIDTH_MASK                         0x7
1444
#       define LC_LINK_WIDTH_X0                           0
1445
#       define LC_LINK_WIDTH_X1                           1
1446
#       define LC_LINK_WIDTH_X2                           2
1447
#       define LC_LINK_WIDTH_X4                           3
1448
#       define LC_LINK_WIDTH_X8                           4
1449
#       define LC_LINK_WIDTH_X16                          6
1450
#       define LC_LINK_WIDTH_RD_SHIFT                     4
1451
#       define LC_LINK_WIDTH_RD_MASK                      0x70
1452
#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
1453
#       define LC_RECONFIG_NOW                            (1 << 8)
1454
#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
1455
#       define LC_RENEGOTIATE_EN                          (1 << 10)
1456
#       define LC_SHORT_RECONFIG_EN                       (1 << 11)
1457
#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
1458
#       define LC_UPCONFIGURE_DIS                         (1 << 13)
1459
#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)
1460
#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)
1461
#       define LC_DYN_LANES_PWR_STATE_SHIFT               21
1462
#define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */
1463
#       define LC_XMIT_N_FTS(x)                           ((x) << 0)
1464
#       define LC_XMIT_N_FTS_MASK                         (0xff << 0)
1465
#       define LC_XMIT_N_FTS_SHIFT                        0
1466
#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)
1467
#       define LC_N_FTS_MASK                              (0xff << 24)
1468
#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
1469
#       define LC_GEN2_EN_STRAP                           (1 << 0)
1470
#       define LC_GEN3_EN_STRAP                           (1 << 1)
1471
#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 2)
1472
#       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 << 3)
1473
#       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3
1474
#       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 << 5)
1475
#       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 << 6)
1476
#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 7)
1477
#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 8)
1478
#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 9)
1479
#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 10)
1480
#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10
1481
#       define LC_CURRENT_DATA_RATE_MASK                  (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1482
#       define LC_CURRENT_DATA_RATE_SHIFT                 13
1483
#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 16)
1484
#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 18)
1485
#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)
1486
#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)
1487
#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)
1488
 
1489
#define PCIE_LC_CNTL2                                     0xb1
1490
#       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)
1491
#       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)
1492
 
1493
#define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */
1494
#       define LC_GO_TO_RECOVERY                          (1 << 30)
1495
#define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */
1496
#       define LC_REDO_EQ                                 (1 << 5)
1497
#       define LC_SET_QUIESCE                             (1 << 13)
1498
 
2997 Serge 1499
/*
3764 Serge 1500
 * UVD
1501
 */
1502
#define UVD_UDEC_ADDR_CONFIG				0xEF4C
1503
#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
1504
#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
1505
#define UVD_RBC_RB_RPTR					0xF690
1506
#define UVD_RBC_RB_WPTR					0xF694
1507
 
5078 serge 1508
#define	UVD_CGC_CTRL					0xF4B0
1509
#	define DCM					(1 << 0)
1510
#	define CG_DT(x)					((x) << 2)
1511
#	define CG_DT_MASK				(0xf << 2)
1512
#	define CLK_OD(x)				((x) << 6)
1513
#	define CLK_OD_MASK				(0x1f << 6)
1514
 
1515
 /* UVD CTX indirect */
1516
#define	UVD_CGC_MEM_CTRL				0xC0
1517
#define	UVD_CGC_CTRL2					0xC1
1518
#	define DYN_OR_EN				(1 << 0)
1519
#	define DYN_RR_EN				(1 << 1)
1520
#	define G_DIV_ID(x)				((x) << 2)
1521
#	define G_DIV_ID_MASK				(0x7 << 2)
1522
 
3764 Serge 1523
/*
2997 Serge 1524
 * PM4
1525
 */
3764 Serge 1526
#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
2997 Serge 1527
			 (((reg) >> 2) & 0xFFFF) |			\
1528
			 ((n) & 0x3FFF) << 16)
1529
#define CP_PACKET2			0x80000000
1530
#define		PACKET2_PAD_SHIFT		0
1531
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
1532
 
1533
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1534
 
3764 Serge 1535
#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
2997 Serge 1536
			 (((op) & 0xFF) << 8) |				\
1537
			 ((n) & 0x3FFF) << 16)
1538
 
1539
#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1540
 
1541
/* Packet 3 types */
1542
#define	PACKET3_NOP					0x10
1543
#define	PACKET3_SET_BASE				0x11
1544
#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
1545
#define			GDS_PARTITION_BASE		2
1546
#define			CE_PARTITION_BASE		3
1547
#define	PACKET3_CLEAR_STATE				0x12
1548
#define	PACKET3_INDEX_BUFFER_SIZE			0x13
1549
#define	PACKET3_DISPATCH_DIRECT				0x15
1550
#define	PACKET3_DISPATCH_INDIRECT			0x16
1551
#define	PACKET3_ALLOC_GDS				0x1B
1552
#define	PACKET3_WRITE_GDS_RAM				0x1C
1553
#define	PACKET3_ATOMIC_GDS				0x1D
1554
#define	PACKET3_ATOMIC					0x1E
1555
#define	PACKET3_OCCLUSION_QUERY				0x1F
1556
#define	PACKET3_SET_PREDICATION				0x20
1557
#define	PACKET3_REG_RMW					0x21
1558
#define	PACKET3_COND_EXEC				0x22
1559
#define	PACKET3_PRED_EXEC				0x23
1560
#define	PACKET3_DRAW_INDIRECT				0x24
1561
#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
1562
#define	PACKET3_INDEX_BASE				0x26
1563
#define	PACKET3_DRAW_INDEX_2				0x27
1564
#define	PACKET3_CONTEXT_CONTROL				0x28
1565
#define	PACKET3_INDEX_TYPE				0x2A
1566
#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
1567
#define	PACKET3_DRAW_INDEX_AUTO				0x2D
1568
#define	PACKET3_DRAW_INDEX_IMMD				0x2E
1569
#define	PACKET3_NUM_INSTANCES				0x2F
1570
#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
1571
#define	PACKET3_INDIRECT_BUFFER_CONST			0x31
1572
#define	PACKET3_INDIRECT_BUFFER				0x32
1573
#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
1574
#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
1575
#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
1576
#define	PACKET3_WRITE_DATA				0x37
1577
#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
1578
                /* 0 - register
1579
		 * 1 - memory (sync - via GRBM)
1580
		 * 2 - tc/l2
1581
		 * 3 - gds
1582
		 * 4 - reserved
1583
		 * 5 - memory (async - direct)
1584
		 */
1585
#define		WR_ONE_ADDR                             (1 << 16)
1586
#define		WR_CONFIRM                              (1 << 20)
1587
#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
1588
                /* 0 - me
1589
		 * 1 - pfp
1590
		 * 2 - ce
1591
		 */
1592
#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
1593
#define	PACKET3_MEM_SEMAPHORE				0x39
1594
#define	PACKET3_MPEG_INDEX				0x3A
1595
#define	PACKET3_COPY_DW					0x3B
1596
#define	PACKET3_WAIT_REG_MEM				0x3C
1597
#define	PACKET3_MEM_WRITE				0x3D
1598
#define	PACKET3_COPY_DATA				0x40
3192 Serge 1599
#define	PACKET3_CP_DMA					0x41
1600
/* 1. header
1601
 * 2. SRC_ADDR_LO or DATA [31:0]
1602
 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1603
 *    SRC_ADDR_HI [7:0]
1604
 * 4. DST_ADDR_LO [31:0]
1605
 * 5. DST_ADDR_HI [7:0]
1606
 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1607
 */
1608
#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
5078 serge 1609
                /* 0 - DST_ADDR
3192 Serge 1610
		 * 1 - GDS
1611
		 */
1612
#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
1613
                /* 0 - ME
1614
		 * 1 - PFP
1615
		 */
1616
#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
1617
                /* 0 - SRC_ADDR
1618
		 * 1 - GDS
1619
		 * 2 - DATA
1620
		 */
1621
#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
1622
/* COMMAND */
1623
#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
5078 serge 1624
#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
3192 Serge 1625
                /* 0 - none
1626
		 * 1 - 8 in 16
1627
		 * 2 - 8 in 32
1628
		 * 3 - 8 in 64
1629
		 */
1630
#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1631
                /* 0 - none
1632
		 * 1 - 8 in 16
1633
		 * 2 - 8 in 32
1634
		 * 3 - 8 in 64
1635
		 */
1636
#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
1637
                /* 0 - memory
1638
		 * 1 - register
1639
		 */
1640
#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
1641
                /* 0 - memory
1642
		 * 1 - register
1643
		 */
1644
#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
1645
#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
1646
#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
2997 Serge 1647
#define	PACKET3_PFP_SYNC_ME				0x42
1648
#define	PACKET3_SURFACE_SYNC				0x43
1649
#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
1650
#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
1651
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
1652
#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
1653
#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
1654
#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
1655
#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
1656
#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
1657
#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
1658
#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
1659
#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
1660
#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
1661
#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
1662
#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
1663
#              define PACKET3_TC_ACTION_ENA        (1 << 23)
1664
#              define PACKET3_CB_ACTION_ENA        (1 << 25)
1665
#              define PACKET3_DB_ACTION_ENA        (1 << 26)
1666
#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1667
#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1668
#define	PACKET3_ME_INITIALIZE				0x44
1669
#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1670
#define	PACKET3_COND_WRITE				0x45
1671
#define	PACKET3_EVENT_WRITE				0x46
1672
#define		EVENT_TYPE(x)                           ((x) << 0)
1673
#define		EVENT_INDEX(x)                          ((x) << 8)
1674
                /* 0 - any non-TS event
1675
		 * 1 - ZPASS_DONE
1676
		 * 2 - SAMPLE_PIPELINESTAT
1677
		 * 3 - SAMPLE_STREAMOUTSTAT*
1678
		 * 4 - *S_PARTIAL_FLUSH
1679
		 * 5 - EOP events
1680
		 * 6 - EOS events
1681
		 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1682
		 */
1683
#define		INV_L2                                  (1 << 20)
1684
                /* INV TC L2 cache when EVENT_INDEX = 7 */
1685
#define	PACKET3_EVENT_WRITE_EOP				0x47
1686
#define		DATA_SEL(x)                             ((x) << 29)
1687
                /* 0 - discard
1688
		 * 1 - send low 32bit data
1689
		 * 2 - send 64bit data
1690
		 * 3 - send 64bit counter value
1691
		 */
1692
#define		INT_SEL(x)                              ((x) << 24)
1693
                /* 0 - none
1694
		 * 1 - interrupt only (DATA_SEL = 0)
1695
		 * 2 - interrupt when data write is confirmed
1696
		 */
1697
#define	PACKET3_EVENT_WRITE_EOS				0x48
1698
#define	PACKET3_PREAMBLE_CNTL				0x4A
1699
#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
1700
#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
1701
#define	PACKET3_ONE_REG_WRITE				0x57
1702
#define	PACKET3_LOAD_CONFIG_REG				0x5F
1703
#define	PACKET3_LOAD_CONTEXT_REG			0x60
1704
#define	PACKET3_LOAD_SH_REG				0x61
1705
#define	PACKET3_SET_CONFIG_REG				0x68
1706
#define		PACKET3_SET_CONFIG_REG_START			0x00008000
1707
#define		PACKET3_SET_CONFIG_REG_END			0x0000b000
1708
#define	PACKET3_SET_CONTEXT_REG				0x69
1709
#define		PACKET3_SET_CONTEXT_REG_START			0x00028000
1710
#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
1711
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
1712
#define	PACKET3_SET_RESOURCE_INDIRECT			0x74
1713
#define	PACKET3_SET_SH_REG				0x76
1714
#define		PACKET3_SET_SH_REG_START			0x0000b000
1715
#define		PACKET3_SET_SH_REG_END				0x0000c000
1716
#define	PACKET3_SET_SH_REG_OFFSET			0x77
1717
#define	PACKET3_ME_WRITE				0x7A
1718
#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
1719
#define	PACKET3_SCRATCH_RAM_READ			0x7E
1720
#define	PACKET3_CE_WRITE				0x7F
1721
#define	PACKET3_LOAD_CONST_RAM				0x80
1722
#define	PACKET3_WRITE_CONST_RAM				0x81
1723
#define	PACKET3_WRITE_CONST_RAM_OFFSET			0x82
1724
#define	PACKET3_DUMP_CONST_RAM				0x83
1725
#define	PACKET3_INCREMENT_CE_COUNTER			0x84
1726
#define	PACKET3_INCREMENT_DE_COUNTER			0x85
1727
#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
1728
#define	PACKET3_WAIT_ON_DE_COUNTER			0x87
1729
#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
1730
#define	PACKET3_SET_CE_DE_COUNTERS			0x89
1731
#define	PACKET3_WAIT_ON_AVAIL_BUFFER			0x8A
1732
#define	PACKET3_SWITCH_BUFFER				0x8B
1733
 
3192 Serge 1734
/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1735
#define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
1736
#define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
1737
 
1738
#define DMA_RB_CNTL                                       0xd000
1739
#       define DMA_RB_ENABLE                              (1 << 0)
1740
#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
1741
#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
1742
#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
1743
#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
1744
#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
1745
#define DMA_RB_BASE                                       0xd004
1746
#define DMA_RB_RPTR                                       0xd008
1747
#define DMA_RB_WPTR                                       0xd00c
1748
 
1749
#define DMA_RB_RPTR_ADDR_HI                               0xd01c
1750
#define DMA_RB_RPTR_ADDR_LO                               0xd020
1751
 
1752
#define DMA_IB_CNTL                                       0xd024
1753
#       define DMA_IB_ENABLE                              (1 << 0)
1754
#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
1755
#define DMA_IB_RPTR                                       0xd028
1756
#define DMA_CNTL                                          0xd02c
1757
#       define TRAP_ENABLE                                (1 << 0)
1758
#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
1759
#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
1760
#       define DATA_SWAP_ENABLE                           (1 << 3)
1761
#       define FENCE_SWAP_ENABLE                          (1 << 4)
1762
#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
1763
#define DMA_STATUS_REG                                    0xd034
1764
#       define DMA_IDLE                                   (1 << 0)
1765
#define DMA_TILING_CONFIG  				  0xd0b8
1766
 
5078 serge 1767
#define	DMA_POWER_CNTL					0xd0bc
1768
#       define MEM_POWER_OVERRIDE                       (1 << 8)
1769
#define	DMA_CLK_CTRL					0xd0c0
1770
 
1771
#define	DMA_PG						0xd0d4
1772
#	define PG_CNTL_ENABLE				(1 << 0)
1773
#define	DMA_PGFSM_CONFIG				0xd0d8
1774
#define	DMA_PGFSM_WRITE					0xd0dc
1775
 
3192 Serge 1776
#define DMA_PACKET(cmd, b, t, s, n)	((((cmd) & 0xF) << 28) |	\
1777
					 (((b) & 0x1) << 26) |		\
1778
					 (((t) & 0x1) << 23) |		\
1779
					 (((s) & 0x1) << 22) |		\
1780
					 (((n) & 0xFFFFF) << 0))
1781
 
1782
#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
1783
					 (((vmid) & 0xF) << 20) |	\
1784
					 (((n) & 0xFFFFF) << 0))
1785
 
1786
#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
1787
					 (1 << 26) |			\
1788
					 (1 << 21) |			\
1789
					 (((n) & 0xFFFFF) << 0))
1790
 
1791
/* async DMA Packet types */
1792
#define	DMA_PACKET_WRITE				  0x2
1793
#define	DMA_PACKET_COPY					  0x3
1794
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
1795
#define	DMA_PACKET_SEMAPHORE				  0x5
1796
#define	DMA_PACKET_FENCE				  0x6
1797
#define	DMA_PACKET_TRAP					  0x7
1798
#define	DMA_PACKET_SRBM_WRITE				  0x9
1799
#define	DMA_PACKET_CONSTANT_FILL			  0xd
1800
#define	DMA_PACKET_NOP					  0xf
1801
 
5078 serge 1802
#define VCE_STATUS					0x20004
1803
#define VCE_VCPU_CNTL					0x20014
1804
#define		VCE_CLK_EN				(1 << 0)
1805
#define VCE_VCPU_CACHE_OFFSET0				0x20024
1806
#define VCE_VCPU_CACHE_SIZE0				0x20028
1807
#define VCE_VCPU_CACHE_OFFSET1				0x2002c
1808
#define VCE_VCPU_CACHE_SIZE1				0x20030
1809
#define VCE_VCPU_CACHE_OFFSET2				0x20034
1810
#define VCE_VCPU_CACHE_SIZE2				0x20038
1811
#define VCE_SOFT_RESET					0x20120
1812
#define 	VCE_ECPU_SOFT_RESET			(1 << 0)
1813
#define 	VCE_FME_SOFT_RESET			(1 << 2)
1814
#define VCE_RB_BASE_LO2					0x2016c
1815
#define VCE_RB_BASE_HI2					0x20170
1816
#define VCE_RB_SIZE2					0x20174
1817
#define VCE_RB_RPTR2					0x20178
1818
#define VCE_RB_WPTR2					0x2017c
1819
#define VCE_RB_BASE_LO					0x20180
1820
#define VCE_RB_BASE_HI					0x20184
1821
#define VCE_RB_SIZE					0x20188
1822
#define VCE_RB_RPTR					0x2018c
1823
#define VCE_RB_WPTR					0x20190
1824
#define VCE_CLOCK_GATING_A				0x202f8
1825
#define VCE_CLOCK_GATING_B				0x202fc
1826
#define VCE_UENC_CLOCK_GATING				0x205bc
1827
#define VCE_UENC_REG_CLOCK_GATING			0x205c0
1828
#define VCE_FW_REG_STATUS				0x20e10
1829
#	define VCE_FW_REG_STATUS_BUSY			(1 << 0)
1830
#	define VCE_FW_REG_STATUS_PASS			(1 << 3)
1831
#	define VCE_FW_REG_STATUS_DONE			(1 << 11)
1832
#define VCE_LMI_FW_START_KEYSEL				0x20e18
1833
#define VCE_LMI_FW_PERIODIC_CTRL			0x20e20
1834
#define VCE_LMI_CTRL2					0x20e74
1835
#define VCE_LMI_CTRL					0x20e98
1836
#define VCE_LMI_VM_CTRL					0x20ea0
1837
#define VCE_LMI_SWAP_CNTL				0x20eb4
1838
#define VCE_LMI_SWAP_CNTL1				0x20eb8
1839
#define VCE_LMI_CACHE_CTRL				0x20ef4
1840
 
1841
#define VCE_CMD_NO_OP					0x00000000
1842
#define VCE_CMD_END					0x00000001
1843
#define VCE_CMD_IB					0x00000002
1844
#define VCE_CMD_FENCE					0x00000003
1845
#define VCE_CMD_TRAP					0x00000004
1846
#define VCE_CMD_IB_AUTO					0x00000005
1847
#define VCE_CMD_SEMAPHORE				0x00000006
1848
 
2997 Serge 1849
#endif