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2997 Serge 1
/*
2
 * Copyright 2011 Advanced Micro Devices, Inc.
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice shall be included in
12
 * all copies or substantial portions of the Software.
13
 *
14
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
 * OTHER DEALINGS IN THE SOFTWARE.
21
 *
22
 * Authors: Alex Deucher
23
 */
24
#ifndef SI_H
25
#define SI_H
26
 
27
#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
28
 
29
#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
30
#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
31
 
32
#define	CG_MULT_THERMAL_STATUS					0x714
33
#define		ASIC_MAX_TEMP(x)				((x) << 0)
34
#define		ASIC_MAX_TEMP_MASK				0x000001ff
35
#define		ASIC_MAX_TEMP_SHIFT				0
36
#define		CTF_TEMP(x)					((x) << 9)
37
#define		CTF_TEMP_MASK					0x0003fe00
38
#define		CTF_TEMP_SHIFT					9
39
 
40
#define SI_MAX_SH_GPRS           256
41
#define SI_MAX_TEMP_GPRS         16
42
#define SI_MAX_SH_THREADS        256
43
#define SI_MAX_SH_STACK_ENTRIES  4096
44
#define SI_MAX_FRC_EOV_CNT       16384
45
#define SI_MAX_BACKENDS          8
46
#define SI_MAX_BACKENDS_MASK     0xFF
47
#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
48
#define SI_MAX_SIMDS             12
49
#define SI_MAX_SIMDS_MASK        0x0FFF
50
#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
51
#define SI_MAX_PIPES             8
52
#define SI_MAX_PIPES_MASK        0xFF
53
#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
54
#define SI_MAX_LDS_NUM           0xFFFF
55
#define SI_MAX_TCC               16
56
#define SI_MAX_TCC_MASK          0xFFFF
57
 
58
#define VGA_HDP_CONTROL  				0x328
59
#define		VGA_MEMORY_DISABLE				(1 << 4)
60
 
61
#define DMIF_ADDR_CONFIG  				0xBD4
62
 
63
#define	SRBM_STATUS				        0xE50
64
 
3192 Serge 65
#define	SRBM_SOFT_RESET				        0x0E60
66
#define		SOFT_RESET_BIF				(1 << 1)
67
#define		SOFT_RESET_DC				(1 << 5)
68
#define		SOFT_RESET_DMA1				(1 << 6)
69
#define		SOFT_RESET_GRBM				(1 << 8)
70
#define		SOFT_RESET_HDP				(1 << 9)
71
#define		SOFT_RESET_IH				(1 << 10)
72
#define		SOFT_RESET_MC				(1 << 11)
73
#define		SOFT_RESET_ROM				(1 << 14)
74
#define		SOFT_RESET_SEM				(1 << 15)
75
#define		SOFT_RESET_VMC				(1 << 17)
76
#define		SOFT_RESET_DMA				(1 << 20)
77
#define		SOFT_RESET_TST				(1 << 21)
78
#define		SOFT_RESET_REGBB			(1 << 22)
79
#define		SOFT_RESET_ORB				(1 << 23)
80
 
2997 Serge 81
#define	CC_SYS_RB_BACKEND_DISABLE			0xe80
82
#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84
83
 
84
#define VM_L2_CNTL					0x1400
85
#define		ENABLE_L2_CACHE					(1 << 0)
86
#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
87
#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)
88
#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)
89
#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
90
#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
91
#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)
92
#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)
93
#define VM_L2_CNTL2					0x1404
94
#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
95
#define		INVALIDATE_L2_CACHE				(1 << 1)
96
#define		INVALIDATE_CACHE_MODE(x)			((x) << 26)
97
#define			INVALIDATE_PTE_AND_PDE_CACHES		0
98
#define			INVALIDATE_ONLY_PTE_CACHES		1
99
#define			INVALIDATE_ONLY_PDE_CACHES		2
100
#define VM_L2_CNTL3					0x1408
101
#define		BANK_SELECT(x)					((x) << 0)
102
#define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)
103
#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
104
#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
105
#define	VM_L2_STATUS					0x140C
106
#define		L2_BUSY						(1 << 0)
107
#define VM_CONTEXT0_CNTL				0x1410
108
#define		ENABLE_CONTEXT					(1 << 0)
109
#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
3192 Serge 110
#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
2997 Serge 111
#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
3192 Serge 112
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
113
#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
114
#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
115
#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
116
#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
117
#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
118
#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
119
#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
120
#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
121
#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
2997 Serge 122
#define VM_CONTEXT1_CNTL				0x1414
123
#define VM_CONTEXT0_CNTL2				0x1430
124
#define VM_CONTEXT1_CNTL2				0x1434
125
#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x1438
126
#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x143c
127
#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x1440
128
#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x1444
129
#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x1448
130
#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x144c
131
#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x1450
132
#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x1454
133
 
3192 Serge 134
#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC
135
#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
136
 
2997 Serge 137
#define VM_INVALIDATE_REQUEST				0x1478
138
#define VM_INVALIDATE_RESPONSE				0x147c
139
 
140
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
141
#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c
142
 
143
#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153c
144
#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x1540
145
#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x1544
146
#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x1548
147
#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x154c
148
#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x1550
149
#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x1554
150
#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x1558
151
#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155c
152
#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x1560
153
 
154
#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
155
#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x1580
156
 
157
#define MC_SHARED_CHMAP						0x2004
158
#define		NOOFCHAN_SHIFT					12
159
#define		NOOFCHAN_MASK					0x0000f000
160
#define MC_SHARED_CHREMAP					0x2008
161
 
162
#define	MC_VM_FB_LOCATION				0x2024
163
#define	MC_VM_AGP_TOP					0x2028
164
#define	MC_VM_AGP_BOT					0x202C
165
#define	MC_VM_AGP_BASE					0x2030
166
#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
167
#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
168
#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
169
 
170
#define	MC_VM_MX_L1_TLB_CNTL				0x2064
171
#define		ENABLE_L1_TLB					(1 << 0)
172
#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
173
#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
174
#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
175
#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
176
#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
177
#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
178
#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
179
 
180
#define MC_SHARED_BLACKOUT_CNTL           		0x20ac
181
 
182
#define	MC_ARB_RAMCFG					0x2760
183
#define		NOOFBANK_SHIFT					0
184
#define		NOOFBANK_MASK					0x00000003
185
#define		NOOFRANK_SHIFT					2
186
#define		NOOFRANK_MASK					0x00000004
187
#define		NOOFROWS_SHIFT					3
188
#define		NOOFROWS_MASK					0x00000038
189
#define		NOOFCOLS_SHIFT					6
190
#define		NOOFCOLS_MASK					0x000000C0
191
#define		CHANSIZE_SHIFT					8
192
#define		CHANSIZE_MASK					0x00000100
193
#define		CHANSIZE_OVERRIDE				(1 << 11)
194
#define		NOOFGROUPS_SHIFT				12
195
#define		NOOFGROUPS_MASK					0x00001000
196
 
197
#define	MC_SEQ_TRAIN_WAKEUP_CNTL			0x2808
198
#define		TRAIN_DONE_D0      			(1 << 30)
199
#define		TRAIN_DONE_D1      			(1 << 31)
200
 
201
#define MC_SEQ_SUP_CNTL           			0x28c8
202
#define		RUN_MASK      				(1 << 0)
203
#define MC_SEQ_SUP_PGM           			0x28cc
204
 
205
#define MC_IO_PAD_CNTL_D0           			0x29d0
206
#define		MEM_FALL_OUT_CMD      			(1 << 8)
207
 
208
#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44
209
#define MC_SEQ_IO_DEBUG_DATA           			0x2a48
210
 
211
#define	HDP_HOST_PATH_CNTL				0x2C00
212
#define	HDP_NONSURFACE_BASE				0x2C04
213
#define	HDP_NONSURFACE_INFO				0x2C08
214
#define	HDP_NONSURFACE_SIZE				0x2C0C
215
 
216
#define HDP_ADDR_CONFIG  				0x2F48
217
#define HDP_MISC_CNTL					0x2F4C
218
#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
219
 
220
#define IH_RB_CNTL                                        0x3e00
221
#       define IH_RB_ENABLE                               (1 << 0)
222
#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
223
#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
224
#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
225
#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
226
#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
227
#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
228
#define IH_RB_BASE                                        0x3e04
229
#define IH_RB_RPTR                                        0x3e08
230
#define IH_RB_WPTR                                        0x3e0c
231
#       define RB_OVERFLOW                                (1 << 0)
232
#       define WPTR_OFFSET_MASK                           0x3fffc
233
#define IH_RB_WPTR_ADDR_HI                                0x3e10
234
#define IH_RB_WPTR_ADDR_LO                                0x3e14
235
#define IH_CNTL                                           0x3e18
236
#       define ENABLE_INTR                                (1 << 0)
237
#       define IH_MC_SWAP(x)                              ((x) << 1)
238
#       define IH_MC_SWAP_NONE                            0
239
#       define IH_MC_SWAP_16BIT                           1
240
#       define IH_MC_SWAP_32BIT                           2
241
#       define IH_MC_SWAP_64BIT                           3
242
#       define RPTR_REARM                                 (1 << 4)
243
#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
244
#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
245
#       define MC_VMID(x)                                 ((x) << 25)
246
 
247
#define	CONFIG_MEMSIZE					0x5428
248
 
249
#define INTERRUPT_CNTL                                    0x5468
250
#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
251
#       define IH_DUMMY_RD_EN                             (1 << 1)
252
#       define IH_REQ_NONSNOOP_EN                         (1 << 3)
253
#       define GEN_IH_INT_EN                              (1 << 8)
254
#define INTERRUPT_CNTL2                                   0x546c
255
 
256
#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
257
 
258
#define	BIF_FB_EN						0x5490
259
#define		FB_READ_EN					(1 << 0)
260
#define		FB_WRITE_EN					(1 << 1)
261
 
262
#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
263
 
264
#define	DC_LB_MEMORY_SPLIT					0x6b0c
265
#define		DC_LB_MEMORY_CONFIG(x)				((x) << 20)
266
 
267
#define	PRIORITY_A_CNT						0x6b18
268
#define		PRIORITY_MARK_MASK				0x7fff
269
#define		PRIORITY_OFF					(1 << 16)
270
#define		PRIORITY_ALWAYS_ON				(1 << 20)
271
#define	PRIORITY_B_CNT						0x6b1c
272
 
273
#define	DPG_PIPE_ARBITRATION_CONTROL3				0x6cc8
274
#       define LATENCY_WATERMARK_MASK(x)			((x) << 16)
275
#define	DPG_PIPE_LATENCY_CONTROL				0x6ccc
276
#       define LATENCY_LOW_WATERMARK(x)				((x) << 0)
277
#       define LATENCY_HIGH_WATERMARK(x)			((x) << 16)
278
 
279
/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
280
#define VLINE_STATUS                                    0x6bb8
281
#       define VLINE_OCCURRED                           (1 << 0)
282
#       define VLINE_ACK                                (1 << 4)
283
#       define VLINE_STAT                               (1 << 12)
284
#       define VLINE_INTERRUPT                          (1 << 16)
285
#       define VLINE_INTERRUPT_TYPE                     (1 << 17)
286
/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
287
#define VBLANK_STATUS                                   0x6bbc
288
#       define VBLANK_OCCURRED                          (1 << 0)
289
#       define VBLANK_ACK                               (1 << 4)
290
#       define VBLANK_STAT                              (1 << 12)
291
#       define VBLANK_INTERRUPT                         (1 << 16)
292
#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
293
 
294
/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
295
#define INT_MASK                                        0x6b40
296
#       define VBLANK_INT_MASK                          (1 << 0)
297
#       define VLINE_INT_MASK                           (1 << 4)
298
 
299
#define DISP_INTERRUPT_STATUS                           0x60f4
300
#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
301
#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
302
#       define DC_HPD1_INTERRUPT                        (1 << 17)
303
#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
304
#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
305
#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
306
#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
307
#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
308
#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
309
#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
310
#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
311
#       define DC_HPD2_INTERRUPT                        (1 << 17)
312
#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
313
#       define DISP_TIMER_INTERRUPT                     (1 << 24)
314
#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
315
#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
316
#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
317
#       define DC_HPD3_INTERRUPT                        (1 << 17)
318
#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
319
#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
320
#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
321
#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
322
#       define DC_HPD4_INTERRUPT                        (1 << 17)
323
#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
324
#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
325
#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
326
#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
327
#       define DC_HPD5_INTERRUPT                        (1 << 17)
328
#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
329
#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
330
#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
331
#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
332
#       define DC_HPD6_INTERRUPT                        (1 << 17)
333
#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
334
 
335
/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
336
#define GRPH_INT_STATUS                                 0x6858
337
#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
338
#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
339
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
340
#define	GRPH_INT_CONTROL			        0x685c
341
#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
342
#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
343
 
344
#define	DACA_AUTODETECT_INT_CONTROL			0x66c8
345
 
346
#define DC_HPD1_INT_STATUS                              0x601c
347
#define DC_HPD2_INT_STATUS                              0x6028
348
#define DC_HPD3_INT_STATUS                              0x6034
349
#define DC_HPD4_INT_STATUS                              0x6040
350
#define DC_HPD5_INT_STATUS                              0x604c
351
#define DC_HPD6_INT_STATUS                              0x6058
352
#       define DC_HPDx_INT_STATUS                       (1 << 0)
353
#       define DC_HPDx_SENSE                            (1 << 1)
354
#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
355
 
356
#define DC_HPD1_INT_CONTROL                             0x6020
357
#define DC_HPD2_INT_CONTROL                             0x602c
358
#define DC_HPD3_INT_CONTROL                             0x6038
359
#define DC_HPD4_INT_CONTROL                             0x6044
360
#define DC_HPD5_INT_CONTROL                             0x6050
361
#define DC_HPD6_INT_CONTROL                             0x605c
362
#       define DC_HPDx_INT_ACK                          (1 << 0)
363
#       define DC_HPDx_INT_POLARITY                     (1 << 8)
364
#       define DC_HPDx_INT_EN                           (1 << 16)
365
#       define DC_HPDx_RX_INT_ACK                       (1 << 20)
366
#       define DC_HPDx_RX_INT_EN                        (1 << 24)
367
 
368
#define DC_HPD1_CONTROL                                   0x6024
369
#define DC_HPD2_CONTROL                                   0x6030
370
#define DC_HPD3_CONTROL                                   0x603c
371
#define DC_HPD4_CONTROL                                   0x6048
372
#define DC_HPD5_CONTROL                                   0x6054
373
#define DC_HPD6_CONTROL                                   0x6060
374
#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
375
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
376
#       define DC_HPDx_EN                                 (1 << 28)
377
 
378
/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
379
#define CRTC_STATUS_FRAME_COUNT                         0x6e98
380
 
381
#define	GRBM_CNTL					0x8000
382
#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
383
 
384
#define	GRBM_STATUS2					0x8008
385
#define		RLC_RQ_PENDING 					(1 << 0)
386
#define		RLC_BUSY 					(1 << 8)
387
#define		TC_BUSY 					(1 << 9)
388
 
389
#define	GRBM_STATUS					0x8010
390
#define		CMDFIFO_AVAIL_MASK				0x0000000F
391
#define		RING2_RQ_PENDING				(1 << 4)
392
#define		SRBM_RQ_PENDING					(1 << 5)
393
#define		RING1_RQ_PENDING				(1 << 6)
394
#define		CF_RQ_PENDING					(1 << 7)
395
#define		PF_RQ_PENDING					(1 << 8)
396
#define		GDS_DMA_RQ_PENDING				(1 << 9)
397
#define		GRBM_EE_BUSY					(1 << 10)
398
#define		DB_CLEAN					(1 << 12)
399
#define		CB_CLEAN					(1 << 13)
400
#define		TA_BUSY 					(1 << 14)
401
#define		GDS_BUSY 					(1 << 15)
402
#define		VGT_BUSY					(1 << 17)
403
#define		IA_BUSY_NO_DMA					(1 << 18)
404
#define		IA_BUSY						(1 << 19)
405
#define		SX_BUSY 					(1 << 20)
406
#define		SPI_BUSY					(1 << 22)
407
#define		BCI_BUSY					(1 << 23)
408
#define		SC_BUSY 					(1 << 24)
409
#define		PA_BUSY 					(1 << 25)
410
#define		DB_BUSY 					(1 << 26)
411
#define		CP_COHERENCY_BUSY      				(1 << 28)
412
#define		CP_BUSY 					(1 << 29)
413
#define		CB_BUSY 					(1 << 30)
414
#define		GUI_ACTIVE					(1 << 31)
415
#define	GRBM_STATUS_SE0					0x8014
416
#define	GRBM_STATUS_SE1					0x8018
417
#define		SE_DB_CLEAN					(1 << 1)
418
#define		SE_CB_CLEAN					(1 << 2)
419
#define		SE_BCI_BUSY					(1 << 22)
420
#define		SE_VGT_BUSY					(1 << 23)
421
#define		SE_PA_BUSY					(1 << 24)
422
#define		SE_TA_BUSY					(1 << 25)
423
#define		SE_SX_BUSY					(1 << 26)
424
#define		SE_SPI_BUSY					(1 << 27)
425
#define		SE_SC_BUSY					(1 << 29)
426
#define		SE_DB_BUSY					(1 << 30)
427
#define		SE_CB_BUSY					(1 << 31)
428
 
429
#define	GRBM_SOFT_RESET					0x8020
430
#define		SOFT_RESET_CP					(1 << 0)
431
#define		SOFT_RESET_CB					(1 << 1)
432
#define		SOFT_RESET_RLC					(1 << 2)
433
#define		SOFT_RESET_DB					(1 << 3)
434
#define		SOFT_RESET_GDS					(1 << 4)
435
#define		SOFT_RESET_PA					(1 << 5)
436
#define		SOFT_RESET_SC					(1 << 6)
437
#define		SOFT_RESET_BCI					(1 << 7)
438
#define		SOFT_RESET_SPI					(1 << 8)
439
#define		SOFT_RESET_SX					(1 << 10)
440
#define		SOFT_RESET_TC					(1 << 11)
441
#define		SOFT_RESET_TA					(1 << 12)
442
#define		SOFT_RESET_VGT					(1 << 14)
443
#define		SOFT_RESET_IA					(1 << 15)
444
 
445
#define GRBM_GFX_INDEX          			0x802C
446
#define		INSTANCE_INDEX(x)			((x) << 0)
447
#define		SH_INDEX(x)     			((x) << 8)
448
#define		SE_INDEX(x)     			((x) << 16)
449
#define		SH_BROADCAST_WRITES      		(1 << 29)
450
#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
451
#define		SE_BROADCAST_WRITES      		(1 << 31)
452
 
453
#define GRBM_INT_CNTL                                   0x8060
454
#       define RDERR_INT_ENABLE                         (1 << 0)
455
#       define GUI_IDLE_INT_ENABLE                      (1 << 19)
456
 
3031 serge 457
#define	CP_STRMOUT_CNTL					0x84FC
2997 Serge 458
#define	SCRATCH_REG0					0x8500
459
#define	SCRATCH_REG1					0x8504
460
#define	SCRATCH_REG2					0x8508
461
#define	SCRATCH_REG3					0x850C
462
#define	SCRATCH_REG4					0x8510
463
#define	SCRATCH_REG5					0x8514
464
#define	SCRATCH_REG6					0x8518
465
#define	SCRATCH_REG7					0x851C
466
 
467
#define	SCRATCH_UMSK					0x8540
468
#define	SCRATCH_ADDR					0x8544
469
 
470
#define	CP_SEM_WAIT_TIMER				0x85BC
471
 
472
#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8
473
 
474
#define CP_ME_CNTL					0x86D8
475
#define		CP_CE_HALT					(1 << 24)
476
#define		CP_PFP_HALT					(1 << 26)
477
#define		CP_ME_HALT					(1 << 28)
478
 
479
#define	CP_COHER_CNTL2					0x85E8
480
 
481
#define	CP_RB2_RPTR					0x86f8
482
#define	CP_RB1_RPTR					0x86fc
483
#define	CP_RB0_RPTR					0x8700
484
#define	CP_RB_WPTR_DELAY				0x8704
485
 
486
#define	CP_QUEUE_THRESHOLDS				0x8760
487
#define		ROQ_IB1_START(x)				((x) << 0)
488
#define		ROQ_IB2_START(x)				((x) << 8)
489
#define CP_MEQ_THRESHOLDS				0x8764
490
#define		MEQ1_START(x)				((x) << 0)
491
#define		MEQ2_START(x)				((x) << 8)
492
 
493
#define	CP_PERFMON_CNTL					0x87FC
494
 
495
#define	VGT_VTX_VECT_EJECT_REG				0x88B0
496
 
497
#define	VGT_CACHE_INVALIDATION				0x88C4
498
#define		CACHE_INVALIDATION(x)				((x) << 0)
499
#define			VC_ONLY						0
500
#define			TC_ONLY						1
501
#define			VC_AND_TC					2
502
#define		AUTO_INVLD_EN(x)				((x) << 6)
503
#define			NO_AUTO						0
504
#define			ES_AUTO						1
505
#define			GS_AUTO						2
506
#define			ES_AND_GS_AUTO					3
507
#define	VGT_ESGS_RING_SIZE				0x88C8
508
#define	VGT_GSVS_RING_SIZE				0x88CC
509
 
510
#define	VGT_GS_VERTEX_REUSE				0x88D4
511
 
512
#define	VGT_PRIMITIVE_TYPE				0x8958
513
#define	VGT_INDEX_TYPE					0x895C
514
 
515
#define	VGT_NUM_INDICES					0x8970
516
#define	VGT_NUM_INSTANCES				0x8974
517
 
518
#define	VGT_TF_RING_SIZE				0x8988
519
 
520
#define	VGT_HS_OFFCHIP_PARAM				0x89B0
521
 
522
#define	VGT_TF_MEMORY_BASE				0x89B8
523
 
524
#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc
525
#define		INACTIVE_CUS_MASK			0xFFFF0000
526
#define		INACTIVE_CUS_SHIFT			16
527
#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0
528
 
529
#define	PA_CL_ENHANCE					0x8A14
530
#define		CLIP_VTX_REORDER_ENA				(1 << 0)
531
#define		NUM_CLIP_SEQ(x)					((x) << 1)
532
 
533
#define	PA_SU_LINE_STIPPLE_VALUE			0x8A60
534
 
535
#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
536
 
537
#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
538
#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
539
#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
540
 
541
#define	PA_SC_FIFO_SIZE					0x8BCC
542
#define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) << 0)
543
#define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) << 6)
544
#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 15)
545
#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 23)
546
 
547
#define	PA_SC_ENHANCE					0x8BF0
548
 
549
#define	SQ_CONFIG					0x8C00
550
 
551
#define	SQC_CACHES					0x8C08
552
 
553
#define	SX_DEBUG_1					0x9060
554
 
555
#define	SPI_STATIC_THREAD_MGMT_1			0x90E0
556
#define	SPI_STATIC_THREAD_MGMT_2			0x90E4
557
#define	SPI_STATIC_THREAD_MGMT_3			0x90E8
558
#define	SPI_PS_MAX_WAVE_ID				0x90EC
559
 
560
#define	SPI_CONFIG_CNTL					0x9100
561
 
562
#define	SPI_CONFIG_CNTL_1				0x913C
563
#define		VTX_DONE_DELAY(x)				((x) << 0)
564
#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
565
 
566
#define	CGTS_TCC_DISABLE				0x9148
567
#define	CGTS_USER_TCC_DISABLE				0x914C
568
#define		TCC_DISABLE_MASK				0xFFFF0000
569
#define		TCC_DISABLE_SHIFT				16
570
 
571
#define	TA_CNTL_AUX					0x9508
572
 
573
#define CC_RB_BACKEND_DISABLE				0x98F4
574
#define		BACKEND_DISABLE(x)     			((x) << 16)
575
#define GB_ADDR_CONFIG  				0x98F8
576
#define		NUM_PIPES(x)				((x) << 0)
577
#define		NUM_PIPES_MASK				0x00000007
578
#define		NUM_PIPES_SHIFT				0
579
#define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
580
#define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
581
#define		PIPE_INTERLEAVE_SIZE_SHIFT		4
582
#define		NUM_SHADER_ENGINES(x)			((x) << 12)
583
#define		NUM_SHADER_ENGINES_MASK			0x00003000
584
#define		NUM_SHADER_ENGINES_SHIFT		12
585
#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
586
#define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
587
#define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
588
#define		NUM_GPUS(x)     			((x) << 20)
589
#define		NUM_GPUS_MASK				0x00700000
590
#define		NUM_GPUS_SHIFT				20
591
#define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)
592
#define		MULTI_GPU_TILE_SIZE_MASK		0x03000000
593
#define		MULTI_GPU_TILE_SIZE_SHIFT		24
594
#define		ROW_SIZE(x)             		((x) << 28)
595
#define		ROW_SIZE_MASK				0x30000000
596
#define		ROW_SIZE_SHIFT				28
597
 
598
#define	GB_TILE_MODE0					0x9910
599
#       define MICRO_TILE_MODE(x)				((x) << 0)
600
#              define	ADDR_SURF_DISPLAY_MICRO_TILING		0
601
#              define	ADDR_SURF_THIN_MICRO_TILING		1
602
#              define	ADDR_SURF_DEPTH_MICRO_TILING		2
603
#       define ARRAY_MODE(x)					((x) << 2)
604
#              define	ARRAY_LINEAR_GENERAL			0
605
#              define	ARRAY_LINEAR_ALIGNED			1
606
#              define	ARRAY_1D_TILED_THIN1			2
607
#              define	ARRAY_2D_TILED_THIN1			4
608
#       define PIPE_CONFIG(x)					((x) << 6)
609
#              define	ADDR_SURF_P2				0
610
#              define	ADDR_SURF_P4_8x16			4
611
#              define	ADDR_SURF_P4_16x16			5
612
#              define	ADDR_SURF_P4_16x32			6
613
#              define	ADDR_SURF_P4_32x32			7
614
#              define	ADDR_SURF_P8_16x16_8x16			8
615
#              define	ADDR_SURF_P8_16x32_8x16			9
616
#              define	ADDR_SURF_P8_32x32_8x16			10
617
#              define	ADDR_SURF_P8_16x32_16x16		11
618
#              define	ADDR_SURF_P8_32x32_16x16		12
619
#              define	ADDR_SURF_P8_32x32_16x32		13
620
#              define	ADDR_SURF_P8_32x64_32x32		14
621
#       define TILE_SPLIT(x)					((x) << 11)
622
#              define	ADDR_SURF_TILE_SPLIT_64B		0
623
#              define	ADDR_SURF_TILE_SPLIT_128B		1
624
#              define	ADDR_SURF_TILE_SPLIT_256B		2
625
#              define	ADDR_SURF_TILE_SPLIT_512B		3
626
#              define	ADDR_SURF_TILE_SPLIT_1KB		4
627
#              define	ADDR_SURF_TILE_SPLIT_2KB		5
628
#              define	ADDR_SURF_TILE_SPLIT_4KB		6
629
#       define BANK_WIDTH(x)					((x) << 14)
630
#              define	ADDR_SURF_BANK_WIDTH_1			0
631
#              define	ADDR_SURF_BANK_WIDTH_2			1
632
#              define	ADDR_SURF_BANK_WIDTH_4			2
633
#              define	ADDR_SURF_BANK_WIDTH_8			3
634
#       define BANK_HEIGHT(x)					((x) << 16)
635
#              define	ADDR_SURF_BANK_HEIGHT_1			0
636
#              define	ADDR_SURF_BANK_HEIGHT_2			1
637
#              define	ADDR_SURF_BANK_HEIGHT_4			2
638
#              define	ADDR_SURF_BANK_HEIGHT_8			3
639
#       define MACRO_TILE_ASPECT(x)				((x) << 18)
640
#              define	ADDR_SURF_MACRO_ASPECT_1		0
641
#              define	ADDR_SURF_MACRO_ASPECT_2		1
642
#              define	ADDR_SURF_MACRO_ASPECT_4		2
643
#              define	ADDR_SURF_MACRO_ASPECT_8		3
644
#       define NUM_BANKS(x)					((x) << 20)
645
#              define	ADDR_SURF_2_BANK			0
646
#              define	ADDR_SURF_4_BANK			1
647
#              define	ADDR_SURF_8_BANK			2
648
#              define	ADDR_SURF_16_BANK			3
649
 
650
#define	CB_PERFCOUNTER0_SELECT0				0x9a20
651
#define	CB_PERFCOUNTER0_SELECT1				0x9a24
652
#define	CB_PERFCOUNTER1_SELECT0				0x9a28
653
#define	CB_PERFCOUNTER1_SELECT1				0x9a2c
654
#define	CB_PERFCOUNTER2_SELECT0				0x9a30
655
#define	CB_PERFCOUNTER2_SELECT1				0x9a34
656
#define	CB_PERFCOUNTER3_SELECT0				0x9a38
657
#define	CB_PERFCOUNTER3_SELECT1				0x9a3c
658
 
659
#define	GC_USER_RB_BACKEND_DISABLE			0x9B7C
660
#define		BACKEND_DISABLE_MASK			0x00FF0000
661
#define		BACKEND_DISABLE_SHIFT			16
662
 
663
#define	TCP_CHAN_STEER_LO				0xac0c
664
#define	TCP_CHAN_STEER_HI				0xac10
665
 
666
#define	CP_RB0_BASE					0xC100
667
#define	CP_RB0_CNTL					0xC104
668
#define		RB_BUFSZ(x)					((x) << 0)
669
#define		RB_BLKSZ(x)					((x) << 8)
670
#define		BUF_SWAP_32BIT					(2 << 16)
671
#define		RB_NO_UPDATE					(1 << 27)
672
#define		RB_RPTR_WR_ENA					(1 << 31)
673
 
674
#define	CP_RB0_RPTR_ADDR				0xC10C
675
#define	CP_RB0_RPTR_ADDR_HI				0xC110
676
#define	CP_RB0_WPTR					0xC114
677
 
678
#define	CP_PFP_UCODE_ADDR				0xC150
679
#define	CP_PFP_UCODE_DATA				0xC154
680
#define	CP_ME_RAM_RADDR					0xC158
681
#define	CP_ME_RAM_WADDR					0xC15C
682
#define	CP_ME_RAM_DATA					0xC160
683
 
684
#define	CP_CE_UCODE_ADDR				0xC168
685
#define	CP_CE_UCODE_DATA				0xC16C
686
 
687
#define	CP_RB1_BASE					0xC180
688
#define	CP_RB1_CNTL					0xC184
689
#define	CP_RB1_RPTR_ADDR				0xC188
690
#define	CP_RB1_RPTR_ADDR_HI				0xC18C
691
#define	CP_RB1_WPTR					0xC190
692
#define	CP_RB2_BASE					0xC194
693
#define	CP_RB2_CNTL					0xC198
694
#define	CP_RB2_RPTR_ADDR				0xC19C
695
#define	CP_RB2_RPTR_ADDR_HI				0xC1A0
696
#define	CP_RB2_WPTR					0xC1A4
697
#define CP_INT_CNTL_RING0                               0xC1A8
698
#define CP_INT_CNTL_RING1                               0xC1AC
699
#define CP_INT_CNTL_RING2                               0xC1B0
700
#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
701
#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
702
#       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
703
#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
704
#       define CP_RINGID2_INT_ENABLE                    (1 << 29)
705
#       define CP_RINGID1_INT_ENABLE                    (1 << 30)
706
#       define CP_RINGID0_INT_ENABLE                    (1 << 31)
707
#define CP_INT_STATUS_RING0                             0xC1B4
708
#define CP_INT_STATUS_RING1                             0xC1B8
709
#define CP_INT_STATUS_RING2                             0xC1BC
710
#       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
711
#       define TIME_STAMP_INT_STAT                      (1 << 26)
712
#       define CP_RINGID2_INT_STAT                      (1 << 29)
713
#       define CP_RINGID1_INT_STAT                      (1 << 30)
714
#       define CP_RINGID0_INT_STAT                      (1 << 31)
715
 
716
#define	CP_DEBUG					0xC1FC
717
 
718
#define RLC_CNTL                                          0xC300
719
#       define RLC_ENABLE                                 (1 << 0)
720
#define RLC_RL_BASE                                       0xC304
721
#define RLC_RL_SIZE                                       0xC308
722
#define RLC_LB_CNTL                                       0xC30C
723
#define RLC_SAVE_AND_RESTORE_BASE                         0xC310
724
#define RLC_LB_CNTR_MAX                                   0xC314
725
#define RLC_LB_CNTR_INIT                                  0xC318
726
 
727
#define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320
728
 
729
#define RLC_UCODE_ADDR                                    0xC32C
730
#define RLC_UCODE_DATA                                    0xC330
731
 
732
#define RLC_GPU_CLOCK_COUNT_LSB                           0xC338
733
#define RLC_GPU_CLOCK_COUNT_MSB                           0xC33C
734
#define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC340
735
#define RLC_MC_CNTL                                       0xC344
736
#define RLC_UCODE_CNTL                                    0xC348
737
 
738
#define PA_SC_RASTER_CONFIG                             0x28350
739
#       define RASTER_CONFIG_RB_MAP_0                   0
740
#       define RASTER_CONFIG_RB_MAP_1                   1
741
#       define RASTER_CONFIG_RB_MAP_2                   2
742
#       define RASTER_CONFIG_RB_MAP_3                   3
743
 
744
#define VGT_EVENT_INITIATOR                             0x28a90
745
#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
746
#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
747
#       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
748
#       define CACHE_FLUSH_TS                           (4 << 0)
749
#       define CACHE_FLUSH                              (6 << 0)
750
#       define CS_PARTIAL_FLUSH                         (7 << 0)
751
#       define VGT_STREAMOUT_RESET                      (10 << 0)
752
#       define END_OF_PIPE_INCR_DE                      (11 << 0)
753
#       define END_OF_PIPE_IB_END                       (12 << 0)
754
#       define RST_PIX_CNT                              (13 << 0)
755
#       define VS_PARTIAL_FLUSH                         (15 << 0)
756
#       define PS_PARTIAL_FLUSH                         (16 << 0)
757
#       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
758
#       define ZPASS_DONE                               (21 << 0)
759
#       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
760
#       define PERFCOUNTER_START                        (23 << 0)
761
#       define PERFCOUNTER_STOP                         (24 << 0)
762
#       define PIPELINESTAT_START                       (25 << 0)
763
#       define PIPELINESTAT_STOP                        (26 << 0)
764
#       define PERFCOUNTER_SAMPLE                       (27 << 0)
765
#       define SAMPLE_PIPELINESTAT                      (30 << 0)
766
#       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
767
#       define RESET_VTX_CNT                            (33 << 0)
768
#       define VGT_FLUSH                                (36 << 0)
769
#       define BOTTOM_OF_PIPE_TS                        (40 << 0)
770
#       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
771
#       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
772
#       define FLUSH_AND_INV_DB_META                    (44 << 0)
773
#       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
774
#       define FLUSH_AND_INV_CB_META                    (46 << 0)
775
#       define CS_DONE                                  (47 << 0)
776
#       define PS_DONE                                  (48 << 0)
777
#       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
778
#       define THREAD_TRACE_START                       (51 << 0)
779
#       define THREAD_TRACE_STOP                        (52 << 0)
780
#       define THREAD_TRACE_FLUSH                       (54 << 0)
781
#       define THREAD_TRACE_FINISH                      (55 << 0)
782
 
783
/*
784
 * PM4
785
 */
786
#define	PACKET_TYPE0	0
787
#define	PACKET_TYPE1	1
788
#define	PACKET_TYPE2	2
789
#define	PACKET_TYPE3	3
790
 
791
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
792
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
793
#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
794
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
795
#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
796
			 (((reg) >> 2) & 0xFFFF) |			\
797
			 ((n) & 0x3FFF) << 16)
798
#define CP_PACKET2			0x80000000
799
#define		PACKET2_PAD_SHIFT		0
800
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
801
 
802
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
803
 
804
#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
805
			 (((op) & 0xFF) << 8) |				\
806
			 ((n) & 0x3FFF) << 16)
807
 
808
#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
809
 
810
/* Packet 3 types */
811
#define	PACKET3_NOP					0x10
812
#define	PACKET3_SET_BASE				0x11
813
#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
814
#define			GDS_PARTITION_BASE		2
815
#define			CE_PARTITION_BASE		3
816
#define	PACKET3_CLEAR_STATE				0x12
817
#define	PACKET3_INDEX_BUFFER_SIZE			0x13
818
#define	PACKET3_DISPATCH_DIRECT				0x15
819
#define	PACKET3_DISPATCH_INDIRECT			0x16
820
#define	PACKET3_ALLOC_GDS				0x1B
821
#define	PACKET3_WRITE_GDS_RAM				0x1C
822
#define	PACKET3_ATOMIC_GDS				0x1D
823
#define	PACKET3_ATOMIC					0x1E
824
#define	PACKET3_OCCLUSION_QUERY				0x1F
825
#define	PACKET3_SET_PREDICATION				0x20
826
#define	PACKET3_REG_RMW					0x21
827
#define	PACKET3_COND_EXEC				0x22
828
#define	PACKET3_PRED_EXEC				0x23
829
#define	PACKET3_DRAW_INDIRECT				0x24
830
#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
831
#define	PACKET3_INDEX_BASE				0x26
832
#define	PACKET3_DRAW_INDEX_2				0x27
833
#define	PACKET3_CONTEXT_CONTROL				0x28
834
#define	PACKET3_INDEX_TYPE				0x2A
835
#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
836
#define	PACKET3_DRAW_INDEX_AUTO				0x2D
837
#define	PACKET3_DRAW_INDEX_IMMD				0x2E
838
#define	PACKET3_NUM_INSTANCES				0x2F
839
#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
840
#define	PACKET3_INDIRECT_BUFFER_CONST			0x31
841
#define	PACKET3_INDIRECT_BUFFER				0x32
842
#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
843
#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
844
#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
845
#define	PACKET3_WRITE_DATA				0x37
846
#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
847
                /* 0 - register
848
		 * 1 - memory (sync - via GRBM)
849
		 * 2 - tc/l2
850
		 * 3 - gds
851
		 * 4 - reserved
852
		 * 5 - memory (async - direct)
853
		 */
854
#define		WR_ONE_ADDR                             (1 << 16)
855
#define		WR_CONFIRM                              (1 << 20)
856
#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
857
                /* 0 - me
858
		 * 1 - pfp
859
		 * 2 - ce
860
		 */
861
#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
862
#define	PACKET3_MEM_SEMAPHORE				0x39
863
#define	PACKET3_MPEG_INDEX				0x3A
864
#define	PACKET3_COPY_DW					0x3B
865
#define	PACKET3_WAIT_REG_MEM				0x3C
866
#define	PACKET3_MEM_WRITE				0x3D
867
#define	PACKET3_COPY_DATA				0x40
3192 Serge 868
#define	PACKET3_CP_DMA					0x41
869
/* 1. header
870
 * 2. SRC_ADDR_LO or DATA [31:0]
871
 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
872
 *    SRC_ADDR_HI [7:0]
873
 * 4. DST_ADDR_LO [31:0]
874
 * 5. DST_ADDR_HI [7:0]
875
 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
876
 */
877
#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
878
                /* 0 - SRC_ADDR
879
		 * 1 - GDS
880
		 */
881
#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
882
                /* 0 - ME
883
		 * 1 - PFP
884
		 */
885
#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
886
                /* 0 - SRC_ADDR
887
		 * 1 - GDS
888
		 * 2 - DATA
889
		 */
890
#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
891
/* COMMAND */
892
#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
893
#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
894
                /* 0 - none
895
		 * 1 - 8 in 16
896
		 * 2 - 8 in 32
897
		 * 3 - 8 in 64
898
		 */
899
#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
900
                /* 0 - none
901
		 * 1 - 8 in 16
902
		 * 2 - 8 in 32
903
		 * 3 - 8 in 64
904
		 */
905
#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
906
                /* 0 - memory
907
		 * 1 - register
908
		 */
909
#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
910
                /* 0 - memory
911
		 * 1 - register
912
		 */
913
#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
914
#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
915
#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
2997 Serge 916
#define	PACKET3_PFP_SYNC_ME				0x42
917
#define	PACKET3_SURFACE_SYNC				0x43
918
#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
919
#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
920
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
921
#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
922
#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
923
#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
924
#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
925
#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
926
#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
927
#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
928
#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
929
#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
930
#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
931
#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
932
#              define PACKET3_TC_ACTION_ENA        (1 << 23)
933
#              define PACKET3_CB_ACTION_ENA        (1 << 25)
934
#              define PACKET3_DB_ACTION_ENA        (1 << 26)
935
#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
936
#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
937
#define	PACKET3_ME_INITIALIZE				0x44
938
#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
939
#define	PACKET3_COND_WRITE				0x45
940
#define	PACKET3_EVENT_WRITE				0x46
941
#define		EVENT_TYPE(x)                           ((x) << 0)
942
#define		EVENT_INDEX(x)                          ((x) << 8)
943
                /* 0 - any non-TS event
944
		 * 1 - ZPASS_DONE
945
		 * 2 - SAMPLE_PIPELINESTAT
946
		 * 3 - SAMPLE_STREAMOUTSTAT*
947
		 * 4 - *S_PARTIAL_FLUSH
948
		 * 5 - EOP events
949
		 * 6 - EOS events
950
		 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
951
		 */
952
#define		INV_L2                                  (1 << 20)
953
                /* INV TC L2 cache when EVENT_INDEX = 7 */
954
#define	PACKET3_EVENT_WRITE_EOP				0x47
955
#define		DATA_SEL(x)                             ((x) << 29)
956
                /* 0 - discard
957
		 * 1 - send low 32bit data
958
		 * 2 - send 64bit data
959
		 * 3 - send 64bit counter value
960
		 */
961
#define		INT_SEL(x)                              ((x) << 24)
962
                /* 0 - none
963
		 * 1 - interrupt only (DATA_SEL = 0)
964
		 * 2 - interrupt when data write is confirmed
965
		 */
966
#define	PACKET3_EVENT_WRITE_EOS				0x48
967
#define	PACKET3_PREAMBLE_CNTL				0x4A
968
#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
969
#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
970
#define	PACKET3_ONE_REG_WRITE				0x57
971
#define	PACKET3_LOAD_CONFIG_REG				0x5F
972
#define	PACKET3_LOAD_CONTEXT_REG			0x60
973
#define	PACKET3_LOAD_SH_REG				0x61
974
#define	PACKET3_SET_CONFIG_REG				0x68
975
#define		PACKET3_SET_CONFIG_REG_START			0x00008000
976
#define		PACKET3_SET_CONFIG_REG_END			0x0000b000
977
#define	PACKET3_SET_CONTEXT_REG				0x69
978
#define		PACKET3_SET_CONTEXT_REG_START			0x00028000
979
#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
980
#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
981
#define	PACKET3_SET_RESOURCE_INDIRECT			0x74
982
#define	PACKET3_SET_SH_REG				0x76
983
#define		PACKET3_SET_SH_REG_START			0x0000b000
984
#define		PACKET3_SET_SH_REG_END				0x0000c000
985
#define	PACKET3_SET_SH_REG_OFFSET			0x77
986
#define	PACKET3_ME_WRITE				0x7A
987
#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
988
#define	PACKET3_SCRATCH_RAM_READ			0x7E
989
#define	PACKET3_CE_WRITE				0x7F
990
#define	PACKET3_LOAD_CONST_RAM				0x80
991
#define	PACKET3_WRITE_CONST_RAM				0x81
992
#define	PACKET3_WRITE_CONST_RAM_OFFSET			0x82
993
#define	PACKET3_DUMP_CONST_RAM				0x83
994
#define	PACKET3_INCREMENT_CE_COUNTER			0x84
995
#define	PACKET3_INCREMENT_DE_COUNTER			0x85
996
#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
997
#define	PACKET3_WAIT_ON_DE_COUNTER			0x87
998
#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
999
#define	PACKET3_SET_CE_DE_COUNTERS			0x89
1000
#define	PACKET3_WAIT_ON_AVAIL_BUFFER			0x8A
1001
#define	PACKET3_SWITCH_BUFFER				0x8B
1002
 
3192 Serge 1003
/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1004
#define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
1005
#define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
1006
 
1007
#define DMA_RB_CNTL                                       0xd000
1008
#       define DMA_RB_ENABLE                              (1 << 0)
1009
#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
1010
#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
1011
#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
1012
#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
1013
#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
1014
#define DMA_RB_BASE                                       0xd004
1015
#define DMA_RB_RPTR                                       0xd008
1016
#define DMA_RB_WPTR                                       0xd00c
1017
 
1018
#define DMA_RB_RPTR_ADDR_HI                               0xd01c
1019
#define DMA_RB_RPTR_ADDR_LO                               0xd020
1020
 
1021
#define DMA_IB_CNTL                                       0xd024
1022
#       define DMA_IB_ENABLE                              (1 << 0)
1023
#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
1024
#define DMA_IB_RPTR                                       0xd028
1025
#define DMA_CNTL                                          0xd02c
1026
#       define TRAP_ENABLE                                (1 << 0)
1027
#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
1028
#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
1029
#       define DATA_SWAP_ENABLE                           (1 << 3)
1030
#       define FENCE_SWAP_ENABLE                          (1 << 4)
1031
#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
1032
#define DMA_STATUS_REG                                    0xd034
1033
#       define DMA_IDLE                                   (1 << 0)
1034
#define DMA_TILING_CONFIG  				  0xd0b8
1035
 
1036
#define DMA_PACKET(cmd, b, t, s, n)	((((cmd) & 0xF) << 28) |	\
1037
					 (((b) & 0x1) << 26) |		\
1038
					 (((t) & 0x1) << 23) |		\
1039
					 (((s) & 0x1) << 22) |		\
1040
					 (((n) & 0xFFFFF) << 0))
1041
 
1042
#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
1043
					 (((vmid) & 0xF) << 20) |	\
1044
					 (((n) & 0xFFFFF) << 0))
1045
 
1046
#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
1047
					 (1 << 26) |			\
1048
					 (1 << 21) |			\
1049
					 (((n) & 0xFFFFF) << 0))
1050
 
1051
/* async DMA Packet types */
1052
#define	DMA_PACKET_WRITE				  0x2
1053
#define	DMA_PACKET_COPY					  0x3
1054
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
1055
#define	DMA_PACKET_SEMAPHORE				  0x5
1056
#define	DMA_PACKET_FENCE				  0x6
1057
#define	DMA_PACKET_TRAP					  0x7
1058
#define	DMA_PACKET_SRBM_WRITE				  0x9
1059
#define	DMA_PACKET_CONSTANT_FILL			  0xd
1060
#define	DMA_PACKET_NOP					  0xf
1061
 
2997 Serge 1062
#endif