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5078 serge 1 
/*
2 
 * Copyright 2013 Advanced Micro Devices, Inc.
3 
 *
4 
 * Permission is hereby granted, free of charge, to any person obtaining a
5 
 * copy of this software and associated documentation files (the "Software"),
6 
 * to deal in the Software without restriction, including without limitation
7 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 
 * and/or sell copies of the Software, and to permit persons to whom the
9 
 * Software is furnished to do so, subject to the following conditions:
10 
 *
11 
 * The above copyright notice and this permission notice shall be included in
12 
 * all copies or substantial portions of the Software.
13 
 *
14 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 
 * OTHER DEALINGS IN THE SOFTWARE.
21 
 *
22 
 */
23 
 
24 
#include "drmP.h"
25 
#include "radeon.h"
5271 serge 26 
#include "radeon_asic.h"
5078 serge 27 
#include "sid.h"
28 
#include "r600_dpm.h"
29 
#include "si_dpm.h"
30 
#include "atom.h"
31 
#include
32 
#include
33 
 
34 
#define MC_CG_ARB_FREQ_F0           0x0a
35 
#define MC_CG_ARB_FREQ_F1           0x0b
36 
#define MC_CG_ARB_FREQ_F2           0x0c
37 
#define MC_CG_ARB_FREQ_F3           0x0d
38 
 
39 
#define SMC_RAM_END                 0x20000
40 
 
41 
#define SCLK_MIN_DEEPSLEEP_FREQ     1350
42 
 
43 
static const struct si_cac_config_reg cac_weights_tahiti[] =
44 
{
45 
	{ 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 
	{ 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 
	{ 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 
	{ 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 
	{ 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 
	{ 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 
	{ 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 
	{ 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 
	{ 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 
	{ 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 
	{ 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 
	{ 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 
	{ 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 
	{ 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 
	{ 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 
	{ 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 
	{ 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 
	{ 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 
	{ 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 
	{ 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 
	{ 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 
	{ 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 
	{ 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 
	{ 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 
	{ 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 
	{ 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 
	{ 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 
	{ 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 
	{ 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 
	{ 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 
	{ 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 
	{ 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 
	{ 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 
	{ 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 
	{ 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 
	{ 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 
	{ 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 
	{ 0xFFFFFFFF }
106 
};
107 
 
108 
static const struct si_cac_config_reg lcac_tahiti[] =
109 
{
110 
	{ 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 
	{ 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 
	{ 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 
	{ 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 
	{ 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 
	{ 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 
	{ 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 
	{ 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 
	{ 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 
	{ 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 
	{ 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 
	{ 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 
	{ 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 
	{ 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 
	{ 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 
	{ 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 
	{ 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 
	{ 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 
	{ 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 
	{ 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 
	{ 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 
	{ 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 
	{ 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 
	{ 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 
	{ 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 
	{ 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 
	{ 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 
	{ 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 
	{ 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 
	{ 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 
	{ 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 
	{ 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 
	{ 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 
	{ 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 
	{ 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 
	{ 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 
	{ 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 
	{ 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 
	{ 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 
	{ 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 
	{ 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 
	{ 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 
	{ 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 
	{ 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 
	{ 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 
	{ 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 
	{ 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 
	{ 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 
	{ 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 
	{ 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 
	{ 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 
	{ 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 
	{ 0xFFFFFFFF }
197 
 
198 
};
199 
 
200 
static const struct si_cac_config_reg cac_override_tahiti[] =
201 
{
202 
	{ 0xFFFFFFFF }
203 
};
204 
 
205 
static const struct si_powertune_data powertune_data_tahiti =
206 
{
207 
	((1 << 16) | 27027),
208 
	6,
209 
	0,
210 
	4,
211 
	95,
212 
	{
213 
		0UL,
214 
		0UL,
215 
		4521550UL,
216 
		309631529UL,
217 
		-1270850L,
218 
		4513710L,
219 
		40
220 
	},
221 
	595000000UL,
222 
	12,
223 
	{
224 
		0,
225 
		0,
226 
		0,
227 
		0,
228 
		0,
229 
		0,
230 
		0,
231 
 
232 
	},
233 
	true
234 
};
235 
 
236 
static const struct si_dte_data dte_data_tahiti =
237 
{
238 
	{ 1159409, 0, 0, 0, 0 },
239 
	{ 777, 0, 0, 0, 0 },
240 
	2,
241 
	54000,
242 
	127000,
243 
	25,
244 
	2,
245 
	10,
246 
	13,
247 
	{ 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 
	{ 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 
	{ 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 
	85,
251 
	false
252 
};
253 
 
254 
static const struct si_dte_data dte_data_tahiti_le =
255 
{
256 
	{ 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 
	{ 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 
	0x5,
259 
	0xAFC8,
260 
	0x64,
261 
	0x32,
262 
	1,
263 
	0,
264 
	0x10,
265 
	{ 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 
	{ 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 
	{ 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 
	85,
269 
	true
270 
};
271 
 
272 
static const struct si_dte_data dte_data_tahiti_pro =
273 
{
274 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
276 
	5,
277 
	45000,
278 
	100,
279 
	0xA,
280 
	1,
281 
	0,
282 
	0x10,
283 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 
	{ 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 
	90,
287 
	true
288 
};
289 
 
290 
static const struct si_dte_data dte_data_new_zealand =
291 
{
292 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 
	{ 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 
	0x5,
295 
	0xAFC8,
296 
	0x69,
297 
	0x32,
298 
	1,
299 
	0,
300 
	0x10,
301 
	{ 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 
	{ 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 
	85,
305 
	true
306 
};
307 
 
308 
static const struct si_dte_data dte_data_aruba_pro =
309 
{
310 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
312 
	5,
313 
	45000,
314 
	100,
315 
	0xA,
316 
	1,
317 
	0,
318 
	0x10,
319 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 
	{ 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 
	90,
323 
	true
324 
};
325 
 
326 
static const struct si_dte_data dte_data_malta =
327 
{
328 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
330 
	5,
331 
	45000,
332 
	100,
333 
	0xA,
334 
	1,
335 
	0,
336 
	0x10,
337 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 
	{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 
	90,
341 
	true
342 
};
343 
 
344 
struct si_cac_config_reg cac_weights_pitcairn[] =
345 
{
346 
	{ 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 
	{ 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 
	{ 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 
	{ 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 
	{ 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 
	{ 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 
	{ 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 
	{ 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 
	{ 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 
	{ 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 
	{ 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 
	{ 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 
	{ 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 
	{ 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 
	{ 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 
	{ 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 
	{ 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 
	{ 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 
	{ 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 
	{ 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 
	{ 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 
	{ 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 
	{ 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 
	{ 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 
	{ 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 
	{ 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 
	{ 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 
	{ 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 
	{ 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 
	{ 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 
	{ 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 
	{ 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 
	{ 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 
	{ 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 
	{ 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 
	{ 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 
	{ 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 
	{ 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 
	{ 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 
	{ 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 
	{ 0xFFFFFFFF }
407 
};
408 
 
409 
static const struct si_cac_config_reg lcac_pitcairn[] =
410 
{
411 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 
	{ 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 
	{ 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 
	{ 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 
	{ 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 
	{ 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 
	{ 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 
	{ 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 
	{ 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 
	{ 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 
	{ 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 
	{ 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 
	{ 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 
	{ 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 
	{ 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 
	{ 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 
	{ 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 
	{ 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 
	{ 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 
	{ 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 
	{ 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 
	{ 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 
	{ 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 
	{ 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 
	{ 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 
	{ 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 
	{ 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 
	{ 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 
	{ 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 
	{ 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 
	{ 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 
	{ 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 
	{ 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 
	{ 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 
	{ 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 
	{ 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 
	{ 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 
	{ 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 
	{ 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 
	{ 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 
	{ 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 
	{ 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 
	{ 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 
	{ 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 
	{ 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 
	{ 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 
	{ 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 
	{ 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 
	{ 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 
	{ 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 
	{ 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 
	{ 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 
	{ 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 
	{ 0xFFFFFFFF }
498 
};
499 
 
500 
static const struct si_cac_config_reg cac_override_pitcairn[] =
501 
{
502 
    { 0xFFFFFFFF }
503 
};
504 
 
505 
static const struct si_powertune_data powertune_data_pitcairn =
506 
{
507 
	((1 << 16) | 27027),
508 
	5,
509 
	0,
510 
	6,
511 
	100,
512 
	{
513 
		51600000UL,
514 
		1800000UL,
515 
		7194395UL,
516 
		309631529UL,
517 
		-1270850L,
518 
		4513710L,
519 
		100
520 
	},
521 
	117830498UL,
522 
	12,
523 
	{
524 
		0,
525 
		0,
526 
		0,
527 
		0,
528 
		0,
529 
		0,
530 
		0,
531 
 
532 
	},
533 
	true
534 
};
535 
 
536 
static const struct si_dte_data dte_data_pitcairn =
537 
{
538 
	{ 0, 0, 0, 0, 0 },
539 
	{ 0, 0, 0, 0, 0 },
540 
	0,
541 
	0,
542 
	0,
543 
	0,
544 
	0,
545 
	0,
546 
	0,
547 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 
	0,
551 
	false
552 
};
553 
 
554 
static const struct si_dte_data dte_data_curacao_xt =
555 
{
556 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
558 
	5,
559 
	45000,
560 
	100,
561 
	0xA,
562 
	1,
563 
	0,
564 
	0x10,
565 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 
	{ 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 
	90,
569 
	true
570 
};
571 
 
572 
static const struct si_dte_data dte_data_curacao_pro =
573 
{
574 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
576 
	5,
577 
	45000,
578 
	100,
579 
	0xA,
580 
	1,
581 
	0,
582 
	0x10,
583 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 
	{ 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 
	90,
587 
	true
588 
};
589 
 
590 
static const struct si_dte_data dte_data_neptune_xt =
591 
{
592 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
594 
	5,
595 
	45000,
596 
	100,
597 
	0xA,
598 
	1,
599 
	0,
600 
	0x10,
601 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 
	{ 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 
	90,
605 
	true
606 
};
607 
 
608 
static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609 
{
610 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 
	{ 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 
	{ 0xFFFFFFFF }
671 
};
672 
 
673 
static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674 
{
675 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 
	{ 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 
	{ 0xFFFFFFFF }
736 
};
737 
 
738 
static const struct si_cac_config_reg cac_weights_heathrow[] =
739 
{
740 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 
	{ 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 
	{ 0xFFFFFFFF }
801 
};
802 
 
803 
static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804 
{
805 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 
	{ 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 
	{ 0xFFFFFFFF }
866 
};
867 
 
868 
static const struct si_cac_config_reg cac_weights_cape_verde[] =
869 
{
870 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 
	{ 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 
	{ 0xFFFFFFFF }
931 
};
932 
 
933 
static const struct si_cac_config_reg lcac_cape_verde[] =
934 
{
935 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 
	{ 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 
	{ 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 
	{ 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 
	{ 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 
	{ 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 
	{ 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 
	{ 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 
	{ 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 
	{ 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 
	{ 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 
	{ 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 
	{ 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 
	{ 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 
	{ 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 
	{ 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 
	{ 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 
	{ 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 
	{ 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 
	{ 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 
	{ 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 
	{ 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 
	{ 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 
	{ 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 
	{ 0xFFFFFFFF }
990 
};
991 
 
992 
static const struct si_cac_config_reg cac_override_cape_verde[] =
993 
{
994 
    { 0xFFFFFFFF }
995 
};
996 
 
997 
static const struct si_powertune_data powertune_data_cape_verde =
998 
{
999 
	((1 << 16) | 0x6993),
1000 
	5,
1001 
	0,
1002 
	7,
1003 
	105,
1004 
	{
1005 
		0UL,
1006 
		0UL,
1007 
		7194395UL,
1008 
		309631529UL,
1009 
		-1270850L,
1010 
		4513710L,
1011 
		100
1012 
	},
1013 
	117830498UL,
1014 
	12,
1015 
	{
1016 
		0,
1017 
		0,
1018 
		0,
1019 
		0,
1020 
		0,
1021 
		0,
1022 
		0,
1023 
 
1024 
	},
1025 
	true
1026 
};
1027 
 
1028 
static const struct si_dte_data dte_data_cape_verde =
1029 
{
1030 
	{ 0, 0, 0, 0, 0 },
1031 
	{ 0, 0, 0, 0, 0 },
1032 
	0,
1033 
	0,
1034 
	0,
1035 
	0,
1036 
	0,
1037 
	0,
1038 
	0,
1039 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 
	0,
1043 
	false
1044 
};
1045 
 
1046 
static const struct si_dte_data dte_data_venus_xtx =
1047 
{
1048 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 
	{ 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 
	5,
1051 
	55000,
1052 
	0x69,
1053 
	0xA,
1054 
	1,
1055 
	0,
1056 
	0x3,
1057 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 
	{ 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 
	90,
1061 
	true
1062 
};
1063 
 
1064 
static const struct si_dte_data dte_data_venus_xt =
1065 
{
1066 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 
	{ 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 
	5,
1069 
	55000,
1070 
	0x69,
1071 
	0xA,
1072 
	1,
1073 
	0,
1074 
	0x3,
1075 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 
	{ 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 
	90,
1079 
	true
1080 
};
1081 
 
1082 
static const struct si_dte_data dte_data_venus_pro =
1083 
{
1084 
	{  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 
	{ 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 
	5,
1087 
	55000,
1088 
	0x69,
1089 
	0xA,
1090 
	1,
1091 
	0,
1092 
	0x3,
1093 
	{ 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 
	{ 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 
	{ 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 
	90,
1097 
	true
1098 
};
1099 
 
1100 
struct si_cac_config_reg cac_weights_oland[] =
1101 
{
1102 
	{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 
	{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 
	{ 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 
	{ 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 
	{ 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 
	{ 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 
	{ 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 
	{ 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 
	{ 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 
	{ 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 
	{ 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 
	{ 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 
	{ 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 
	{ 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 
	{ 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 
	{ 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 
	{ 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 
	{ 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 
	{ 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 
	{ 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 
	{ 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 
	{ 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 
	{ 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 
	{ 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 
	{ 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 
	{ 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 
	{ 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 
	{ 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 
	{ 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 
	{ 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 
	{ 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 
	{ 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 
	{ 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 
	{ 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 
	{ 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 
	{ 0xFFFFFFFF }
1163 
};
1164 
 
1165 
static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 
{
1167 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 
	{ 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 
	{ 0xFFFFFFFF }
1228 
};
1229 
 
1230 
static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 
{
1232 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 
	{ 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 
	{ 0xFFFFFFFF }
1293 
};
1294 
 
1295 
static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 
{
1297 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 
	{ 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 
	{ 0xFFFFFFFF }
1358 
};
1359 
 
1360 
static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 
{
1362 
	{ 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 
	{ 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 
	{ 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 
	{ 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 
	{ 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 
	{ 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 
	{ 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 
	{ 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 
	{ 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 
	{ 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 
	{ 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 
	{ 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 
	{ 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 
	{ 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 
	{ 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 
	{ 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 
	{ 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 
	{ 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 
	{ 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 
	{ 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 
	{ 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 
	{ 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 
	{ 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 
	{ 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 
	{ 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 
	{ 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 
	{ 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 
	{ 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 
	{ 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 
	{ 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 
	{ 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 
	{ 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 
	{ 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 
	{ 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 
	{ 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 
	{ 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 
	{ 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 
	{ 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 
	{ 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 
	{ 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 
	{ 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 
	{ 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 
	{ 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 
	{ 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 
	{ 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 
	{ 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 
	{ 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 
	{ 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 
	{ 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 
	{ 0xFFFFFFFF }
1423 
};
1424 
 
1425 
static const struct si_cac_config_reg lcac_oland[] =
1426 
{
1427 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 
	{ 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 
	{ 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 
	{ 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 
	{ 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 
	{ 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 
	{ 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 
	{ 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 
	{ 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 
	{ 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 
	{ 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 
	{ 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 
	{ 0xFFFFFFFF }
1470 
};
1471 
 
1472 
static const struct si_cac_config_reg lcac_mars_pro[] =
1473 
{
1474 
	{ 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 
	{ 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 
	{ 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 
	{ 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 
	{ 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 
	{ 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 
	{ 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 
	{ 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 
	{ 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 
	{ 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 
	{ 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 
	{ 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 
	{ 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 
	{ 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 
	{ 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 
	{ 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 
	{ 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 
	{ 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 
	{ 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 
	{ 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 
	{ 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 
	{ 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 
	{ 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 
	{ 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 
	{ 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 
	{ 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 
	{ 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 
	{ 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 
	{ 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 
	{ 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 
	{ 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 
	{ 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 
	{ 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 
	{ 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 
	{ 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 
	{ 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 
	{ 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 
	{ 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 
	{ 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 
	{ 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 
	{ 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 
	{ 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 
	{ 0xFFFFFFFF }
1517 
};
1518 
 
1519 
static const struct si_cac_config_reg cac_override_oland[] =
1520 
{
1521 
	{ 0xFFFFFFFF }
1522 
};
1523 
 
1524 
static const struct si_powertune_data powertune_data_oland =
1525 
{
1526 
	((1 << 16) | 0x6993),
1527 
	5,
1528 
	0,
1529 
	7,
1530 
	105,
1531 
	{
1532 
		0UL,
1533 
		0UL,
1534 
		7194395UL,
1535 
		309631529UL,
1536 
		-1270850L,
1537 
		4513710L,
1538 
		100
1539 
	},
1540 
	117830498UL,
1541 
	12,
1542 
	{
1543 
		0,
1544 
		0,
1545 
		0,
1546 
		0,
1547 
		0,
1548 
		0,
1549 
		0,
1550 
 
1551 
	},
1552 
	true
1553 
};
1554 
 
1555 
static const struct si_powertune_data powertune_data_mars_pro =
1556 
{
1557 
	((1 << 16) | 0x6993),
1558 
	5,
1559 
	0,
1560 
	7,
1561 
	105,
1562 
	{
1563 
		0UL,
1564 
		0UL,
1565 
		7194395UL,
1566 
		309631529UL,
1567 
		-1270850L,
1568 
		4513710L,
1569 
		100
1570 
	},
1571 
	117830498UL,
1572 
	12,
1573 
	{
1574 
		0,
1575 
		0,
1576 
		0,
1577 
		0,
1578 
		0,
1579 
		0,
1580 
		0,
1581 
 
1582 
	},
1583 
	true
1584 
};
1585 
 
1586 
static const struct si_dte_data dte_data_oland =
1587 
{
1588 
	{ 0, 0, 0, 0, 0 },
1589 
	{ 0, 0, 0, 0, 0 },
1590 
	0,
1591 
	0,
1592 
	0,
1593 
	0,
1594 
	0,
1595 
	0,
1596 
	0,
1597 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 
	0,
1601 
	false
1602 
};
1603 
 
1604 
static const struct si_dte_data dte_data_mars_pro =
1605 
{
1606 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 
	5,
1609 
	55000,
1610 
	105,
1611 
	0xA,
1612 
	1,
1613 
	0,
1614 
	0x10,
1615 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 
	{ 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 
	90,
1619 
	true
1620 
};
1621 
 
1622 
static const struct si_dte_data dte_data_sun_xt =
1623 
{
1624 
	{ 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 
	{ 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 
	5,
1627 
	55000,
1628 
	105,
1629 
	0xA,
1630 
	1,
1631 
	0,
1632 
	0x10,
1633 
	{ 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 
	{ 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 
	{ 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 
	90,
1637 
	true
1638 
};
1639 
 
1640 
 
1641 
static const struct si_cac_config_reg cac_weights_hainan[] =
1642 
{
1643 
	{ 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 
	{ 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 
	{ 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 
	{ 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 
	{ 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 
	{ 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 
	{ 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 
	{ 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 
	{ 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 
	{ 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 
	{ 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 
	{ 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 
	{ 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 
	{ 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 
	{ 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 
	{ 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 
	{ 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 
	{ 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 
	{ 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 
	{ 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 
	{ 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 
	{ 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 
	{ 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 
	{ 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 
	{ 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 
	{ 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 
	{ 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 
	{ 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 
	{ 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 
	{ 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 
	{ 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 
	{ 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 
	{ 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 
	{ 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 
	{ 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 
	{ 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 
	{ 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 
	{ 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 
	{ 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 
	{ 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 
	{ 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 
	{ 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 
	{ 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 
	{ 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 
	{ 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 
	{ 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 
	{ 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 
	{ 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 
	{ 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 
	{ 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 
	{ 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 
	{ 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 
	{ 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 
	{ 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 
	{ 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 
	{ 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 
	{ 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 
	{ 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 
	{ 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 
	{ 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 
	{ 0xFFFFFFFF }
1704 
};
1705 
 
1706 
static const struct si_powertune_data powertune_data_hainan =
1707 
{
1708 
	((1 << 16) | 0x6993),
1709 
	5,
1710 
	0,
1711 
	9,
1712 
	105,
1713 
	{
1714 
		0UL,
1715 
		0UL,
1716 
		7194395UL,
1717 
		309631529UL,
1718 
		-1270850L,
1719 
		4513710L,
1720 
		100
1721 
	},
1722 
	117830498UL,
1723 
	12,
1724 
	{
1725 
		0,
1726 
		0,
1727 
		0,
1728 
		0,
1729 
		0,
1730 
		0,
1731 
		0,
1732 
 
1733 
	},
1734 
	true
1735 
};
1736 
 
1737 
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 
struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 
struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741 
 
1742 
extern int si_mc_load_microcode(struct radeon_device *rdev);
6104 serge 1743 
extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
5078 serge 1744 
 
1745 
static int si_populate_voltage_value(struct radeon_device *rdev,
1746 
				     const struct atom_voltage_table *table,
1747 
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 
static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 
				    u16 *std_voltage);
1751 
static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 
				      u16 reg_offset, u32 value);
1753 
static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 
					 struct rv7xx_pl *pl,
1755 
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 
static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 
				    u32 engine_clock,
1758 
				    SISLANDS_SMC_SCLK_VALUE *sclk);
1759 
 
6104 serge 1760 
static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 
static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762 
 
5078 serge 1763 
static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 
{
1765 
        struct si_power_info *pi = rdev->pm.dpm.priv;
1766 
 
1767 
        return pi;
1768 
}
1769 
 
1770 
static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 
						     u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 
{
1773 
	s64 kt, kv, leakage_w, i_leakage, vddc;
1774 
	s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 
	s64 tmp;
1776 
 
1777 
	i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 
	vddc = div64_s64(drm_int2fixp(v), 1000);
1779 
	temperature = div64_s64(drm_int2fixp(t), 1000);
1780 
 
1781 
	t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 
	t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 
	av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 
	bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 
	t_ref = drm_int2fixp(coeff->t_ref);
1786 
 
1787 
	tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 
	kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 
	kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 
	kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791 
 
1792 
	leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793 
 
1794 
	*leakage = drm_fixp2int(leakage_w * 1000);
1795 
}
1796 
 
1797 
static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 
					     const struct ni_leakage_coeffients *coeff,
1799 
					     u16 v,
1800 
					     s32 t,
1801 
					     u32 i_leakage,
1802 
					     u32 *leakage)
1803 
{
1804 
	si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 
}
1806 
 
1807 
static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 
					       const u32 fixed_kt, u16 v,
1809 
					       u32 ileakage, u32 *leakage)
1810 
{
1811 
	s64 kt, kv, leakage_w, i_leakage, vddc;
1812 
 
1813 
	i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 
	vddc = div64_s64(drm_int2fixp(v), 1000);
1815 
 
1816 
	kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 
	kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 
			  drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819 
 
1820 
	leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821 
 
1822 
	*leakage = drm_fixp2int(leakage_w * 1000);
1823 
}
1824 
 
1825 
static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 
				       const struct ni_leakage_coeffients *coeff,
1827 
				       const u32 fixed_kt,
1828 
				       u16 v,
1829 
				       u32 i_leakage,
1830 
				       u32 *leakage)
1831 
{
1832 
	si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 
}
1834 
 
1835 
 
1836 
static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 
				   struct si_dte_data *dte_data)
1838 
{
1839 
	u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 
	u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 
	u32 k = dte_data->k;
1842 
	u32 t_max = dte_data->max_t;
1843 
	u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 
	u32 t_0 = dte_data->t0;
1845 
	u32 i;
1846 
 
1847 
	if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 
		dte_data->tdep_count = 3;
1849 
 
1850 
		for (i = 0; i < k; i++) {
1851 
			dte_data->r[i] =
1852 
				(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 
				(p_limit2  * (u32)100);
1854 
		}
1855 
 
1856 
		dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857 
 
1858 
		for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 
			dte_data->tdep_r[i] = dte_data->r[4];
1860 
		}
1861 
	} else {
1862 
		DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 
	}
1864 
}
1865 
 
1866 
static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 
{
1868 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 
	struct si_power_info *si_pi = si_get_pi(rdev);
1870 
	bool update_dte_from_pl2 = false;
1871 
 
1872 
	if (rdev->family == CHIP_TAHITI) {
1873 
		si_pi->cac_weights = cac_weights_tahiti;
1874 
		si_pi->lcac_config = lcac_tahiti;
1875 
		si_pi->cac_override = cac_override_tahiti;
1876 
		si_pi->powertune_data = &powertune_data_tahiti;
1877 
		si_pi->dte_data = dte_data_tahiti;
1878 
 
1879 
		switch (rdev->pdev->device) {
1880 
		case 0x6798:
1881 
			si_pi->dte_data.enable_dte_by_default = true;
1882 
			break;
1883 
		case 0x6799:
1884 
			si_pi->dte_data = dte_data_new_zealand;
1885 
			break;
1886 
		case 0x6790:
1887 
		case 0x6791:
1888 
		case 0x6792:
1889 
		case 0x679E:
1890 
			si_pi->dte_data = dte_data_aruba_pro;
1891 
			update_dte_from_pl2 = true;
1892 
			break;
1893 
		case 0x679B:
1894 
			si_pi->dte_data = dte_data_malta;
1895 
			update_dte_from_pl2 = true;
1896 
			break;
1897 
		case 0x679A:
1898 
			si_pi->dte_data = dte_data_tahiti_pro;
1899 
			update_dte_from_pl2 = true;
1900 
			break;
1901 
		default:
1902 
			if (si_pi->dte_data.enable_dte_by_default == true)
1903 
				DRM_ERROR("DTE is not enabled!\n");
1904 
			break;
1905 
		}
1906 
	} else if (rdev->family == CHIP_PITCAIRN) {
1907 
		switch (rdev->pdev->device) {
1908 
		case 0x6810:
1909 
		case 0x6818:
1910 
			si_pi->cac_weights = cac_weights_pitcairn;
1911 
			si_pi->lcac_config = lcac_pitcairn;
1912 
			si_pi->cac_override = cac_override_pitcairn;
1913 
			si_pi->powertune_data = &powertune_data_pitcairn;
1914 
			si_pi->dte_data = dte_data_curacao_xt;
1915 
			update_dte_from_pl2 = true;
1916 
			break;
1917 
		case 0x6819:
1918 
		case 0x6811:
1919 
			si_pi->cac_weights = cac_weights_pitcairn;
1920 
			si_pi->lcac_config = lcac_pitcairn;
1921 
			si_pi->cac_override = cac_override_pitcairn;
1922 
			si_pi->powertune_data = &powertune_data_pitcairn;
1923 
			si_pi->dte_data = dte_data_curacao_pro;
1924 
			update_dte_from_pl2 = true;
1925 
			break;
1926 
		case 0x6800:
1927 
		case 0x6806:
1928 
			si_pi->cac_weights = cac_weights_pitcairn;
1929 
			si_pi->lcac_config = lcac_pitcairn;
1930 
			si_pi->cac_override = cac_override_pitcairn;
1931 
			si_pi->powertune_data = &powertune_data_pitcairn;
1932 
			si_pi->dte_data = dte_data_neptune_xt;
1933 
			update_dte_from_pl2 = true;
1934 
			break;
1935 
		default:
1936 
			si_pi->cac_weights = cac_weights_pitcairn;
1937 
			si_pi->lcac_config = lcac_pitcairn;
1938 
			si_pi->cac_override = cac_override_pitcairn;
1939 
			si_pi->powertune_data = &powertune_data_pitcairn;
1940 
			si_pi->dte_data = dte_data_pitcairn;
1941 
			break;
1942 
		}
1943 
	} else if (rdev->family == CHIP_VERDE) {
1944 
		si_pi->lcac_config = lcac_cape_verde;
1945 
		si_pi->cac_override = cac_override_cape_verde;
1946 
		si_pi->powertune_data = &powertune_data_cape_verde;
1947 
 
1948 
		switch (rdev->pdev->device) {
1949 
		case 0x683B:
1950 
		case 0x683F:
1951 
		case 0x6829:
1952 
		case 0x6835:
1953 
			si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 
			si_pi->dte_data = dte_data_cape_verde;
1955 
			break;
1956 
		case 0x682C:
1957 
			si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 
			si_pi->dte_data = dte_data_sun_xt;
1959 
			break;
1960 
		case 0x6825:
1961 
		case 0x6827:
1962 
			si_pi->cac_weights = cac_weights_heathrow;
1963 
			si_pi->dte_data = dte_data_cape_verde;
1964 
			break;
1965 
		case 0x6824:
1966 
		case 0x682D:
1967 
			si_pi->cac_weights = cac_weights_chelsea_xt;
1968 
			si_pi->dte_data = dte_data_cape_verde;
1969 
			break;
1970 
		case 0x682F:
1971 
			si_pi->cac_weights = cac_weights_chelsea_pro;
1972 
			si_pi->dte_data = dte_data_cape_verde;
1973 
			break;
1974 
		case 0x6820:
1975 
			si_pi->cac_weights = cac_weights_heathrow;
1976 
			si_pi->dte_data = dte_data_venus_xtx;
1977 
			break;
1978 
		case 0x6821:
1979 
			si_pi->cac_weights = cac_weights_heathrow;
1980 
			si_pi->dte_data = dte_data_venus_xt;
1981 
			break;
1982 
		case 0x6823:
1983 
		case 0x682B:
1984 
		case 0x6822:
1985 
		case 0x682A:
1986 
			si_pi->cac_weights = cac_weights_chelsea_pro;
1987 
			si_pi->dte_data = dte_data_venus_pro;
1988 
			break;
1989 
		default:
1990 
			si_pi->cac_weights = cac_weights_cape_verde;
1991 
			si_pi->dte_data = dte_data_cape_verde;
1992 
			break;
1993 
		}
1994 
	} else if (rdev->family == CHIP_OLAND) {
1995 
		switch (rdev->pdev->device) {
1996 
		case 0x6601:
1997 
		case 0x6621:
1998 
		case 0x6603:
1999 
		case 0x6605:
2000 
			si_pi->cac_weights = cac_weights_mars_pro;
2001 
			si_pi->lcac_config = lcac_mars_pro;
2002 
			si_pi->cac_override = cac_override_oland;
2003 
			si_pi->powertune_data = &powertune_data_mars_pro;
2004 
			si_pi->dte_data = dte_data_mars_pro;
2005 
			update_dte_from_pl2 = true;
2006 
			break;
2007 
		case 0x6600:
2008 
		case 0x6606:
2009 
		case 0x6620:
2010 
		case 0x6604:
2011 
			si_pi->cac_weights = cac_weights_mars_xt;
2012 
			si_pi->lcac_config = lcac_mars_pro;
2013 
			si_pi->cac_override = cac_override_oland;
2014 
			si_pi->powertune_data = &powertune_data_mars_pro;
2015 
			si_pi->dte_data = dte_data_mars_pro;
2016 
			update_dte_from_pl2 = true;
2017 
			break;
2018 
		case 0x6611:
2019 
		case 0x6613:
2020 
		case 0x6608:
2021 
			si_pi->cac_weights = cac_weights_oland_pro;
2022 
			si_pi->lcac_config = lcac_mars_pro;
2023 
			si_pi->cac_override = cac_override_oland;
2024 
			si_pi->powertune_data = &powertune_data_mars_pro;
2025 
			si_pi->dte_data = dte_data_mars_pro;
2026 
			update_dte_from_pl2 = true;
2027 
			break;
2028 
		case 0x6610:
2029 
			si_pi->cac_weights = cac_weights_oland_xt;
2030 
			si_pi->lcac_config = lcac_mars_pro;
2031 
			si_pi->cac_override = cac_override_oland;
2032 
			si_pi->powertune_data = &powertune_data_mars_pro;
2033 
			si_pi->dte_data = dte_data_mars_pro;
2034 
			update_dte_from_pl2 = true;
2035 
			break;
2036 
		default:
2037 
			si_pi->cac_weights = cac_weights_oland;
2038 
			si_pi->lcac_config = lcac_oland;
2039 
			si_pi->cac_override = cac_override_oland;
2040 
			si_pi->powertune_data = &powertune_data_oland;
2041 
			si_pi->dte_data = dte_data_oland;
2042 
			break;
2043 
		}
2044 
	} else if (rdev->family == CHIP_HAINAN) {
2045 
		si_pi->cac_weights = cac_weights_hainan;
2046 
		si_pi->lcac_config = lcac_oland;
2047 
		si_pi->cac_override = cac_override_oland;
2048 
		si_pi->powertune_data = &powertune_data_hainan;
2049 
		si_pi->dte_data = dte_data_sun_xt;
2050 
		update_dte_from_pl2 = true;
2051 
	} else {
2052 
		DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 
		return;
2054 
	}
2055 
 
2056 
	ni_pi->enable_power_containment = false;
2057 
	ni_pi->enable_cac = false;
2058 
	ni_pi->enable_sq_ramping = false;
2059 
	si_pi->enable_dte = false;
2060 
 
2061 
	if (si_pi->powertune_data->enable_powertune_by_default) {
2062 
		ni_pi->enable_power_containment= true;
2063 
		ni_pi->enable_cac = true;
2064 
		if (si_pi->dte_data.enable_dte_by_default) {
2065 
			si_pi->enable_dte = true;
2066 
			if (update_dte_from_pl2)
2067 
				si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068 
 
2069 
		}
2070 
		ni_pi->enable_sq_ramping = true;
2071 
	}
2072 
 
2073 
	ni_pi->driver_calculate_cac_leakage = true;
2074 
	ni_pi->cac_configuration_required = true;
2075 
 
2076 
	if (ni_pi->cac_configuration_required) {
2077 
		ni_pi->support_cac_long_term_average = true;
2078 
		si_pi->dyn_powertune_data.l2_lta_window_size =
2079 
			si_pi->powertune_data->l2_lta_window_size_default;
2080 
		si_pi->dyn_powertune_data.lts_truncate =
2081 
			si_pi->powertune_data->lts_truncate_default;
2082 
	} else {
2083 
		ni_pi->support_cac_long_term_average = false;
2084 
		si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 
		si_pi->dyn_powertune_data.lts_truncate = 0;
2086 
	}
2087 
 
2088 
	si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 
}
2090 
 
2091 
static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 
{
2093 
	return 1;
2094 
}
2095 
 
2096 
static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 
{
2098 
	u32 xclk;
2099 
	u32 wintime;
2100 
	u32 cac_window;
2101 
	u32 cac_window_size;
2102 
 
2103 
	xclk = radeon_get_xclk(rdev);
2104 
 
2105 
	if (xclk == 0)
2106 
		return 0;
2107 
 
2108 
	cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 
	cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110 
 
2111 
	wintime = (cac_window_size * 100) / xclk;
2112 
 
2113 
	return wintime;
2114 
}
2115 
 
2116 
static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 
{
2118 
	return power_in_watts;
2119 
}
2120 
 
2121 
static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 
					    bool adjust_polarity,
2123 
					    u32 tdp_adjustment,
2124 
					    u32 *tdp_limit,
2125 
					    u32 *near_tdp_limit)
2126 
{
2127 
	u32 adjustment_delta, max_tdp_limit;
2128 
 
2129 
	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 
		return -EINVAL;
2131 
 
2132 
	max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133 
 
2134 
	if (adjust_polarity) {
2135 
		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 
		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 
	} else {
2138 
		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 
		adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 
		if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 
			*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 
		else
2143 
			*near_tdp_limit = 0;
2144 
	}
2145 
 
2146 
	if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 
		return -EINVAL;
2148 
	if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 
		return -EINVAL;
2150 
 
2151 
	return 0;
2152 
}
2153 
 
2154 
static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 
				      struct radeon_ps *radeon_state)
2156 
{
2157 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 
	struct si_power_info *si_pi = si_get_pi(rdev);
2159 
 
2160 
	if (ni_pi->enable_power_containment) {
2161 
		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 
		PP_SIslands_PAPMParameters *papm_parm;
2163 
		struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 
		u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 
		u32 tdp_limit;
2166 
		u32 near_tdp_limit;
2167 
		int ret;
2168 
 
2169 
		if (scaling_factor == 0)
2170 
			return -EINVAL;
2171 
 
2172 
		memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173 
 
2174 
		ret = si_calculate_adjusted_tdp_limits(rdev,
2175 
						       false, /* ??? */
2176 
						       rdev->pm.dpm.tdp_adjustment,
2177 
						       &tdp_limit,
2178 
						       &near_tdp_limit);
2179 
		if (ret)
2180 
			return ret;
2181 
 
2182 
		smc_table->dpm2Params.TDPLimit =
2183 
			cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 
		smc_table->dpm2Params.NearTDPLimit =
2185 
			cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 
		smc_table->dpm2Params.SafePowerLimit =
2187 
			cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188 
 
2189 
		ret = si_copy_bytes_to_smc(rdev,
2190 
					   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 
						 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 
					   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 
					   sizeof(u32) * 3,
2194 
					   si_pi->sram_end);
2195 
		if (ret)
2196 
			return ret;
2197 
 
2198 
		if (si_pi->enable_ppm) {
2199 
			papm_parm = &si_pi->papm_parm;
2200 
			memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 
			papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 
			papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 
			papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 
			papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 
			papm_parm->PlatformPowerLimit = 0xffffffff;
2206 
			papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207 
 
2208 
			ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 
						   (u8 *)papm_parm,
2210 
						   sizeof(PP_SIslands_PAPMParameters),
2211 
						   si_pi->sram_end);
2212 
			if (ret)
2213 
				return ret;
2214 
		}
2215 
	}
2216 
	return 0;
2217 
}
2218 
 
2219 
static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 
					struct radeon_ps *radeon_state)
2221 
{
2222 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 
	struct si_power_info *si_pi = si_get_pi(rdev);
2224 
 
2225 
	if (ni_pi->enable_power_containment) {
2226 
		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 
		u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 
		int ret;
2229 
 
2230 
		memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231 
 
2232 
		smc_table->dpm2Params.NearTDPLimit =
2233 
			cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 
		smc_table->dpm2Params.SafePowerLimit =
2235 
			cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236 
 
2237 
		ret = si_copy_bytes_to_smc(rdev,
2238 
					   (si_pi->state_table_start +
2239 
					    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 
					    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 
					   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 
					   sizeof(u32) * 2,
2243 
					   si_pi->sram_end);
2244 
		if (ret)
2245 
			return ret;
2246 
	}
2247 
 
2248 
	return 0;
2249 
}
2250 
 
2251 
static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 
					       const u16 prev_std_vddc,
2253 
					       const u16 curr_std_vddc)
2254 
{
2255 
	u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 
	u64 prev_vddc = (u64)prev_std_vddc;
2257 
	u64 curr_vddc = (u64)curr_std_vddc;
2258 
	u64 pwr_efficiency_ratio, n, d;
2259 
 
2260 
	if ((prev_vddc == 0) || (curr_vddc == 0))
2261 
		return 0;
2262 
 
2263 
	n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 
	d = prev_vddc * prev_vddc;
2265 
	pwr_efficiency_ratio = div64_u64(n, d);
2266 
 
2267 
	if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 
		return 0;
2269 
 
2270 
	return (u16)pwr_efficiency_ratio;
2271 
}
2272 
 
2273 
static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 
					    struct radeon_ps *radeon_state)
2275 
{
2276 
	struct si_power_info *si_pi = si_get_pi(rdev);
2277 
 
2278 
	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 
	    radeon_state->vclk && radeon_state->dclk)
2280 
		return true;
2281 
 
2282 
	return false;
2283 
}
2284 
 
2285 
static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 
						struct radeon_ps *radeon_state,
2287 
						SISLANDS_SMC_SWSTATE *smc_state)
2288 
{
2289 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 
	struct ni_ps *state = ni_get_ps(radeon_state);
2292 
	SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 
	u32 prev_sclk;
2294 
	u32 max_sclk;
2295 
	u32 min_sclk;
2296 
	u16 prev_std_vddc;
2297 
	u16 curr_std_vddc;
2298 
	int i;
2299 
	u16 pwr_efficiency_ratio;
2300 
	u8 max_ps_percent;
2301 
	bool disable_uvd_power_tune;
2302 
	int ret;
2303 
 
2304 
	if (ni_pi->enable_power_containment == false)
2305 
		return 0;
2306 
 
2307 
	if (state->performance_level_count == 0)
2308 
		return -EINVAL;
2309 
 
2310 
	if (smc_state->levelCount != state->performance_level_count)
2311 
		return -EINVAL;
2312 
 
2313 
	disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314 
 
2315 
	smc_state->levels[0].dpm2.MaxPS = 0;
2316 
	smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 
	smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 
	smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 
	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320 
 
2321 
	for (i = 1; i < state->performance_level_count; i++) {
2322 
		prev_sclk = state->performance_levels[i-1].sclk;
2323 
		max_sclk  = state->performance_levels[i].sclk;
2324 
		if (i == 1)
2325 
			max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 
		else
2327 
			max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328 
 
2329 
		if (prev_sclk > max_sclk)
2330 
			return -EINVAL;
2331 
 
2332 
		if ((max_ps_percent == 0) ||
2333 
		    (prev_sclk == max_sclk) ||
2334 
		    disable_uvd_power_tune) {
2335 
			min_sclk = max_sclk;
2336 
		} else if (i == 1) {
2337 
			min_sclk = prev_sclk;
2338 
		} else {
2339 
			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 
		}
2341 
 
2342 
		if (min_sclk < state->performance_levels[0].sclk)
2343 
			min_sclk = state->performance_levels[0].sclk;
2344 
 
2345 
		if (min_sclk == 0)
2346 
			return -EINVAL;
2347 
 
2348 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 
						state->performance_levels[i-1].vddc, &vddc);
2350 
		if (ret)
2351 
			return ret;
2352 
 
2353 
		ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 
		if (ret)
2355 
			return ret;
2356 
 
2357 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 
						state->performance_levels[i].vddc, &vddc);
2359 
		if (ret)
2360 
			return ret;
2361 
 
2362 
		ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 
		if (ret)
2364 
			return ret;
2365 
 
2366 
		pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 
									   prev_std_vddc, curr_std_vddc);
2368 
 
2369 
		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 
		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 
		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 
		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 
		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 
	}
2375 
 
2376 
	return 0;
2377 
}
2378 
 
2379 
static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 
					 struct radeon_ps *radeon_state,
2381 
					 SISLANDS_SMC_SWSTATE *smc_state)
2382 
{
2383 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 
	struct ni_ps *state = ni_get_ps(radeon_state);
2385 
	u32 sq_power_throttle, sq_power_throttle2;
2386 
	bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 
	int i;
2388 
 
2389 
	if (state->performance_level_count == 0)
2390 
		return -EINVAL;
2391 
 
2392 
	if (smc_state->levelCount != state->performance_level_count)
2393 
		return -EINVAL;
2394 
 
2395 
	if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 
		return -EINVAL;
2397 
 
2398 
	if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 
		enable_sq_ramping = false;
2400 
 
2401 
	if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 
		enable_sq_ramping = false;
2403 
 
2404 
	if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 
		enable_sq_ramping = false;
2406 
 
2407 
	if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 
		enable_sq_ramping = false;
2409 
 
2410 
	if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 
		enable_sq_ramping = false;
2412 
 
2413 
	for (i = 0; i < state->performance_level_count; i++) {
2414 
		sq_power_throttle = 0;
2415 
		sq_power_throttle2 = 0;
2416 
 
2417 
		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 
		    enable_sq_ramping) {
2419 
			sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 
			sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 
			sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 
			sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 
			sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 
		} else {
2425 
			sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 
			sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 
		}
2428 
 
2429 
		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 
		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 
	}
2432 
 
2433 
	return 0;
2434 
}
2435 
 
2436 
static int si_enable_power_containment(struct radeon_device *rdev,
2437 
				       struct radeon_ps *radeon_new_state,
2438 
				       bool enable)
2439 
{
2440 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 
	PPSMC_Result smc_result;
2442 
	int ret = 0;
2443 
 
2444 
	if (ni_pi->enable_power_containment) {
2445 
		if (enable) {
2446 
			if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 
				if (smc_result != PPSMC_Result_OK) {
2449 
					ret = -EINVAL;
2450 
					ni_pi->pc_enabled = false;
2451 
				} else {
2452 
					ni_pi->pc_enabled = true;
2453 
				}
2454 
			}
2455 
		} else {
2456 
			smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 
			if (smc_result != PPSMC_Result_OK)
2458 
				ret = -EINVAL;
2459 
			ni_pi->pc_enabled = false;
2460 
		}
2461 
	}
2462 
 
2463 
	return ret;
2464 
}
2465 
 
2466 
static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 
{
2468 
	struct si_power_info *si_pi = si_get_pi(rdev);
2469 
	int ret = 0;
2470 
	struct si_dte_data *dte_data = &si_pi->dte_data;
2471 
	Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 
	u32 table_size;
2473 
	u8 tdep_count;
2474 
	u32 i;
2475 
 
2476 
	if (dte_data == NULL)
2477 
		si_pi->enable_dte = false;
2478 
 
2479 
	if (si_pi->enable_dte == false)
2480 
		return 0;
2481 
 
2482 
	if (dte_data->k <= 0)
2483 
		return -EINVAL;
2484 
 
2485 
	dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 
	if (dte_tables == NULL) {
2487 
		si_pi->enable_dte = false;
2488 
		return -ENOMEM;
2489 
	}
2490 
 
2491 
	table_size = dte_data->k;
2492 
 
2493 
	if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 
		table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495 
 
2496 
	tdep_count = dte_data->tdep_count;
2497 
	if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 
		tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499 
 
2500 
	dte_tables->K = cpu_to_be32(table_size);
2501 
	dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 
	dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 
	dte_tables->WindowSize = dte_data->window_size;
2504 
	dte_tables->temp_select = dte_data->temp_select;
2505 
	dte_tables->DTE_mode = dte_data->dte_mode;
2506 
	dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507 
 
2508 
	if (tdep_count > 0)
2509 
		table_size--;
2510 
 
2511 
	for (i = 0; i < table_size; i++) {
2512 
		dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 
		dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2514 
	}
2515 
 
2516 
	dte_tables->Tdep_count = tdep_count;
2517 
 
2518 
	for (i = 0; i < (u32)tdep_count; i++) {
2519 
		dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 
		dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 
		dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 
	}
2523 
 
2524 
	ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 
				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 
	kfree(dte_tables);
2527 
 
2528 
	return ret;
2529 
}
2530 
 
2531 
static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 
					  u16 *max, u16 *min)
2533 
{
2534 
	struct si_power_info *si_pi = si_get_pi(rdev);
2535 
	struct radeon_cac_leakage_table *table =
2536 
		&rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 
	u32 i;
2538 
	u32 v0_loadline;
2539 
 
2540 
 
2541 
	if (table == NULL)
2542 
		return -EINVAL;
2543 
 
2544 
	*max = 0;
2545 
	*min = 0xFFFF;
2546 
 
2547 
	for (i = 0; i < table->count; i++) {
2548 
		if (table->entries[i].vddc > *max)
2549 
			*max = table->entries[i].vddc;
2550 
		if (table->entries[i].vddc < *min)
2551 
			*min = table->entries[i].vddc;
2552 
	}
2553 
 
2554 
	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 
		return -EINVAL;
2556 
 
2557 
	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558 
 
2559 
	if (v0_loadline > 0xFFFFUL)
2560 
		return -EINVAL;
2561 
 
2562 
	*min = (u16)v0_loadline;
2563 
 
2564 
	if ((*min > *max) || (*max == 0) || (*min == 0))
2565 
		return -EINVAL;
2566 
 
2567 
	return 0;
2568 
}
2569 
 
2570 
static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 
{
2572 
	return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 
		SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 
}
2575 
 
2576 
static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 
				     PP_SIslands_CacConfig *cac_tables,
2578 
				     u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 
				     u16 t0, u16 t_step)
2580 
{
2581 
	struct si_power_info *si_pi = si_get_pi(rdev);
2582 
	u32 leakage;
2583 
	unsigned int i, j;
2584 
	s32 t;
2585 
	u32 smc_leakage;
2586 
	u32 scaling_factor;
2587 
	u16 voltage;
2588 
 
2589 
	scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590 
 
2591 
	for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 
		t = (1000 * (i * t_step + t0));
2593 
 
2594 
		for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 
			voltage = vddc_max - (vddc_step * j);
2596 
 
2597 
			si_calculate_leakage_for_v_and_t(rdev,
2598 
							 &si_pi->powertune_data->leakage_coefficients,
2599 
							 voltage,
2600 
							 t,
2601 
							 si_pi->dyn_powertune_data.cac_leakage,
2602 
							 &leakage);
2603 
 
2604 
			smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605 
 
2606 
			if (smc_leakage > 0xFFFF)
2607 
				smc_leakage = 0xFFFF;
2608 
 
2609 
			cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 
				cpu_to_be16((u16)smc_leakage);
2611 
		}
2612 
	}
2613 
	return 0;
2614 
}
2615 
 
2616 
static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 
					    PP_SIslands_CacConfig *cac_tables,
2618 
					    u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 
{
2620 
	struct si_power_info *si_pi = si_get_pi(rdev);
2621 
	u32 leakage;
2622 
	unsigned int i, j;
2623 
	u32 smc_leakage;
2624 
	u32 scaling_factor;
2625 
	u16 voltage;
2626 
 
2627 
	scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628 
 
2629 
	for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 
		voltage = vddc_max - (vddc_step * j);
2631 
 
2632 
		si_calculate_leakage_for_v(rdev,
2633 
					   &si_pi->powertune_data->leakage_coefficients,
2634 
					   si_pi->powertune_data->fixed_kt,
2635 
					   voltage,
2636 
					   si_pi->dyn_powertune_data.cac_leakage,
2637 
					   &leakage);
2638 
 
2639 
		smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640 
 
2641 
		if (smc_leakage > 0xFFFF)
2642 
			smc_leakage = 0xFFFF;
2643 
 
2644 
		for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 
			cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 
				cpu_to_be16((u16)smc_leakage);
2647 
	}
2648 
	return 0;
2649 
}
2650 
 
2651 
static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 
{
2653 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 
	struct si_power_info *si_pi = si_get_pi(rdev);
2655 
	PP_SIslands_CacConfig *cac_tables = NULL;
2656 
	u16 vddc_max, vddc_min, vddc_step;
2657 
	u16 t0, t_step;
2658 
	u32 load_line_slope, reg;
2659 
	int ret = 0;
2660 
	u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661 
 
2662 
	if (ni_pi->enable_cac == false)
2663 
		return 0;
2664 
 
2665 
	cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 
	if (!cac_tables)
2667 
		return -ENOMEM;
2668 
 
2669 
	reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 
	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 
	WREG32(CG_CAC_CTRL, reg);
2672 
 
2673 
	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 
	si_pi->dyn_powertune_data.dc_pwr_value =
2675 
		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 
	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 
	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678 
 
2679 
	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680 
 
2681 
	ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 
	if (ret)
2683 
		goto done_free;
2684 
 
2685 
	vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 
	vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 
	t_step = 4;
2688 
	t0 = 60;
2689 
 
2690 
	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 
		ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 
						vddc_max, vddc_min, vddc_step,
2693 
						t0, t_step);
2694 
	else
2695 
		ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 
						       vddc_max, vddc_min, vddc_step);
2697 
	if (ret)
2698 
		goto done_free;
2699 
 
2700 
	load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701 
 
2702 
	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 
	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 
	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 
	cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 
	cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 
	cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 
	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 
	cac_tables->calculation_repeats = cpu_to_be32(2);
2710 
	cac_tables->dc_cac = cpu_to_be32(0);
2711 
	cac_tables->log2_PG_LKG_SCALE = 12;
2712 
	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 
	cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 
	cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715 
 
2716 
	ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 
				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718 
 
2719 
	if (ret)
2720 
		goto done_free;
2721 
 
2722 
	ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723 
 
2724 
done_free:
2725 
	if (ret) {
2726 
		ni_pi->enable_cac = false;
2727 
		ni_pi->enable_power_containment = false;
2728 
	}
2729 
 
2730 
	kfree(cac_tables);
2731 
 
2732 
	return 0;
2733 
}
2734 
 
2735 
static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 
					   const struct si_cac_config_reg *cac_config_regs)
2737 
{
2738 
	const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 
	u32 data = 0, offset;
2740 
 
2741 
	if (!config_regs)
2742 
		return -EINVAL;
2743 
 
2744 
	while (config_regs->offset != 0xFFFFFFFF) {
2745 
		switch (config_regs->type) {
2746 
		case SISLANDS_CACCONFIG_CGIND:
2747 
			offset = SMC_CG_IND_START + config_regs->offset;
2748 
			if (offset < SMC_CG_IND_END)
2749 
				data = RREG32_SMC(offset);
2750 
			break;
2751 
		default:
2752 
			data = RREG32(config_regs->offset << 2);
2753 
			break;
2754 
		}
2755 
 
2756 
		data &= ~config_regs->mask;
2757 
		data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758 
 
2759 
		switch (config_regs->type) {
2760 
		case SISLANDS_CACCONFIG_CGIND:
2761 
			offset = SMC_CG_IND_START + config_regs->offset;
2762 
			if (offset < SMC_CG_IND_END)
2763 
				WREG32_SMC(offset, data);
2764 
			break;
2765 
		default:
2766 
			WREG32(config_regs->offset << 2, data);
2767 
			break;
2768 
		}
2769 
		config_regs++;
2770 
	}
2771 
	return 0;
2772 
}
2773 
 
2774 
static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 
{
2776 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 
	struct si_power_info *si_pi = si_get_pi(rdev);
2778 
	int ret;
2779 
 
2780 
	if ((ni_pi->enable_cac == false) ||
2781 
	    (ni_pi->cac_configuration_required == false))
2782 
		return 0;
2783 
 
2784 
	ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 
	if (ret)
2786 
		return ret;
2787 
	ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 
	if (ret)
2789 
		return ret;
2790 
	ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 
	if (ret)
2792 
		return ret;
2793 
 
2794 
	return 0;
2795 
}
2796 
 
2797 
static int si_enable_smc_cac(struct radeon_device *rdev,
2798 
			     struct radeon_ps *radeon_new_state,
2799 
			     bool enable)
2800 
{
2801 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 
	struct si_power_info *si_pi = si_get_pi(rdev);
2803 
	PPSMC_Result smc_result;
2804 
	int ret = 0;
2805 
 
2806 
	if (ni_pi->enable_cac) {
2807 
		if (enable) {
2808 
			if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 
				if (ni_pi->support_cac_long_term_average) {
2810 
					smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 
					if (smc_result != PPSMC_Result_OK)
2812 
						ni_pi->support_cac_long_term_average = false;
2813 
				}
2814 
 
2815 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 
				if (smc_result != PPSMC_Result_OK) {
2817 
					ret = -EINVAL;
2818 
					ni_pi->cac_enabled = false;
2819 
				} else {
2820 
					ni_pi->cac_enabled = true;
2821 
				}
2822 
 
2823 
				if (si_pi->enable_dte) {
2824 
					smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 
					if (smc_result != PPSMC_Result_OK)
2826 
						ret = -EINVAL;
2827 
				}
2828 
			}
2829 
		} else if (ni_pi->cac_enabled) {
2830 
			if (si_pi->enable_dte)
2831 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832 
 
2833 
			smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834 
 
2835 
			ni_pi->cac_enabled = false;
2836 
 
2837 
			if (ni_pi->support_cac_long_term_average)
2838 
				smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 
		}
2840 
	}
2841 
	return ret;
2842 
}
2843 
 
2844 
static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 
{
2846 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 
	struct si_power_info *si_pi = si_get_pi(rdev);
2848 
	SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 
	SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 
	u32 fb_div, p_div;
2851 
	u32 clk_s, clk_v;
2852 
	u32 sclk = 0;
2853 
	int ret = 0;
2854 
	u32 tmp;
2855 
	int i;
2856 
 
2857 
	if (si_pi->spll_table_start == 0)
2858 
		return -EINVAL;
2859 
 
2860 
	spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 
	if (spll_table == NULL)
2862 
		return -ENOMEM;
2863 
 
2864 
	for (i = 0; i < 256; i++) {
2865 
		ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 
		if (ret)
2867 
			break;
2868 
 
2869 
		p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 
		fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 
		clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 
		clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873 
 
2874 
		fb_div &= ~0x00001FFF;
2875 
		fb_div >>= 1;
2876 
		clk_v >>= 6;
2877 
 
2878 
		if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 
			ret = -EINVAL;
2880 
		if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 
			ret = -EINVAL;
2882 
		if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 
			ret = -EINVAL;
2884 
		if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 
			ret = -EINVAL;
2886 
 
2887 
		if (ret)
2888 
			break;
2889 
 
2890 
		tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 
			((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 
		spll_table->freq[i] = cpu_to_be32(tmp);
2893 
 
2894 
		tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 
			((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 
		spll_table->ss[i] = cpu_to_be32(tmp);
2897 
 
2898 
		sclk += 512;
2899 
	}
2900 
 
2901 
 
2902 
	if (!ret)
2903 
		ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 
					   (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 
					   si_pi->sram_end);
2906 
 
2907 
	if (ret)
2908 
		ni_pi->enable_power_containment = false;
2909 
 
2910 
	kfree(spll_table);
2911 
 
2912 
	return ret;
2913 
}
2914 
 
6104 serge 2915 
struct si_dpm_quirk {
2916 
	u32 chip_vendor;
2917 
	u32 chip_device;
2918 
	u32 subsys_vendor;
2919 
	u32 subsys_device;
2920 
	u32 max_sclk;
2921 
	u32 max_mclk;
2922 
};
2923 
 
2924 
/* cards with dpm stability problems */
2925 
static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 
	/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 
	{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 
	{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 
	{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2930 
	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2931 
	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2932 
	{ 0, 0, 0, 0 },
2933 
};
2934 
 
2935 
static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2936 
						   u16 vce_voltage)
2937 
{
2938 
	u16 highest_leakage = 0;
2939 
	struct si_power_info *si_pi = si_get_pi(rdev);
2940 
	int i;
2941 
 
2942 
	for (i = 0; i < si_pi->leakage_voltage.count; i++){
2943 
		if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2944 
			highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2945 
	}
2946 
 
2947 
	if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2948 
		return highest_leakage;
2949 
 
2950 
	return vce_voltage;
2951 
}
2952 
 
2953 
static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2954 
				    u32 evclk, u32 ecclk, u16 *voltage)
2955 
{
2956 
	u32 i;
2957 
	int ret = -EINVAL;
2958 
	struct radeon_vce_clock_voltage_dependency_table *table =
2959 
		&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2960 
 
2961 
	if (((evclk == 0) && (ecclk == 0)) ||
2962 
	    (table && (table->count == 0))) {
2963 
		*voltage = 0;
2964 
		return 0;
2965 
	}
2966 
 
2967 
	for (i = 0; i < table->count; i++) {
2968 
		if ((evclk <= table->entries[i].evclk) &&
2969 
		    (ecclk <= table->entries[i].ecclk)) {
2970 
			*voltage = table->entries[i].v;
2971 
			ret = 0;
2972 
			break;
2973 
		}
2974 
	}
2975 
 
2976 
	/* if no match return the highest voltage */
2977 
	if (ret)
2978 
		*voltage = table->entries[table->count - 1].v;
2979 
 
2980 
	*voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2981 
 
2982 
	return ret;
2983 
}
2984 
 
5078 serge 2985 
static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2986 
					struct radeon_ps *rps)
2987 
{
2988 
	struct ni_ps *ps = ni_get_ps(rps);
2989 
	struct radeon_clock_and_voltage_limits *max_limits;
2990 
	bool disable_mclk_switching = false;
2991 
	bool disable_sclk_switching = false;
2992 
	u32 mclk, sclk;
6104 serge 2993 
	u16 vddc, vddci, min_vce_voltage = 0;
5078 serge 2994 
	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
6104 serge 2995 
	u32 max_sclk = 0, max_mclk = 0;
5078 serge 2996 
	int i;
6104 serge 2997 
	struct si_dpm_quirk *p = si_dpm_quirk_list;
5078 serge 2998 
 
6104 serge 2999 
	/* Apply dpm quirks */
3000 
	while (p && p->chip_device != 0) {
3001 
		if (rdev->pdev->vendor == p->chip_vendor &&
3002 
		    rdev->pdev->device == p->chip_device &&
3003 
		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3004 
		    rdev->pdev->subsystem_device == p->subsys_device) {
3005 
			max_sclk = p->max_sclk;
3006 
			max_mclk = p->max_mclk;
3007 
			break;
3008 
		}
3009 
		++p;
3010 
	}
3011 
 
3012 
	if (rps->vce_active) {
3013 
		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3014 
		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3015 
		si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3016 
					 &min_vce_voltage);
3017 
	} else {
3018 
		rps->evclk = 0;
3019 
		rps->ecclk = 0;
3020 
	}
3021 
 
5078 serge 3022 
	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3023 
	    ni_dpm_vblank_too_short(rdev))
3024 
		disable_mclk_switching = true;
3025 
 
3026 
	if (rps->vclk || rps->dclk) {
3027 
		disable_mclk_switching = true;
3028 
		disable_sclk_switching = true;
3029 
	}
3030 
 
3031 
	if (rdev->pm.dpm.ac_power)
3032 
		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3033 
	else
3034 
		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3035 
 
3036 
	for (i = ps->performance_level_count - 2; i >= 0; i--) {
3037 
		if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3038 
			ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3039 
	}
3040 
	if (rdev->pm.dpm.ac_power == false) {
3041 
		for (i = 0; i < ps->performance_level_count; i++) {
3042 
			if (ps->performance_levels[i].mclk > max_limits->mclk)
3043 
				ps->performance_levels[i].mclk = max_limits->mclk;
3044 
			if (ps->performance_levels[i].sclk > max_limits->sclk)
3045 
				ps->performance_levels[i].sclk = max_limits->sclk;
3046 
			if (ps->performance_levels[i].vddc > max_limits->vddc)
3047 
				ps->performance_levels[i].vddc = max_limits->vddc;
3048 
			if (ps->performance_levels[i].vddci > max_limits->vddci)
3049 
				ps->performance_levels[i].vddci = max_limits->vddci;
3050 
		}
3051 
	}
3052 
 
3053 
	/* limit clocks to max supported clocks based on voltage dependency tables */
3054 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3055 
							&max_sclk_vddc);
3056 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3057 
							&max_mclk_vddci);
3058 
	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3059 
							&max_mclk_vddc);
3060 
 
3061 
	for (i = 0; i < ps->performance_level_count; i++) {
3062 
		if (max_sclk_vddc) {
3063 
			if (ps->performance_levels[i].sclk > max_sclk_vddc)
3064 
				ps->performance_levels[i].sclk = max_sclk_vddc;
3065 
		}
3066 
		if (max_mclk_vddci) {
3067 
			if (ps->performance_levels[i].mclk > max_mclk_vddci)
3068 
				ps->performance_levels[i].mclk = max_mclk_vddci;
3069 
		}
3070 
		if (max_mclk_vddc) {
3071 
			if (ps->performance_levels[i].mclk > max_mclk_vddc)
3072 
				ps->performance_levels[i].mclk = max_mclk_vddc;
3073 
		}
6104 serge 3074 
		if (max_mclk) {
3075 
			if (ps->performance_levels[i].mclk > max_mclk)
3076 
				ps->performance_levels[i].mclk = max_mclk;
3077 
		}
3078 
		if (max_sclk) {
3079 
			if (ps->performance_levels[i].sclk > max_sclk)
3080 
				ps->performance_levels[i].sclk = max_sclk;
3081 
		}
5078 serge 3082 
	}
3083 
 
3084 
	/* XXX validate the min clocks required for display */
3085 
 
3086 
	if (disable_mclk_switching) {
3087 
		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3088 
		vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3089 
	} else {
3090 
		mclk = ps->performance_levels[0].mclk;
3091 
		vddci = ps->performance_levels[0].vddci;
3092 
	}
3093 
 
3094 
	if (disable_sclk_switching) {
3095 
		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3096 
		vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3097 
	} else {
3098 
		sclk = ps->performance_levels[0].sclk;
3099 
		vddc = ps->performance_levels[0].vddc;
3100 
	}
3101 
 
6104 serge 3102 
	if (rps->vce_active) {
3103 
		if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3104 
			sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3105 
		if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3106 
			mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3107 
	}
3108 
 
5078 serge 3109 
	/* adjusted low state */
3110 
	ps->performance_levels[0].sclk = sclk;
3111 
	ps->performance_levels[0].mclk = mclk;
3112 
	ps->performance_levels[0].vddc = vddc;
3113 
	ps->performance_levels[0].vddci = vddci;
3114 
 
3115 
	if (disable_sclk_switching) {
3116 
		sclk = ps->performance_levels[0].sclk;
3117 
		for (i = 1; i < ps->performance_level_count; i++) {
3118 
			if (sclk < ps->performance_levels[i].sclk)
3119 
				sclk = ps->performance_levels[i].sclk;
3120 
		}
3121 
		for (i = 0; i < ps->performance_level_count; i++) {
3122 
			ps->performance_levels[i].sclk = sclk;
3123 
			ps->performance_levels[i].vddc = vddc;
3124 
		}
3125 
	} else {
3126 
		for (i = 1; i < ps->performance_level_count; i++) {
3127 
			if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3128 
				ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3129 
			if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3130 
				ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3131 
		}
3132 
	}
3133 
 
3134 
	if (disable_mclk_switching) {
3135 
		mclk = ps->performance_levels[0].mclk;
3136 
		for (i = 1; i < ps->performance_level_count; i++) {
3137 
			if (mclk < ps->performance_levels[i].mclk)
3138 
				mclk = ps->performance_levels[i].mclk;
3139 
		}
3140 
		for (i = 0; i < ps->performance_level_count; i++) {
3141 
			ps->performance_levels[i].mclk = mclk;
3142 
			ps->performance_levels[i].vddci = vddci;
3143 
		}
3144 
	} else {
3145 
		for (i = 1; i < ps->performance_level_count; i++) {
3146 
			if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3147 
				ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3148 
			if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3149 
				ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3150 
		}
3151 
	}
3152 
 
3153 
        for (i = 0; i < ps->performance_level_count; i++)
3154 
                btc_adjust_clock_combinations(rdev, max_limits,
3155 
                                              &ps->performance_levels[i]);
3156 
 
3157 
	for (i = 0; i < ps->performance_level_count; i++) {
6104 serge 3158 
		if (ps->performance_levels[i].vddc < min_vce_voltage)
3159 
			ps->performance_levels[i].vddc = min_vce_voltage;
5078 serge 3160 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3161 
						   ps->performance_levels[i].sclk,
3162 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3163 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3164 
						   ps->performance_levels[i].mclk,
3165 
						   max_limits->vddci, &ps->performance_levels[i].vddci);
3166 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3167 
						   ps->performance_levels[i].mclk,
3168 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3169 
		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3170 
						   rdev->clock.current_dispclk,
3171 
						   max_limits->vddc,  &ps->performance_levels[i].vddc);
3172 
	}
3173 
 
3174 
	for (i = 0; i < ps->performance_level_count; i++) {
3175 
		btc_apply_voltage_delta_rules(rdev,
3176 
					      max_limits->vddc, max_limits->vddci,
3177 
					      &ps->performance_levels[i].vddc,
3178 
					      &ps->performance_levels[i].vddci);
3179 
	}
3180 
 
3181 
	ps->dc_compatible = true;
3182 
	for (i = 0; i < ps->performance_level_count; i++) {
3183 
		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3184 
			ps->dc_compatible = false;
3185 
	}
3186 
}
3187 
 
3188 
#if 0
3189 
static int si_read_smc_soft_register(struct radeon_device *rdev,
3190 
				     u16 reg_offset, u32 *value)
3191 
{
3192 
	struct si_power_info *si_pi = si_get_pi(rdev);
3193 
 
3194 
	return si_read_smc_sram_dword(rdev,
3195 
				      si_pi->soft_regs_start + reg_offset, value,
3196 
				      si_pi->sram_end);
3197 
}
3198 
#endif
3199 
 
3200 
static int si_write_smc_soft_register(struct radeon_device *rdev,
3201 
				      u16 reg_offset, u32 value)
3202 
{
3203 
	struct si_power_info *si_pi = si_get_pi(rdev);
3204 
 
3205 
	return si_write_smc_sram_dword(rdev,
3206 
				       si_pi->soft_regs_start + reg_offset,
3207 
				       value, si_pi->sram_end);
3208 
}
3209 
 
3210 
static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3211 
{
3212 
	bool ret = false;
3213 
	u32 tmp, width, row, column, bank, density;
3214 
	bool is_memory_gddr5, is_special;
3215 
 
3216 
	tmp = RREG32(MC_SEQ_MISC0);
3217 
	is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3218 
	is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3219 
		& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3220 
 
3221 
	WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3222 
	width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3223 
 
3224 
	tmp = RREG32(MC_ARB_RAMCFG);
3225 
	row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3226 
	column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3227 
	bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3228 
 
3229 
	density = (1 << (row + column - 20 + bank)) * width;
3230 
 
3231 
	if ((rdev->pdev->device == 0x6819) &&
3232 
	    is_memory_gddr5 && is_special && (density == 0x400))
3233 
		ret = true;
3234 
 
3235 
	return ret;
3236 
}
3237 
 
3238 
static void si_get_leakage_vddc(struct radeon_device *rdev)
3239 
{
3240 
	struct si_power_info *si_pi = si_get_pi(rdev);
3241 
	u16 vddc, count = 0;
3242 
	int i, ret;
3243 
 
3244 
	for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3245 
		ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3246 
 
3247 
		if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3248 
			si_pi->leakage_voltage.entries[count].voltage = vddc;
3249 
			si_pi->leakage_voltage.entries[count].leakage_index =
3250 
				SISLANDS_LEAKAGE_INDEX0 + i;
3251 
			count++;
3252 
		}
3253 
	}
3254 
	si_pi->leakage_voltage.count = count;
3255 
}
3256 
 
3257 
static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3258 
						     u32 index, u16 *leakage_voltage)
3259 
{
3260 
	struct si_power_info *si_pi = si_get_pi(rdev);
3261 
	int i;
3262 
 
3263 
	if (leakage_voltage == NULL)
3264 
		return -EINVAL;
3265 
 
3266 
	if ((index & 0xff00) != 0xff00)
3267 
		return -EINVAL;
3268 
 
3269 
	if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3270 
		return -EINVAL;
3271 
 
3272 
	if (index < SISLANDS_LEAKAGE_INDEX0)
3273 
		return -EINVAL;
3274 
 
3275 
	for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3276 
		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3277 
			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3278 
			return 0;
3279 
		}
3280 
	}
3281 
	return -EAGAIN;
3282 
}
3283 
 
3284 
static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3285 
{
3286 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3287 
	bool want_thermal_protection;
3288 
	enum radeon_dpm_event_src dpm_event_src;
3289 
 
3290 
	switch (sources) {
3291 
	case 0:
3292 
	default:
3293 
		want_thermal_protection = false;
3294 
                break;
3295 
	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3296 
		want_thermal_protection = true;
3297 
		dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3298 
		break;
3299 
	case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3300 
		want_thermal_protection = true;
3301 
		dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3302 
		break;
3303 
	case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3304 
	      (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3305 
		want_thermal_protection = true;
3306 
		dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3307 
		break;
3308 
	}
3309 
 
3310 
	if (want_thermal_protection) {
3311 
		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3312 
		if (pi->thermal_protection)
3313 
			WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3314 
	} else {
3315 
		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3316 
	}
3317 
}
3318 
 
3319 
static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3320 
					   enum radeon_dpm_auto_throttle_src source,
3321 
					   bool enable)
3322 
{
3323 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3324 
 
3325 
	if (enable) {
3326 
		if (!(pi->active_auto_throttle_sources & (1 << source))) {
3327 
			pi->active_auto_throttle_sources |= 1 << source;
3328 
			si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3329 
		}
3330 
	} else {
3331 
		if (pi->active_auto_throttle_sources & (1 << source)) {
3332 
			pi->active_auto_throttle_sources &= ~(1 << source);
3333 
			si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3334 
		}
3335 
	}
3336 
}
3337 
 
3338 
static void si_start_dpm(struct radeon_device *rdev)
3339 
{
3340 
	WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3341 
}
3342 
 
3343 
static void si_stop_dpm(struct radeon_device *rdev)
3344 
{
3345 
	WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3346 
}
3347 
 
3348 
static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3349 
{
3350 
	if (enable)
3351 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3352 
	else
3353 
		WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3354 
 
3355 
}
3356 
 
3357 
#if 0
3358 
static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3359 
					       u32 thermal_level)
3360 
{
3361 
	PPSMC_Result ret;
3362 
 
3363 
	if (thermal_level == 0) {
3364 
		ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3365 
		if (ret == PPSMC_Result_OK)
3366 
			return 0;
3367 
		else
3368 
			return -EINVAL;
3369 
	}
3370 
	return 0;
3371 
}
3372 
 
3373 
static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3374 
{
3375 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3376 
}
3377 
#endif
3378 
 
3379 
#if 0
3380 
static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3381 
{
3382 
	if (ac_power)
3383 
		return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3384 
 
3385 
 
3386 
	return 0;
3387 
}
3388 
#endif
3389 
 
3390 
static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3391 
						      PPSMC_Msg msg, u32 parameter)
3392 
{
3393 
	WREG32(SMC_SCRATCH0, parameter);
3394 
	return si_send_msg_to_smc(rdev, msg);
3395 
}
3396 
 
3397 
static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3398 
{
3399 
	if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3400 
		return -EINVAL;
3401 
 
3402 
	return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3403 
 
3404 
}
3405 
 
3406 
int si_dpm_force_performance_level(struct radeon_device *rdev,
3407 
				   enum radeon_dpm_forced_level level)
3408 
{
3409 
	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3410 
	struct ni_ps *ps = ni_get_ps(rps);
3411 
	u32 levels = ps->performance_level_count;
3412 
 
3413 
	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3414 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3415 
			return -EINVAL;
3416 
 
3417 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3418 
			return -EINVAL;
3419 
	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3420 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3421 
			return -EINVAL;
3422 
 
3423 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3424 
			return -EINVAL;
3425 
	} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3426 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3427 
			return -EINVAL;
3428 
 
3429 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3430 
			return -EINVAL;
3431 
	}
3432 
 
3433 
	rdev->pm.dpm.forced_level = level;
3434 
 
3435 
	return 0;
3436 
}
3437 
 
6104 serge 3438 
#if 0
5078 serge 3439 
static int si_set_boot_state(struct radeon_device *rdev)
3440 
{
3441 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3442 
 
3443 
}
6104 serge 3444 
#endif
5078 serge 3445 
 
3446 
static int si_set_sw_state(struct radeon_device *rdev)
3447 
{
3448 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3449 
 
3450 
}
3451 
 
3452 
static int si_halt_smc(struct radeon_device *rdev)
3453 
{
3454 
	if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3455 
		return -EINVAL;
3456 
 
3457 
	return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3458 
 
3459 
}
3460 
 
3461 
static int si_resume_smc(struct radeon_device *rdev)
3462 
{
3463 
	if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3464 
		return -EINVAL;
3465 
 
3466 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3467 
 
3468 
}
3469 
 
3470 
static void si_dpm_start_smc(struct radeon_device *rdev)
3471 
{
3472 
	si_program_jump_on_start(rdev);
3473 
	si_start_smc(rdev);
3474 
	si_start_smc_clock(rdev);
3475 
}
3476 
 
3477 
static void si_dpm_stop_smc(struct radeon_device *rdev)
3478 
{
3479 
	si_reset_smc(rdev);
3480 
	si_stop_smc_clock(rdev);
3481 
}
3482 
 
3483 
static int si_process_firmware_header(struct radeon_device *rdev)
3484 
{
3485 
	struct si_power_info *si_pi = si_get_pi(rdev);
3486 
	u32 tmp;
3487 
	int ret;
3488 
 
3489 
	ret = si_read_smc_sram_dword(rdev,
3490 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3491 
				     SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3492 
				     &tmp, si_pi->sram_end);
3493 
	if (ret)
3494 
		return ret;
3495 
 
3496 
        si_pi->state_table_start = tmp;
3497 
 
3498 
	ret = si_read_smc_sram_dword(rdev,
3499 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3500 
				     SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3501 
				     &tmp, si_pi->sram_end);
3502 
	if (ret)
3503 
		return ret;
3504 
 
3505 
	si_pi->soft_regs_start = tmp;
3506 
 
3507 
	ret = si_read_smc_sram_dword(rdev,
3508 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3509 
				     SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3510 
				     &tmp, si_pi->sram_end);
3511 
	if (ret)
3512 
		return ret;
3513 
 
3514 
	si_pi->mc_reg_table_start = tmp;
3515 
 
3516 
	ret = si_read_smc_sram_dword(rdev,
3517 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
5271 serge 3518 
				     SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3519 
				     &tmp, si_pi->sram_end);
3520 
	if (ret)
3521 
		return ret;
3522 
 
3523 
	si_pi->fan_table_start = tmp;
3524 
 
3525 
	ret = si_read_smc_sram_dword(rdev,
3526 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
5078 serge 3527 
				     SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3528 
				     &tmp, si_pi->sram_end);
3529 
	if (ret)
3530 
		return ret;
3531 
 
3532 
	si_pi->arb_table_start = tmp;
3533 
 
3534 
	ret = si_read_smc_sram_dword(rdev,
3535 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3536 
				     SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3537 
				     &tmp, si_pi->sram_end);
3538 
	if (ret)
3539 
		return ret;
3540 
 
3541 
	si_pi->cac_table_start = tmp;
3542 
 
3543 
	ret = si_read_smc_sram_dword(rdev,
3544 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3545 
				     SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3546 
				     &tmp, si_pi->sram_end);
3547 
	if (ret)
3548 
		return ret;
3549 
 
3550 
	si_pi->dte_table_start = tmp;
3551 
 
3552 
	ret = si_read_smc_sram_dword(rdev,
3553 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3554 
				     SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3555 
				     &tmp, si_pi->sram_end);
3556 
	if (ret)
3557 
		return ret;
3558 
 
3559 
	si_pi->spll_table_start = tmp;
3560 
 
3561 
	ret = si_read_smc_sram_dword(rdev,
3562 
				     SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3563 
				     SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3564 
				     &tmp, si_pi->sram_end);
3565 
	if (ret)
3566 
		return ret;
3567 
 
3568 
	si_pi->papm_cfg_table_start = tmp;
3569 
 
3570 
	return ret;
3571 
}
3572 
 
3573 
static void si_read_clock_registers(struct radeon_device *rdev)
3574 
{
3575 
	struct si_power_info *si_pi = si_get_pi(rdev);
3576 
 
3577 
	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3578 
	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3579 
	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3580 
	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3581 
	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3582 
	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3583 
	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3584 
	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3585 
	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3586 
	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3587 
	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3588 
	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3589 
	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3590 
	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3591 
	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3592 
}
3593 
 
3594 
static void si_enable_thermal_protection(struct radeon_device *rdev,
3595 
					  bool enable)
3596 
{
3597 
	if (enable)
3598 
		WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3599 
	else
3600 
		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3601 
}
3602 
 
3603 
static void si_enable_acpi_power_management(struct radeon_device *rdev)
3604 
{
3605 
	WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3606 
}
3607 
 
3608 
#if 0
3609 
static int si_enter_ulp_state(struct radeon_device *rdev)
3610 
{
3611 
	WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3612 
 
3613 
	udelay(25000);
3614 
 
3615 
	return 0;
3616 
}
3617 
 
3618 
static int si_exit_ulp_state(struct radeon_device *rdev)
3619 
{
3620 
	int i;
3621 
 
3622 
	WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3623 
 
3624 
	udelay(7000);
3625 
 
3626 
	for (i = 0; i < rdev->usec_timeout; i++) {
3627 
		if (RREG32(SMC_RESP_0) == 1)
3628 
			break;
3629 
		udelay(1000);
3630 
	}
3631 
 
3632 
	return 0;
3633 
}
3634 
#endif
3635 
 
3636 
static int si_notify_smc_display_change(struct radeon_device *rdev,
3637 
				     bool has_display)
3638 
{
3639 
	PPSMC_Msg msg = has_display ?
3640 
		PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3641 
 
3642 
	return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3643 
 
3644 
}
3645 
 
3646 
static void si_program_response_times(struct radeon_device *rdev)
3647 
{
3648 
	u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3649 
	u32 vddc_dly, acpi_dly, vbi_dly;
3650 
	u32 reference_clock;
3651 
 
3652 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3653 
 
3654 
	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3655 
        backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3656 
 
3657 
	if (voltage_response_time == 0)
3658 
		voltage_response_time = 1000;
3659 
 
3660 
	acpi_delay_time = 15000;
3661 
	vbi_time_out = 100000;
3662 
 
3663 
	reference_clock = radeon_get_xclk(rdev);
3664 
 
3665 
	vddc_dly = (voltage_response_time  * reference_clock) / 100;
3666 
	acpi_dly = (acpi_delay_time * reference_clock) / 100;
3667 
	vbi_dly  = (vbi_time_out * reference_clock) / 100;
3668 
 
3669 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3670 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3671 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3672 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3673 
}
3674 
 
3675 
static void si_program_ds_registers(struct radeon_device *rdev)
3676 
{
3677 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3678 
	u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3679 
 
3680 
	if (eg_pi->sclk_deep_sleep) {
3681 
		WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3682 
		WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3683 
			 ~AUTOSCALE_ON_SS_CLEAR);
3684 
	}
3685 
}
3686 
 
3687 
static void si_program_display_gap(struct radeon_device *rdev)
3688 
{
3689 
	u32 tmp, pipe;
3690 
	int i;
3691 
 
3692 
	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3693 
	if (rdev->pm.dpm.new_active_crtc_count > 0)
3694 
		tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3695 
	else
3696 
		tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3697 
 
3698 
	if (rdev->pm.dpm.new_active_crtc_count > 1)
3699 
		tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3700 
	else
3701 
		tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3702 
 
3703 
	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3704 
 
3705 
	tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3706 
	pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3707 
 
3708 
	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3709 
	    (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3710 
		/* find the first active crtc */
3711 
		for (i = 0; i < rdev->num_crtc; i++) {
3712 
			if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3713 
				break;
3714 
		}
3715 
		if (i == rdev->num_crtc)
3716 
			pipe = 0;
3717 
		else
3718 
			pipe = i;
3719 
 
3720 
		tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3721 
		tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3722 
		WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3723 
	}
3724 
 
3725 
	/* Setting this to false forces the performance state to low if the crtcs are disabled.
3726 
	 * This can be a problem on PowerXpress systems or if you want to use the card
3727 
	 * for offscreen rendering or compute if there are no crtcs enabled.
3728 
	 */
3729 
	si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3730 
}
3731 
 
3732 
static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3733 
{
3734 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3735 
 
3736 
	if (enable) {
3737 
		if (pi->sclk_ss)
3738 
			WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3739 
	} else {
3740 
		WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3741 
		WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3742 
	}
3743 
}
3744 
 
3745 
static void si_setup_bsp(struct radeon_device *rdev)
3746 
{
3747 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3748 
	u32 xclk = radeon_get_xclk(rdev);
3749 
 
3750 
	r600_calculate_u_and_p(pi->asi,
3751 
			       xclk,
3752 
			       16,
3753 
			       &pi->bsp,
3754 
			       &pi->bsu);
3755 
 
3756 
	r600_calculate_u_and_p(pi->pasi,
3757 
			       xclk,
3758 
			       16,
3759 
			       &pi->pbsp,
3760 
			       &pi->pbsu);
3761 
 
3762 
 
3763 
        pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3764 
	pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3765 
 
3766 
	WREG32(CG_BSP, pi->dsp);
3767 
}
3768 
 
3769 
static void si_program_git(struct radeon_device *rdev)
3770 
{
3771 
	WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3772 
}
3773 
 
3774 
static void si_program_tp(struct radeon_device *rdev)
3775 
{
3776 
	int i;
3777 
	enum r600_td td = R600_TD_DFLT;
3778 
 
3779 
	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3780 
		WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3781 
 
3782 
	if (td == R600_TD_AUTO)
3783 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3784 
	else
3785 
		WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3786 
 
3787 
	if (td == R600_TD_UP)
3788 
		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3789 
 
3790 
	if (td == R600_TD_DOWN)
3791 
		WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3792 
}
3793 
 
3794 
static void si_program_tpp(struct radeon_device *rdev)
3795 
{
3796 
	WREG32(CG_TPC, R600_TPC_DFLT);
3797 
}
3798 
 
3799 
static void si_program_sstp(struct radeon_device *rdev)
3800 
{
3801 
	WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3802 
}
3803 
 
3804 
static void si_enable_display_gap(struct radeon_device *rdev)
3805 
{
3806 
	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3807 
 
3808 
	tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3809 
	tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3810 
		DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3811 
 
3812 
	tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3813 
	tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3814 
		DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3815 
	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3816 
}
3817 
 
3818 
static void si_program_vc(struct radeon_device *rdev)
3819 
{
3820 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3821 
 
3822 
	WREG32(CG_FTV, pi->vrc);
3823 
}
3824 
 
3825 
static void si_clear_vc(struct radeon_device *rdev)
3826 
{
3827 
	WREG32(CG_FTV, 0);
3828 
}
3829 
 
3830 
u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3831 
{
3832 
	u8 mc_para_index;
3833 
 
3834 
	if (memory_clock < 10000)
3835 
		mc_para_index = 0;
3836 
	else if (memory_clock >= 80000)
3837 
		mc_para_index = 0x0f;
3838 
	else
3839 
		mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3840 
	return mc_para_index;
3841 
}
3842 
 
3843 
u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3844 
{
3845 
	u8 mc_para_index;
3846 
 
3847 
	if (strobe_mode) {
3848 
		if (memory_clock < 12500)
3849 
			mc_para_index = 0x00;
3850 
		else if (memory_clock > 47500)
3851 
			mc_para_index = 0x0f;
3852 
		else
3853 
			mc_para_index = (u8)((memory_clock - 10000) / 2500);
3854 
	} else {
3855 
		if (memory_clock < 65000)
3856 
			mc_para_index = 0x00;
3857 
		else if (memory_clock > 135000)
3858 
			mc_para_index = 0x0f;
3859 
		else
3860 
			mc_para_index = (u8)((memory_clock - 60000) / 5000);
3861 
	}
3862 
	return mc_para_index;
3863 
}
3864 
 
3865 
static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3866 
{
3867 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3868 
	bool strobe_mode = false;
3869 
	u8 result = 0;
3870 
 
3871 
	if (mclk <= pi->mclk_strobe_mode_threshold)
3872 
		strobe_mode = true;
3873 
 
3874 
	if (pi->mem_gddr5)
3875 
		result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3876 
	else
3877 
		result = si_get_ddr3_mclk_frequency_ratio(mclk);
3878 
 
3879 
	if (strobe_mode)
3880 
		result |= SISLANDS_SMC_STROBE_ENABLE;
3881 
 
3882 
	return result;
3883 
}
3884 
 
3885 
static int si_upload_firmware(struct radeon_device *rdev)
3886 
{
3887 
	struct si_power_info *si_pi = si_get_pi(rdev);
3888 
	int ret;
3889 
 
3890 
	si_reset_smc(rdev);
3891 
	si_stop_smc_clock(rdev);
3892 
 
3893 
	ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3894 
 
3895 
	return ret;
3896 
}
3897 
 
3898 
static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3899 
					      const struct atom_voltage_table *table,
3900 
					      const struct radeon_phase_shedding_limits_table *limits)
3901 
{
3902 
	u32 data, num_bits, num_levels;
3903 
 
3904 
	if ((table == NULL) || (limits == NULL))
3905 
		return false;
3906 
 
3907 
	data = table->mask_low;
3908 
 
3909 
	num_bits = hweight32(data);
3910 
 
3911 
	if (num_bits == 0)
3912 
		return false;
3913 
 
3914 
	num_levels = (1 << num_bits);
3915 
 
3916 
	if (table->count != num_levels)
3917 
		return false;
3918 
 
3919 
	if (limits->count != (num_levels - 1))
3920 
		return false;
3921 
 
3922 
	return true;
3923 
}
3924 
 
3925 
void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3926 
					      u32 max_voltage_steps,
3927 
					      struct atom_voltage_table *voltage_table)
3928 
{
3929 
	unsigned int i, diff;
3930 
 
3931 
	if (voltage_table->count <= max_voltage_steps)
3932 
		return;
3933 
 
3934 
	diff = voltage_table->count - max_voltage_steps;
3935 
 
3936 
	for (i= 0; i < max_voltage_steps; i++)
3937 
		voltage_table->entries[i] = voltage_table->entries[i + diff];
3938 
 
3939 
	voltage_table->count = max_voltage_steps;
3940 
}
3941 
 
3942 
static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3943 
				     struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3944 
				     struct atom_voltage_table *voltage_table)
3945 
{
3946 
	u32 i;
3947 
 
3948 
	if (voltage_dependency_table == NULL)
3949 
		return -EINVAL;
3950 
 
3951 
	voltage_table->mask_low = 0;
3952 
	voltage_table->phase_delay = 0;
3953 
 
3954 
	voltage_table->count = voltage_dependency_table->count;
3955 
	for (i = 0; i < voltage_table->count; i++) {
3956 
		voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3957 
		voltage_table->entries[i].smio_low = 0;
3958 
	}
3959 
 
3960 
	return 0;
3961 
}
3962 
 
3963 
static int si_construct_voltage_tables(struct radeon_device *rdev)
3964 
{
3965 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3966 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3967 
	struct si_power_info *si_pi = si_get_pi(rdev);
3968 
	int ret;
3969 
 
3970 
	if (pi->voltage_control) {
3971 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3972 
						    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3973 
		if (ret)
3974 
			return ret;
3975 
 
3976 
		if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3977 
			si_trim_voltage_table_to_fit_state_table(rdev,
3978 
								 SISLANDS_MAX_NO_VREG_STEPS,
3979 
								 &eg_pi->vddc_voltage_table);
3980 
	} else if (si_pi->voltage_control_svi2) {
3981 
		ret = si_get_svi2_voltage_table(rdev,
3982 
						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3983 
						&eg_pi->vddc_voltage_table);
3984 
		if (ret)
3985 
			return ret;
3986 
	} else {
3987 
		return -EINVAL;
3988 
	}
3989 
 
3990 
	if (eg_pi->vddci_control) {
3991 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3992 
						    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3993 
		if (ret)
3994 
			return ret;
3995 
 
3996 
		if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3997 
			si_trim_voltage_table_to_fit_state_table(rdev,
3998 
								 SISLANDS_MAX_NO_VREG_STEPS,
3999 
								 &eg_pi->vddci_voltage_table);
4000 
	}
4001 
	if (si_pi->vddci_control_svi2) {
4002 
		ret = si_get_svi2_voltage_table(rdev,
4003 
						&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4004 
						&eg_pi->vddci_voltage_table);
4005 
		if (ret)
4006 
			return ret;
4007 
	}
4008 
 
4009 
	if (pi->mvdd_control) {
4010 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4011 
						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4012 
 
4013 
		if (ret) {
4014 
			pi->mvdd_control = false;
4015 
			return ret;
4016 
		}
4017 
 
4018 
		if (si_pi->mvdd_voltage_table.count == 0) {
4019 
			pi->mvdd_control = false;
4020 
			return -EINVAL;
4021 
		}
4022 
 
4023 
		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4024 
			si_trim_voltage_table_to_fit_state_table(rdev,
4025 
								 SISLANDS_MAX_NO_VREG_STEPS,
4026 
								 &si_pi->mvdd_voltage_table);
4027 
	}
4028 
 
4029 
	if (si_pi->vddc_phase_shed_control) {
4030 
		ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4031 
						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4032 
		if (ret)
4033 
			si_pi->vddc_phase_shed_control = false;
4034 
 
4035 
		if ((si_pi->vddc_phase_shed_table.count == 0) ||
4036 
		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4037 
			si_pi->vddc_phase_shed_control = false;
4038 
	}
4039 
 
4040 
	return 0;
4041 
}
4042 
 
4043 
static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4044 
					  const struct atom_voltage_table *voltage_table,
4045 
					  SISLANDS_SMC_STATETABLE *table)
4046 
{
4047 
	unsigned int i;
4048 
 
4049 
	for (i = 0; i < voltage_table->count; i++)
4050 
		table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4051 
}
4052 
 
4053 
static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4054 
					  SISLANDS_SMC_STATETABLE *table)
4055 
{
4056 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4057 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4058 
	struct si_power_info *si_pi = si_get_pi(rdev);
4059 
	u8 i;
4060 
 
4061 
	if (si_pi->voltage_control_svi2) {
4062 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4063 
			si_pi->svc_gpio_id);
4064 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4065 
			si_pi->svd_gpio_id);
4066 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4067 
					   2);
4068 
	} else {
4069 
		if (eg_pi->vddc_voltage_table.count) {
4070 
			si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4071 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4072 
				cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4073 
 
4074 
			for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4075 
				if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4076 
					table->maxVDDCIndexInPPTable = i;
4077 
					break;
4078 
				}
4079 
			}
4080 
		}
4081 
 
4082 
		if (eg_pi->vddci_voltage_table.count) {
4083 
			si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4084 
 
4085 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4086 
				cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4087 
		}
4088 
 
4089 
 
4090 
		if (si_pi->mvdd_voltage_table.count) {
4091 
			si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4092 
 
4093 
			table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4094 
				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4095 
		}
4096 
 
4097 
		if (si_pi->vddc_phase_shed_control) {
4098 
			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4099 
							      &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4100 
				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4101 
 
4102 
				table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4103 
					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4104 
 
4105 
				si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4106 
							   (u32)si_pi->vddc_phase_shed_table.phase_delay);
4107 
			} else {
4108 
				si_pi->vddc_phase_shed_control = false;
4109 
			}
4110 
		}
4111 
	}
4112 
 
4113 
	return 0;
4114 
}
4115 
 
4116 
static int si_populate_voltage_value(struct radeon_device *rdev,
4117 
				     const struct atom_voltage_table *table,
4118 
				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4119 
{
4120 
	unsigned int i;
4121 
 
4122 
	for (i = 0; i < table->count; i++) {
4123 
		if (value <= table->entries[i].value) {
4124 
			voltage->index = (u8)i;
4125 
			voltage->value = cpu_to_be16(table->entries[i].value);
4126 
			break;
4127 
		}
4128 
	}
4129 
 
4130 
	if (i >= table->count)
4131 
		return -EINVAL;
4132 
 
4133 
	return 0;
4134 
}
4135 
 
4136 
static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4137 
				  SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4138 
{
4139 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4140 
	struct si_power_info *si_pi = si_get_pi(rdev);
4141 
 
4142 
	if (pi->mvdd_control) {
4143 
		if (mclk <= pi->mvdd_split_frequency)
4144 
			voltage->index = 0;
4145 
		else
4146 
			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4147 
 
4148 
		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4149 
	}
4150 
	return 0;
4151 
}
4152 
 
4153 
static int si_get_std_voltage_value(struct radeon_device *rdev,
4154 
				    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4155 
				    u16 *std_voltage)
4156 
{
4157 
	u16 v_index;
4158 
	bool voltage_found = false;
4159 
	*std_voltage = be16_to_cpu(voltage->value);
4160 
 
4161 
	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4162 
		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4163 
			if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4164 
				return -EINVAL;
4165 
 
4166 
			for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4167 
				if (be16_to_cpu(voltage->value) ==
4168 
				    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4169 
					voltage_found = true;
4170 
					if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4171 
						*std_voltage =
4172 
							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4173 
					else
4174 
						*std_voltage =
4175 
							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4176 
					break;
4177 
				}
4178 
			}
4179 
 
4180 
			if (!voltage_found) {
4181 
				for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4182 
					if (be16_to_cpu(voltage->value) <=
4183 
					    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4184 
						voltage_found = true;
4185 
						if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4186 
							*std_voltage =
4187 
								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4188 
						else
4189 
							*std_voltage =
4190 
								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4191 
						break;
4192 
					}
4193 
				}
4194 
			}
4195 
		} else {
4196 
			if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4197 
				*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4198 
		}
4199 
	}
4200 
 
4201 
	return 0;
4202 
}
4203 
 
4204 
static int si_populate_std_voltage_value(struct radeon_device *rdev,
4205 
					 u16 value, u8 index,
4206 
					 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4207 
{
4208 
	voltage->index = index;
4209 
	voltage->value = cpu_to_be16(value);
4210 
 
4211 
	return 0;
4212 
}
4213 
 
4214 
static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4215 
					    const struct radeon_phase_shedding_limits_table *limits,
4216 
					    u16 voltage, u32 sclk, u32 mclk,
4217 
					    SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4218 
{
4219 
	unsigned int i;
4220 
 
4221 
	for (i = 0; i < limits->count; i++) {
4222 
		if ((voltage <= limits->entries[i].voltage) &&
4223 
		    (sclk <= limits->entries[i].sclk) &&
4224 
		    (mclk <= limits->entries[i].mclk))
4225 
			break;
4226 
	}
4227 
 
4228 
	smc_voltage->phase_settings = (u8)i;
4229 
 
4230 
	return 0;
4231 
}
4232 
 
4233 
static int si_init_arb_table_index(struct radeon_device *rdev)
4234 
{
4235 
	struct si_power_info *si_pi = si_get_pi(rdev);
4236 
	u32 tmp;
4237 
	int ret;
4238 
 
4239 
	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4240 
	if (ret)
4241 
		return ret;
4242 
 
4243 
	tmp &= 0x00FFFFFF;
4244 
	tmp |= MC_CG_ARB_FREQ_F1 << 24;
4245 
 
4246 
	return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4247 
}
4248 
 
4249 
static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4250 
{
4251 
	return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4252 
}
4253 
 
4254 
static int si_reset_to_default(struct radeon_device *rdev)
4255 
{
4256 
	return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4257 
 
4258 
}
4259 
 
4260 
static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4261 
{
4262 
	struct si_power_info *si_pi = si_get_pi(rdev);
4263 
	u32 tmp;
4264 
	int ret;
4265 
 
4266 
	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4267 
				     &tmp, si_pi->sram_end);
4268 
	if (ret)
4269 
		return ret;
4270 
 
4271 
	tmp = (tmp >> 24) & 0xff;
4272 
 
4273 
	if (tmp == MC_CG_ARB_FREQ_F0)
4274 
		return 0;
4275 
 
4276 
	return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4277 
}
4278 
 
4279 
static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4280 
					    u32 engine_clock)
4281 
{
4282 
	u32 dram_rows;
4283 
	u32 dram_refresh_rate;
4284 
	u32 mc_arb_rfsh_rate;
4285 
	u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4286 
 
4287 
	if (tmp >= 4)
4288 
		dram_rows = 16384;
4289 
	else
4290 
		dram_rows = 1 << (tmp + 10);
4291 
 
4292 
	dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4293 
	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4294 
 
4295 
	return mc_arb_rfsh_rate;
4296 
}
4297 
 
4298 
static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4299 
						struct rv7xx_pl *pl,
4300 
						SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4301 
{
4302 
	u32 dram_timing;
4303 
	u32 dram_timing2;
4304 
	u32 burst_time;
4305 
 
4306 
	arb_regs->mc_arb_rfsh_rate =
4307 
		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4308 
 
4309 
	radeon_atom_set_engine_dram_timings(rdev,
4310 
					    pl->sclk,
4311 
                                            pl->mclk);
4312 
 
4313 
	dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4314 
	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4315 
	burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4316 
 
4317 
	arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4318 
	arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4319 
	arb_regs->mc_arb_burst_time = (u8)burst_time;
4320 
 
4321 
	return 0;
4322 
}
4323 
 
4324 
static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4325 
						  struct radeon_ps *radeon_state,
4326 
						  unsigned int first_arb_set)
4327 
{
4328 
	struct si_power_info *si_pi = si_get_pi(rdev);
4329 
	struct ni_ps *state = ni_get_ps(radeon_state);
4330 
	SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4331 
	int i, ret = 0;
4332 
 
4333 
	for (i = 0; i < state->performance_level_count; i++) {
4334 
		ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4335 
		if (ret)
4336 
			break;
4337 
		ret = si_copy_bytes_to_smc(rdev,
4338 
					   si_pi->arb_table_start +
4339 
					   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4340 
					   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4341 
					   (u8 *)&arb_regs,
4342 
					   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4343 
					   si_pi->sram_end);
4344 
		if (ret)
4345 
			break;
4346 
        }
4347 
 
4348 
	return ret;
4349 
}
4350 
 
4351 
static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4352 
					       struct radeon_ps *radeon_new_state)
4353 
{
4354 
	return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4355 
						      SISLANDS_DRIVER_STATE_ARB_INDEX);
4356 
}
4357 
 
4358 
static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4359 
					  struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4360 
{
4361 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4362 
	struct si_power_info *si_pi = si_get_pi(rdev);
4363 
 
4364 
	if (pi->mvdd_control)
4365 
		return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4366 
						 si_pi->mvdd_bootup_value, voltage);
4367 
 
4368 
	return 0;
4369 
}
4370 
 
4371 
static int si_populate_smc_initial_state(struct radeon_device *rdev,
4372 
					 struct radeon_ps *radeon_initial_state,
4373 
					 SISLANDS_SMC_STATETABLE *table)
4374 
{
4375 
	struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4376 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4377 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4378 
	struct si_power_info *si_pi = si_get_pi(rdev);
4379 
	u32 reg;
4380 
	int ret;
4381 
 
4382 
	table->initialState.levels[0].mclk.vDLL_CNTL =
4383 
		cpu_to_be32(si_pi->clock_registers.dll_cntl);
4384 
	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4385 
		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4386 
	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4387 
		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4388 
	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4389 
		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4390 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4391 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4392 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4393 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4394 
	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4395 
		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4396 
	table->initialState.levels[0].mclk.vMPLL_SS =
4397 
		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4398 
	table->initialState.levels[0].mclk.vMPLL_SS2 =
4399 
		cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4400 
 
4401 
	table->initialState.levels[0].mclk.mclk_value =
4402 
		cpu_to_be32(initial_state->performance_levels[0].mclk);
4403 
 
4404 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4405 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4406 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4407 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4408 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4409 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4410 
	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4411 
		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4412 
	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4413 
		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4414 
	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4415 
		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4416 
 
4417 
	table->initialState.levels[0].sclk.sclk_value =
4418 
		cpu_to_be32(initial_state->performance_levels[0].sclk);
4419 
 
4420 
	table->initialState.levels[0].arbRefreshState =
4421 
		SISLANDS_INITIAL_STATE_ARB_INDEX;
4422 
 
4423 
	table->initialState.levels[0].ACIndex = 0;
4424 
 
4425 
	ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4426 
					initial_state->performance_levels[0].vddc,
4427 
					&table->initialState.levels[0].vddc);
4428 
 
4429 
	if (!ret) {
4430 
		u16 std_vddc;
4431 
 
4432 
		ret = si_get_std_voltage_value(rdev,
4433 
					       &table->initialState.levels[0].vddc,
4434 
					       &std_vddc);
4435 
		if (!ret)
4436 
			si_populate_std_voltage_value(rdev, std_vddc,
4437 
						      table->initialState.levels[0].vddc.index,
4438 
						      &table->initialState.levels[0].std_vddc);
4439 
	}
4440 
 
4441 
	if (eg_pi->vddci_control)
4442 
		si_populate_voltage_value(rdev,
4443 
					  &eg_pi->vddci_voltage_table,
4444 
					  initial_state->performance_levels[0].vddci,
4445 
					  &table->initialState.levels[0].vddci);
4446 
 
4447 
	if (si_pi->vddc_phase_shed_control)
4448 
		si_populate_phase_shedding_value(rdev,
4449 
						 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4450 
						 initial_state->performance_levels[0].vddc,
4451 
						 initial_state->performance_levels[0].sclk,
4452 
						 initial_state->performance_levels[0].mclk,
4453 
						 &table->initialState.levels[0].vddc);
4454 
 
4455 
	si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4456 
 
4457 
	reg = CG_R(0xffff) | CG_L(0);
4458 
	table->initialState.levels[0].aT = cpu_to_be32(reg);
4459 
 
4460 
	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4461 
 
4462 
	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4463 
 
4464 
	if (pi->mem_gddr5) {
4465 
		table->initialState.levels[0].strobeMode =
4466 
			si_get_strobe_mode_settings(rdev,
4467 
						    initial_state->performance_levels[0].mclk);
4468 
 
4469 
		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4470 
			table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4471 
		else
4472 
			table->initialState.levels[0].mcFlags =  0;
4473 
	}
4474 
 
4475 
	table->initialState.levelCount = 1;
4476 
 
4477 
	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4478 
 
4479 
	table->initialState.levels[0].dpm2.MaxPS = 0;
4480 
	table->initialState.levels[0].dpm2.NearTDPDec = 0;
4481 
	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4482 
	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4483 
	table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4484 
 
4485 
	reg = MIN_POWER_MASK | MAX_POWER_MASK;
4486 
	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4487 
 
4488 
	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4489 
	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4490 
 
4491 
	return 0;
4492 
}
4493 
 
4494 
static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4495 
				      SISLANDS_SMC_STATETABLE *table)
4496 
{
4497 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4498 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4499 
	struct si_power_info *si_pi = si_get_pi(rdev);
4500 
	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4501 
	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4502 
	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4503 
	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4504 
	u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4505 
	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4506 
	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4507 
	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4508 
	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4509 
	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4510 
	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4511 
	u32 reg;
4512 
	int ret;
4513 
 
4514 
	table->ACPIState = table->initialState;
4515 
 
4516 
	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4517 
 
4518 
	if (pi->acpi_vddc) {
4519 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4520 
						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4521 
		if (!ret) {
4522 
			u16 std_vddc;
4523 
 
4524 
			ret = si_get_std_voltage_value(rdev,
4525 
						       &table->ACPIState.levels[0].vddc, &std_vddc);
4526 
			if (!ret)
4527 
				si_populate_std_voltage_value(rdev, std_vddc,
4528 
							      table->ACPIState.levels[0].vddc.index,
4529 
							      &table->ACPIState.levels[0].std_vddc);
4530 
		}
4531 
		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4532 
 
4533 
		if (si_pi->vddc_phase_shed_control) {
4534 
			si_populate_phase_shedding_value(rdev,
4535 
							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4536 
							 pi->acpi_vddc,
4537 
							 0,
4538 
							 0,
4539 
							 &table->ACPIState.levels[0].vddc);
4540 
		}
4541 
	} else {
4542 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4543 
						pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4544 
		if (!ret) {
4545 
			u16 std_vddc;
4546 
 
4547 
			ret = si_get_std_voltage_value(rdev,
4548 
						       &table->ACPIState.levels[0].vddc, &std_vddc);
4549 
 
4550 
			if (!ret)
4551 
				si_populate_std_voltage_value(rdev, std_vddc,
4552 
							      table->ACPIState.levels[0].vddc.index,
4553 
							      &table->ACPIState.levels[0].std_vddc);
4554 
		}
4555 
		table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4556 
										    si_pi->sys_pcie_mask,
4557 
										    si_pi->boot_pcie_gen,
4558 
										    RADEON_PCIE_GEN1);
4559 
 
4560 
		if (si_pi->vddc_phase_shed_control)
4561 
			si_populate_phase_shedding_value(rdev,
4562 
							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4563 
							 pi->min_vddc_in_table,
4564 
							 0,
4565 
							 0,
4566 
							 &table->ACPIState.levels[0].vddc);
4567 
	}
4568 
 
4569 
	if (pi->acpi_vddc) {
4570 
		if (eg_pi->acpi_vddci)
4571 
			si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4572 
						  eg_pi->acpi_vddci,
4573 
						  &table->ACPIState.levels[0].vddci);
4574 
	}
4575 
 
4576 
	mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4577 
	mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4578 
 
4579 
	dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4580 
 
4581 
	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4582 
	spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4583 
 
4584 
	table->ACPIState.levels[0].mclk.vDLL_CNTL =
4585 
		cpu_to_be32(dll_cntl);
4586 
	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4587 
		cpu_to_be32(mclk_pwrmgt_cntl);
4588 
	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4589 
		cpu_to_be32(mpll_ad_func_cntl);
4590 
	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4591 
		cpu_to_be32(mpll_dq_func_cntl);
4592 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4593 
		cpu_to_be32(mpll_func_cntl);
4594 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4595 
		cpu_to_be32(mpll_func_cntl_1);
4596 
	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4597 
		cpu_to_be32(mpll_func_cntl_2);
4598 
	table->ACPIState.levels[0].mclk.vMPLL_SS =
4599 
		cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4600 
	table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4601 
		cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4602 
 
4603 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4604 
		cpu_to_be32(spll_func_cntl);
4605 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4606 
		cpu_to_be32(spll_func_cntl_2);
4607 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4608 
		cpu_to_be32(spll_func_cntl_3);
4609 
	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4610 
		cpu_to_be32(spll_func_cntl_4);
4611 
 
4612 
	table->ACPIState.levels[0].mclk.mclk_value = 0;
4613 
	table->ACPIState.levels[0].sclk.sclk_value = 0;
4614 
 
4615 
	si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4616 
 
4617 
	if (eg_pi->dynamic_ac_timing)
4618 
		table->ACPIState.levels[0].ACIndex = 0;
4619 
 
4620 
	table->ACPIState.levels[0].dpm2.MaxPS = 0;
4621 
	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4622 
	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4623 
	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4624 
	table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4625 
 
4626 
	reg = MIN_POWER_MASK | MAX_POWER_MASK;
4627 
	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4628 
 
4629 
	reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4630 
	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4631 
 
4632 
	return 0;
4633 
}
4634 
 
4635 
static int si_populate_ulv_state(struct radeon_device *rdev,
4636 
				 SISLANDS_SMC_SWSTATE *state)
4637 
{
4638 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4639 
	struct si_power_info *si_pi = si_get_pi(rdev);
4640 
	struct si_ulv_param *ulv = &si_pi->ulv;
4641 
	u32 sclk_in_sr = 1350; /* ??? */
4642 
	int ret;
4643 
 
4644 
	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4645 
					    &state->levels[0]);
4646 
	if (!ret) {
4647 
		if (eg_pi->sclk_deep_sleep) {
4648 
			if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4649 
				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4650 
			else
4651 
				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4652 
		}
4653 
		if (ulv->one_pcie_lane_in_ulv)
4654 
			state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4655 
		state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4656 
		state->levels[0].ACIndex = 1;
4657 
		state->levels[0].std_vddc = state->levels[0].vddc;
4658 
		state->levelCount = 1;
4659 
 
4660 
		state->flags |= PPSMC_SWSTATE_FLAG_DC;
4661 
	}
4662 
 
4663 
	return ret;
4664 
}
4665 
 
4666 
static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4667 
{
4668 
	struct si_power_info *si_pi = si_get_pi(rdev);
4669 
	struct si_ulv_param *ulv = &si_pi->ulv;
4670 
	SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4671 
	int ret;
4672 
 
4673 
	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4674 
						   &arb_regs);
4675 
	if (ret)
4676 
		return ret;
4677 
 
4678 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4679 
				   ulv->volt_change_delay);
4680 
 
4681 
	ret = si_copy_bytes_to_smc(rdev,
4682 
				   si_pi->arb_table_start +
4683 
				   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4684 
				   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4685 
				   (u8 *)&arb_regs,
4686 
				   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4687 
				   si_pi->sram_end);
4688 
 
4689 
	return ret;
4690 
}
4691 
 
4692 
static void si_get_mvdd_configuration(struct radeon_device *rdev)
4693 
{
4694 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4695 
 
4696 
	pi->mvdd_split_frequency = 30000;
4697 
}
4698 
 
4699 
static int si_init_smc_table(struct radeon_device *rdev)
4700 
{
4701 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4702 
	struct si_power_info *si_pi = si_get_pi(rdev);
4703 
	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4704 
	const struct si_ulv_param *ulv = &si_pi->ulv;
4705 
	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4706 
	int ret;
4707 
	u32 lane_width;
4708 
	u32 vr_hot_gpio;
4709 
 
4710 
	si_populate_smc_voltage_tables(rdev, table);
4711 
 
4712 
	switch (rdev->pm.int_thermal_type) {
4713 
	case THERMAL_TYPE_SI:
4714 
	case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4715 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4716 
		break;
4717 
	case THERMAL_TYPE_NONE:
4718 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4719 
		break;
4720 
	default:
4721 
		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4722 
		break;
4723 
	}
4724 
 
4725 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4726 
		table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4727 
 
4728 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4729 
		if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4730 
			table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4731 
	}
4732 
 
4733 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4734 
		table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4735 
 
4736 
	if (pi->mem_gddr5)
4737 
		table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4738 
 
4739 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4740 
		table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4741 
 
4742 
	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4743 
		table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4744 
		vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4745 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4746 
					   vr_hot_gpio);
4747 
	}
4748 
 
4749 
	ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4750 
	if (ret)
4751 
		return ret;
4752 
 
4753 
	ret = si_populate_smc_acpi_state(rdev, table);
4754 
	if (ret)
4755 
		return ret;
4756 
 
4757 
	table->driverState = table->initialState;
4758 
 
4759 
	ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4760 
						     SISLANDS_INITIAL_STATE_ARB_INDEX);
4761 
	if (ret)
4762 
		return ret;
4763 
 
4764 
	if (ulv->supported && ulv->pl.vddc) {
4765 
		ret = si_populate_ulv_state(rdev, &table->ULVState);
4766 
		if (ret)
4767 
			return ret;
4768 
 
4769 
		ret = si_program_ulv_memory_timing_parameters(rdev);
4770 
		if (ret)
4771 
			return ret;
4772 
 
4773 
		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4774 
		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4775 
 
4776 
		lane_width = radeon_get_pcie_lanes(rdev);
4777 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4778 
	} else {
4779 
		table->ULVState = table->initialState;
4780 
	}
4781 
 
4782 
	return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4783 
				    (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4784 
				    si_pi->sram_end);
4785 
}
4786 
 
4787 
static int si_calculate_sclk_params(struct radeon_device *rdev,
4788 
				    u32 engine_clock,
4789 
				    SISLANDS_SMC_SCLK_VALUE *sclk)
4790 
{
4791 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4792 
	struct si_power_info *si_pi = si_get_pi(rdev);
4793 
	struct atom_clock_dividers dividers;
4794 
	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4795 
	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4796 
	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4797 
	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4798 
	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4799 
	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4800 
	u64 tmp;
4801 
	u32 reference_clock = rdev->clock.spll.reference_freq;
4802 
	u32 reference_divider;
4803 
	u32 fbdiv;
4804 
	int ret;
4805 
 
4806 
	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4807 
					     engine_clock, false, ÷rs);
4808 
	if (ret)
4809 
		return ret;
4810 
 
4811 
	reference_divider = 1 + dividers.ref_div;
4812 
 
4813 
	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4814 
	do_div(tmp, reference_clock);
4815 
	fbdiv = (u32) tmp;
4816 
 
4817 
	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4818 
	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4819 
	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4820 
 
4821 
	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4822 
	spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4823 
 
4824 
        spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4825 
        spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4826 
        spll_func_cntl_3 |= SPLL_DITHEN;
4827 
 
4828 
	if (pi->sclk_ss) {
4829 
		struct radeon_atom_ss ss;
4830 
		u32 vco_freq = engine_clock * dividers.post_div;
4831 
 
4832 
		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4833 
						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4834 
			u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4835 
			u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4836 
 
4837 
			cg_spll_spread_spectrum &= ~CLK_S_MASK;
4838 
			cg_spll_spread_spectrum |= CLK_S(clk_s);
4839 
			cg_spll_spread_spectrum |= SSEN;
4840 
 
4841 
			cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4842 
			cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4843 
		}
4844 
	}
4845 
 
4846 
	sclk->sclk_value = engine_clock;
4847 
	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4848 
	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4849 
	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4850 
	sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4851 
	sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4852 
	sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4853 
 
4854 
	return 0;
4855 
}
4856 
 
4857 
static int si_populate_sclk_value(struct radeon_device *rdev,
4858 
				  u32 engine_clock,
4859 
				  SISLANDS_SMC_SCLK_VALUE *sclk)
4860 
{
4861 
	SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4862 
	int ret;
4863 
 
4864 
	ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4865 
	if (!ret) {
4866 
		sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4867 
		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4868 
		sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4869 
		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4870 
		sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4871 
		sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4872 
		sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4873 
	}
4874 
 
4875 
	return ret;
4876 
}
4877 
 
4878 
static int si_populate_mclk_value(struct radeon_device *rdev,
4879 
				  u32 engine_clock,
4880 
				  u32 memory_clock,
4881 
				  SISLANDS_SMC_MCLK_VALUE *mclk,
4882 
				  bool strobe_mode,
4883 
				  bool dll_state_on)
4884 
{
4885 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4886 
	struct si_power_info *si_pi = si_get_pi(rdev);
4887 
	u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4888 
	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4889 
	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4890 
	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4891 
	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4892 
	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4893 
	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4894 
	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4895 
	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4896 
	struct atom_mpll_param mpll_param;
4897 
	int ret;
4898 
 
4899 
	ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4900 
	if (ret)
4901 
		return ret;
4902 
 
4903 
	mpll_func_cntl &= ~BWCTRL_MASK;
4904 
	mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4905 
 
4906 
	mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4907 
	mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4908 
		CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4909 
 
4910 
	mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4911 
	mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4912 
 
4913 
	if (pi->mem_gddr5) {
4914 
		mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4915 
		mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4916 
			YCLK_POST_DIV(mpll_param.post_div);
4917 
	}
4918 
 
4919 
	if (pi->mclk_ss) {
4920 
		struct radeon_atom_ss ss;
4921 
		u32 freq_nom;
4922 
		u32 tmp;
4923 
		u32 reference_clock = rdev->clock.mpll.reference_freq;
4924 
 
4925 
		if (pi->mem_gddr5)
4926 
			freq_nom = memory_clock * 4;
4927 
		else
4928 
			freq_nom = memory_clock * 2;
4929 
 
4930 
		tmp = freq_nom / reference_clock;
4931 
		tmp = tmp * tmp;
4932 
		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4933 
                                                     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4934 
			u32 clks = reference_clock * 5 / ss.rate;
4935 
			u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4936 
 
4937 
                        mpll_ss1 &= ~CLKV_MASK;
4938 
                        mpll_ss1 |= CLKV(clkv);
4939 
 
4940 
                        mpll_ss2 &= ~CLKS_MASK;
4941 
                        mpll_ss2 |= CLKS(clks);
4942 
		}
4943 
	}
4944 
 
4945 
	mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4946 
	mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4947 
 
4948 
	if (dll_state_on)
4949 
		mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4950 
	else
4951 
		mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4952 
 
4953 
	mclk->mclk_value = cpu_to_be32(memory_clock);
4954 
	mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4955 
	mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4956 
	mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4957 
	mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4958 
	mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4959 
	mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4960 
	mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4961 
	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4962 
	mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4963 
 
4964 
	return 0;
4965 
}
4966 
 
4967 
static void si_populate_smc_sp(struct radeon_device *rdev,
4968 
			       struct radeon_ps *radeon_state,
4969 
			       SISLANDS_SMC_SWSTATE *smc_state)
4970 
{
4971 
	struct ni_ps *ps = ni_get_ps(radeon_state);
4972 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4973 
	int i;
4974 
 
4975 
	for (i = 0; i < ps->performance_level_count - 1; i++)
4976 
		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4977 
 
4978 
	smc_state->levels[ps->performance_level_count - 1].bSP =
4979 
		cpu_to_be32(pi->psp);
4980 
}
4981 
 
4982 
static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4983 
					 struct rv7xx_pl *pl,
4984 
					 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4985 
{
4986 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4987 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4988 
	struct si_power_info *si_pi = si_get_pi(rdev);
4989 
	int ret;
4990 
	bool dll_state_on;
4991 
	u16 std_vddc;
4992 
	bool gmc_pg = false;
4993 
 
4994 
	if (eg_pi->pcie_performance_request &&
4995 
	    (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4996 
		level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4997 
	else
4998 
		level->gen2PCIE = (u8)pl->pcie_gen;
4999 
 
5000 
	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5001 
	if (ret)
5002 
		return ret;
5003 
 
5004 
	level->mcFlags =  0;
5005 
 
5006 
	if (pi->mclk_stutter_mode_threshold &&
5007 
	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5008 
	    !eg_pi->uvd_enabled &&
5009 
	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5010 
	    (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5011 
		level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5012 
 
5013 
		if (gmc_pg)
5014 
			level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5015 
	}
5016 
 
5017 
	if (pi->mem_gddr5) {
5018 
		if (pl->mclk > pi->mclk_edc_enable_threshold)
5019 
			level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5020 
 
5021 
		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5022 
			level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5023 
 
5024 
		level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5025 
 
5026 
		if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5027 
			if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5028 
			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5029 
				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5030 
			else
5031 
				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5032 
		} else {
5033 
			dll_state_on = false;
5034 
		}
5035 
	} else {
5036 
		level->strobeMode = si_get_strobe_mode_settings(rdev,
5037 
								pl->mclk);
5038 
 
5039 
		dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5040 
	}
5041 
 
5042 
	ret = si_populate_mclk_value(rdev,
5043 
				     pl->sclk,
5044 
				     pl->mclk,
5045 
				     &level->mclk,
5046 
				     (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5047 
	if (ret)
5048 
		return ret;
5049 
 
5050 
	ret = si_populate_voltage_value(rdev,
5051 
					&eg_pi->vddc_voltage_table,
5052 
					pl->vddc, &level->vddc);
5053 
	if (ret)
5054 
		return ret;
5055 
 
5056 
 
5057 
	ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5058 
	if (ret)
5059 
		return ret;
5060 
 
5061 
	ret = si_populate_std_voltage_value(rdev, std_vddc,
5062 
					    level->vddc.index, &level->std_vddc);
5063 
	if (ret)
5064 
		return ret;
5065 
 
5066 
	if (eg_pi->vddci_control) {
5067 
		ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5068 
						pl->vddci, &level->vddci);
5069 
		if (ret)
5070 
			return ret;
5071 
	}
5072 
 
5073 
	if (si_pi->vddc_phase_shed_control) {
5074 
		ret = si_populate_phase_shedding_value(rdev,
5075 
						       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5076 
						       pl->vddc,
5077 
						       pl->sclk,
5078 
						       pl->mclk,
5079 
						       &level->vddc);
5080 
		if (ret)
5081 
			return ret;
5082 
	}
5083 
 
5084 
	level->MaxPoweredUpCU = si_pi->max_cu;
5085 
 
5086 
	ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5087 
 
5088 
	return ret;
5089 
}
5090 
 
5091 
static int si_populate_smc_t(struct radeon_device *rdev,
5092 
			     struct radeon_ps *radeon_state,
5093 
			     SISLANDS_SMC_SWSTATE *smc_state)
5094 
{
5095 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5096 
	struct ni_ps *state = ni_get_ps(radeon_state);
5097 
	u32 a_t;
5098 
	u32 t_l, t_h;
5099 
	u32 high_bsp;
5100 
	int i, ret;
5101 
 
5102 
	if (state->performance_level_count >= 9)
5103 
		return -EINVAL;
5104 
 
5105 
	if (state->performance_level_count < 2) {
5106 
		a_t = CG_R(0xffff) | CG_L(0);
5107 
		smc_state->levels[0].aT = cpu_to_be32(a_t);
5108 
		return 0;
5109 
	}
5110 
 
5111 
	smc_state->levels[0].aT = cpu_to_be32(0);
5112 
 
5113 
	for (i = 0; i <= state->performance_level_count - 2; i++) {
5114 
		ret = r600_calculate_at(
5115 
			(50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5116 
			100 * R600_AH_DFLT,
5117 
			state->performance_levels[i + 1].sclk,
5118 
			state->performance_levels[i].sclk,
5119 
			&t_l,
5120 
			&t_h);
5121 
 
5122 
		if (ret) {
5123 
			t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5124 
			t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5125 
		}
5126 
 
5127 
		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5128 
		a_t |= CG_R(t_l * pi->bsp / 20000);
5129 
		smc_state->levels[i].aT = cpu_to_be32(a_t);
5130 
 
5131 
		high_bsp = (i == state->performance_level_count - 2) ?
5132 
			pi->pbsp : pi->bsp;
5133 
		a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5134 
		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5135 
	}
5136 
 
5137 
	return 0;
5138 
}
5139 
 
5140 
static int si_disable_ulv(struct radeon_device *rdev)
5141 
{
5142 
	struct si_power_info *si_pi = si_get_pi(rdev);
5143 
	struct si_ulv_param *ulv = &si_pi->ulv;
5144 
 
5145 
	if (ulv->supported)
5146 
		return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5147 
 
5148 
 
5149 
	return 0;
5150 
}
5151 
 
5152 
static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5153 
				       struct radeon_ps *radeon_state)
5154 
{
5155 
	const struct si_power_info *si_pi = si_get_pi(rdev);
5156 
	const struct si_ulv_param *ulv = &si_pi->ulv;
5157 
	const struct ni_ps *state = ni_get_ps(radeon_state);
5158 
	int i;
5159 
 
5160 
	if (state->performance_levels[0].mclk != ulv->pl.mclk)
5161 
		return false;
5162 
 
5163 
	/* XXX validate against display requirements! */
5164 
 
5165 
	for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5166 
		if (rdev->clock.current_dispclk <=
5167 
		    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5168 
			if (ulv->pl.vddc <
5169 
			    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5170 
				return false;
5171 
		}
5172 
	}
5173 
 
5174 
	if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5175 
		return false;
5176 
 
5177 
	return true;
5178 
}
5179 
 
5180 
static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5181 
						       struct radeon_ps *radeon_new_state)
5182 
{
5183 
	const struct si_power_info *si_pi = si_get_pi(rdev);
5184 
	const struct si_ulv_param *ulv = &si_pi->ulv;
5185 
 
5186 
	if (ulv->supported) {
5187 
		if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5188 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5189 
 
5190 
	}
5191 
	return 0;
5192 
}
5193 
 
5194 
static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5195 
					 struct radeon_ps *radeon_state,
5196 
					 SISLANDS_SMC_SWSTATE *smc_state)
5197 
{
5198 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5199 
	struct ni_power_info *ni_pi = ni_get_pi(rdev);
5200 
	struct si_power_info *si_pi = si_get_pi(rdev);
5201 
	struct ni_ps *state = ni_get_ps(radeon_state);
5202 
	int i, ret;
5203 
	u32 threshold;
5204 
	u32 sclk_in_sr = 1350; /* ??? */
5205 
 
5206 
	if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5207 
		return -EINVAL;
5208 
 
5209 
	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5210 
 
5211 
	if (radeon_state->vclk && radeon_state->dclk) {
5212 
		eg_pi->uvd_enabled = true;
5213 
		if (eg_pi->smu_uvd_hs)
5214 
			smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5215 
	} else {
5216 
		eg_pi->uvd_enabled = false;
5217 
	}
5218 
 
5219 
	if (state->dc_compatible)
5220 
		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5221 
 
5222 
	smc_state->levelCount = 0;
5223 
	for (i = 0; i < state->performance_level_count; i++) {
5224 
		if (eg_pi->sclk_deep_sleep) {
5225 
			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5226 
				if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5227 
					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5228 
				else
5229 
					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5230 
			}
5231 
		}
5232 
 
5233 
		ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5234 
						    &smc_state->levels[i]);
5235 
		smc_state->levels[i].arbRefreshState =
5236 
			(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5237 
 
5238 
		if (ret)
5239 
			return ret;
5240 
 
5241 
		if (ni_pi->enable_power_containment)
5242 
			smc_state->levels[i].displayWatermark =
5243 
				(state->performance_levels[i].sclk < threshold) ?
5244 
				PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5245 
		else
5246 
			smc_state->levels[i].displayWatermark = (i < 2) ?
5247 
				PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5248 
 
5249 
		if (eg_pi->dynamic_ac_timing)
5250 
			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5251 
		else
5252 
			smc_state->levels[i].ACIndex = 0;
5253 
 
5254 
		smc_state->levelCount++;
5255 
	}
5256 
 
5257 
	si_write_smc_soft_register(rdev,
5258 
				   SI_SMC_SOFT_REGISTER_watermark_threshold,
5259 
				   threshold / 512);
5260 
 
5261 
	si_populate_smc_sp(rdev, radeon_state, smc_state);
5262 
 
5263 
	ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5264 
	if (ret)
5265 
		ni_pi->enable_power_containment = false;
5266 
 
5267 
	ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5268 
        if (ret)
5269 
		ni_pi->enable_sq_ramping = false;
5270 
 
5271 
	return si_populate_smc_t(rdev, radeon_state, smc_state);
5272 
}
5273 
 
5274 
static int si_upload_sw_state(struct radeon_device *rdev,
5275 
			      struct radeon_ps *radeon_new_state)
5276 
{
5277 
	struct si_power_info *si_pi = si_get_pi(rdev);
5278 
	struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5279 
	int ret;
5280 
	u32 address = si_pi->state_table_start +
5281 
		offsetof(SISLANDS_SMC_STATETABLE, driverState);
5282 
	u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5283 
		((new_state->performance_level_count - 1) *
5284 
		 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5285 
	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5286 
 
5287 
	memset(smc_state, 0, state_size);
5288 
 
5289 
	ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5290 
	if (ret)
5291 
		return ret;
5292 
 
5293 
	ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5294 
				   state_size, si_pi->sram_end);
5295 
 
5296 
	return ret;
5297 
}
5298 
 
5299 
static int si_upload_ulv_state(struct radeon_device *rdev)
5300 
{
5301 
	struct si_power_info *si_pi = si_get_pi(rdev);
5302 
	struct si_ulv_param *ulv = &si_pi->ulv;
5303 
	int ret = 0;
5304 
 
5305 
	if (ulv->supported && ulv->pl.vddc) {
5306 
		u32 address = si_pi->state_table_start +
5307 
			offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5308 
		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5309 
		u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5310 
 
5311 
		memset(smc_state, 0, state_size);
5312 
 
5313 
		ret = si_populate_ulv_state(rdev, smc_state);
5314 
		if (!ret)
5315 
			ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5316 
						   state_size, si_pi->sram_end);
5317 
	}
5318 
 
5319 
	return ret;
5320 
}
5321 
 
5322 
static int si_upload_smc_data(struct radeon_device *rdev)
5323 
{
5324 
	struct radeon_crtc *radeon_crtc = NULL;
5325 
	int i;
5326 
 
5327 
	if (rdev->pm.dpm.new_active_crtc_count == 0)
5328 
		return 0;
5329 
 
5330 
	for (i = 0; i < rdev->num_crtc; i++) {
5331 
		if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5332 
			radeon_crtc = rdev->mode_info.crtcs[i];
5333 
			break;
5334 
		}
5335 
	}
5336 
 
5337 
	if (radeon_crtc == NULL)
5338 
		return 0;
5339 
 
5340 
	if (radeon_crtc->line_time <= 0)
5341 
		return 0;
5342 
 
5343 
	if (si_write_smc_soft_register(rdev,
5344 
				       SI_SMC_SOFT_REGISTER_crtc_index,
5345 
				       radeon_crtc->crtc_id) != PPSMC_Result_OK)
5346 
		return 0;
5347 
 
5348 
	if (si_write_smc_soft_register(rdev,
5349 
				       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5350 
				       radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5351 
		return 0;
5352 
 
5353 
	if (si_write_smc_soft_register(rdev,
5354 
				       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5355 
				       radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5356 
		return 0;
5357 
 
5358 
	return 0;
5359 
}
5360 
 
5361 
static int si_set_mc_special_registers(struct radeon_device *rdev,
5362 
				       struct si_mc_reg_table *table)
5363 
{
5364 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5365 
	u8 i, j, k;
5366 
	u32 temp_reg;
5367 
 
5368 
	for (i = 0, j = table->last; i < table->last; i++) {
5369 
		if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5370 
			return -EINVAL;
5371 
		switch (table->mc_reg_address[i].s1 << 2) {
5372 
		case MC_SEQ_MISC1:
5373 
			temp_reg = RREG32(MC_PMG_CMD_EMRS);
5374 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5375 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5376 
			for (k = 0; k < table->num_entries; k++)
5377 
				table->mc_reg_table_entry[k].mc_data[j] =
5378 
					((temp_reg & 0xffff0000)) |
5379 
					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5380 
			j++;
5381 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5382 
				return -EINVAL;
5383 
 
5384 
			temp_reg = RREG32(MC_PMG_CMD_MRS);
5385 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5386 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5387 
			for (k = 0; k < table->num_entries; k++) {
5388 
				table->mc_reg_table_entry[k].mc_data[j] =
5389 
					(temp_reg & 0xffff0000) |
5390 
					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5391 
				if (!pi->mem_gddr5)
5392 
					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5393 
			}
5394 
			j++;
5395 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5396 
				return -EINVAL;
5397 
 
5398 
			if (!pi->mem_gddr5) {
5399 
				table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5400 
				table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5401 
				for (k = 0; k < table->num_entries; k++)
5402 
					table->mc_reg_table_entry[k].mc_data[j] =
5403 
						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5404 
				j++;
5405 
				if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5406 
					return -EINVAL;
5407 
			}
5408 
			break;
5409 
		case MC_SEQ_RESERVE_M:
5410 
			temp_reg = RREG32(MC_PMG_CMD_MRS1);
5411 
			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5412 
			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5413 
			for(k = 0; k < table->num_entries; k++)
5414 
				table->mc_reg_table_entry[k].mc_data[j] =
5415 
					(temp_reg & 0xffff0000) |
5416 
					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5417 
			j++;
5418 
			if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5419 
				return -EINVAL;
5420 
			break;
5421 
		default:
5422 
			break;
5423 
		}
5424 
	}
5425 
 
5426 
	table->last = j;
5427 
 
5428 
	return 0;
5429 
}
5430 
 
5431 
static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5432 
{
5433 
	bool result = true;
5434 
 
5435 
	switch (in_reg) {
5436 
	case  MC_SEQ_RAS_TIMING >> 2:
5437 
		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5438 
		break;
5439 
        case MC_SEQ_CAS_TIMING >> 2:
5440 
		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5441 
		break;
5442 
        case MC_SEQ_MISC_TIMING >> 2:
5443 
		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5444 
		break;
5445 
        case MC_SEQ_MISC_TIMING2 >> 2:
5446 
		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5447 
		break;
5448 
        case MC_SEQ_RD_CTL_D0 >> 2:
5449 
		*out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5450 
		break;
5451 
        case MC_SEQ_RD_CTL_D1 >> 2:
5452 
		*out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5453 
		break;
5454 
        case MC_SEQ_WR_CTL_D0 >> 2:
5455 
		*out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5456 
		break;
5457 
        case MC_SEQ_WR_CTL_D1 >> 2:
5458 
		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5459 
		break;
5460 
        case MC_PMG_CMD_EMRS >> 2:
5461 
		*out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5462 
		break;
5463 
        case MC_PMG_CMD_MRS >> 2:
5464 
		*out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5465 
		break;
5466 
        case MC_PMG_CMD_MRS1 >> 2:
5467 
		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5468 
		break;
5469 
        case MC_SEQ_PMG_TIMING >> 2:
5470 
		*out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5471 
		break;
5472 
        case MC_PMG_CMD_MRS2 >> 2:
5473 
		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5474 
		break;
5475 
        case MC_SEQ_WR_CTL_2 >> 2:
5476 
		*out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5477 
		break;
5478 
        default:
5479 
		result = false;
5480 
		break;
5481 
	}
5482 
 
5483 
	return result;
5484 
}
5485 
 
5486 
static void si_set_valid_flag(struct si_mc_reg_table *table)
5487 
{
5488 
	u8 i, j;
5489 
 
5490 
	for (i = 0; i < table->last; i++) {
5491 
		for (j = 1; j < table->num_entries; j++) {
5492 
			if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5493 
				table->valid_flag |= 1 << i;
5494 
				break;
5495 
			}
5496 
		}
5497 
	}
5498 
}
5499 
 
5500 
static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5501 
{
5502 
	u32 i;
5503 
	u16 address;
5504 
 
5505 
	for (i = 0; i < table->last; i++)
5506 
		table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5507 
			address : table->mc_reg_address[i].s1;
5508 
 
5509 
}
5510 
 
5511 
static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5512 
				      struct si_mc_reg_table *si_table)
5513 
{
5514 
	u8 i, j;
5515 
 
5516 
	if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5517 
		return -EINVAL;
5518 
	if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5519 
		return -EINVAL;
5520 
 
5521 
	for (i = 0; i < table->last; i++)
5522 
		si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5523 
	si_table->last = table->last;
5524 
 
5525 
	for (i = 0; i < table->num_entries; i++) {
5526 
		si_table->mc_reg_table_entry[i].mclk_max =
5527 
			table->mc_reg_table_entry[i].mclk_max;
5528 
		for (j = 0; j < table->last; j++) {
5529 
			si_table->mc_reg_table_entry[i].mc_data[j] =
5530 
				table->mc_reg_table_entry[i].mc_data[j];
5531 
		}
5532 
	}
5533 
	si_table->num_entries = table->num_entries;
5534 
 
5535 
	return 0;
5536 
}
5537 
 
5538 
static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5539 
{
5540 
	struct si_power_info *si_pi = si_get_pi(rdev);
5541 
	struct atom_mc_reg_table *table;
5542 
	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5543 
	u8 module_index = rv770_get_memory_module_index(rdev);
5544 
	int ret;
5545 
 
5546 
	table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5547 
	if (!table)
5548 
		return -ENOMEM;
5549 
 
5550 
	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5551 
	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5552 
	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5553 
	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5554 
	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5555 
	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5556 
	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5557 
	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5558 
	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5559 
	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5560 
	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5561 
	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5562 
	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5563 
	WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5564 
 
5565 
        ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5566 
        if (ret)
5567 
                goto init_mc_done;
5568 
 
5569 
        ret = si_copy_vbios_mc_reg_table(table, si_table);
5570 
        if (ret)
5571 
                goto init_mc_done;
5572 
 
5573 
	si_set_s0_mc_reg_index(si_table);
5574 
 
5575 
	ret = si_set_mc_special_registers(rdev, si_table);
5576 
        if (ret)
5577 
                goto init_mc_done;
5578 
 
5579 
	si_set_valid_flag(si_table);
5580 
 
5581 
init_mc_done:
5582 
	kfree(table);
5583 
 
5584 
	return ret;
5585 
 
5586 
}
5587 
 
5588 
static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5589 
					 SMC_SIslands_MCRegisters *mc_reg_table)
5590 
{
5591 
	struct si_power_info *si_pi = si_get_pi(rdev);
5592 
	u32 i, j;
5593 
 
5594 
	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5595 
		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5596 
			if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5597 
				break;
5598 
			mc_reg_table->address[i].s0 =
5599 
				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5600 
			mc_reg_table->address[i].s1 =
5601 
				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5602 
			i++;
5603 
		}
5604 
	}
5605 
	mc_reg_table->last = (u8)i;
5606 
}
5607 
 
5608 
static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5609 
				    SMC_SIslands_MCRegisterSet *data,
5610 
				    u32 num_entries, u32 valid_flag)
5611 
{
5612 
	u32 i, j;
5613 
 
5614 
	for(i = 0, j = 0; j < num_entries; j++) {
5615 
		if (valid_flag & (1 << j)) {
5616 
			data->value[i] = cpu_to_be32(entry->mc_data[j]);
5617 
			i++;
5618 
		}
5619 
	}
5620 
}
5621 
 
5622 
static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5623 
						 struct rv7xx_pl *pl,
5624 
						 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5625 
{
5626 
	struct si_power_info *si_pi = si_get_pi(rdev);
5627 
	u32 i = 0;
5628 
 
5629 
	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5630 
		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5631 
			break;
5632 
	}
5633 
 
5634 
	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5635 
		--i;
5636 
 
5637 
	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5638 
				mc_reg_table_data, si_pi->mc_reg_table.last,
5639 
				si_pi->mc_reg_table.valid_flag);
5640 
}
5641 
 
5642 
static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5643 
					   struct radeon_ps *radeon_state,
5644 
					   SMC_SIslands_MCRegisters *mc_reg_table)
5645 
{
5646 
	struct ni_ps *state = ni_get_ps(radeon_state);
5647 
	int i;
5648 
 
5649 
	for (i = 0; i < state->performance_level_count; i++) {
5650 
		si_convert_mc_reg_table_entry_to_smc(rdev,
5651 
						     &state->performance_levels[i],
5652 
						     &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5653 
	}
5654 
}
5655 
 
5656 
static int si_populate_mc_reg_table(struct radeon_device *rdev,
5657 
				    struct radeon_ps *radeon_boot_state)
5658 
{
5659 
	struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5660 
	struct si_power_info *si_pi = si_get_pi(rdev);
5661 
	struct si_ulv_param *ulv = &si_pi->ulv;
5662 
	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5663 
 
5664 
	memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5665 
 
5666 
	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5667 
 
5668 
	si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5669 
 
5670 
	si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5671 
					     &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5672 
 
5673 
	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5674 
				&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5675 
				si_pi->mc_reg_table.last,
5676 
				si_pi->mc_reg_table.valid_flag);
5677 
 
5678 
	if (ulv->supported && ulv->pl.vddc != 0)
5679 
		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5680 
						     &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5681 
	else
5682 
		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5683 
					&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5684 
					si_pi->mc_reg_table.last,
5685 
					si_pi->mc_reg_table.valid_flag);
5686 
 
5687 
	si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5688 
 
5689 
	return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5690 
				    (u8 *)smc_mc_reg_table,
5691 
				    sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5692 
}
5693 
 
5694 
static int si_upload_mc_reg_table(struct radeon_device *rdev,
5695 
				  struct radeon_ps *radeon_new_state)
5696 
{
5697 
	struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5698 
	struct si_power_info *si_pi = si_get_pi(rdev);
5699 
	u32 address = si_pi->mc_reg_table_start +
5700 
		offsetof(SMC_SIslands_MCRegisters,
5701 
			 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5702 
	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5703 
 
5704 
	memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5705 
 
5706 
	si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5707 
 
5708 
 
5709 
	return si_copy_bytes_to_smc(rdev, address,
5710 
				    (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5711 
				    sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5712 
				    si_pi->sram_end);
5713 
 
5714 
}
5715 
 
5716 
static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5717 
{
5718 
        if (enable)
5719 
                WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5720 
        else
5721 
                WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5722 
}
5723 
 
5724 
static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5725 
						      struct radeon_ps *radeon_state)
5726 
{
5727 
	struct ni_ps *state = ni_get_ps(radeon_state);
5728 
	int i;
5729 
	u16 pcie_speed, max_speed = 0;
5730 
 
5731 
	for (i = 0; i < state->performance_level_count; i++) {
5732 
		pcie_speed = state->performance_levels[i].pcie_gen;
5733 
		if (max_speed < pcie_speed)
5734 
			max_speed = pcie_speed;
5735 
	}
5736 
	return max_speed;
5737 
}
5738 
 
5739 
static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5740 
{
5741 
	u32 speed_cntl;
5742 
 
5743 
	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5744 
	speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5745 
 
5746 
	return (u16)speed_cntl;
5747 
}
5748 
 
5749 
static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5750 
							     struct radeon_ps *radeon_new_state,
5751 
							     struct radeon_ps *radeon_current_state)
5752 
{
5753 
	struct si_power_info *si_pi = si_get_pi(rdev);
5754 
	enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5755 
	enum radeon_pcie_gen current_link_speed;
5756 
 
5757 
	if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5758 
		current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5759 
	else
5760 
		current_link_speed = si_pi->force_pcie_gen;
5761 
 
5762 
	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5763 
	si_pi->pspp_notify_required = false;
5764 
	if (target_link_speed > current_link_speed) {
5765 
		switch (target_link_speed) {
5766 
#if defined(CONFIG_ACPI)
5767 
		case RADEON_PCIE_GEN3:
5768 
			if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5769 
				break;
5770 
			si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5771 
			if (current_link_speed == RADEON_PCIE_GEN2)
5772 
				break;
5773 
		case RADEON_PCIE_GEN2:
5774 
			if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5775 
				break;
5776 
#endif
5777 
		default:
5778 
			si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5779 
			break;
5780 
		}
5781 
	} else {
5782 
		if (target_link_speed < current_link_speed)
5783 
			si_pi->pspp_notify_required = true;
5784 
	}
5785 
}
5786 
 
5787 
static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5788 
							   struct radeon_ps *radeon_new_state,
5789 
							   struct radeon_ps *radeon_current_state)
5790 
{
5791 
	struct si_power_info *si_pi = si_get_pi(rdev);
5792 
	enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5793 
	u8 request;
5794 
 
5795 
	if (si_pi->pspp_notify_required) {
5796 
		if (target_link_speed == RADEON_PCIE_GEN3)
5797 
			request = PCIE_PERF_REQ_PECI_GEN3;
5798 
		else if (target_link_speed == RADEON_PCIE_GEN2)
5799 
			request = PCIE_PERF_REQ_PECI_GEN2;
5800 
		else
5801 
			request = PCIE_PERF_REQ_PECI_GEN1;
5802 
 
5803 
		if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5804 
		    (si_get_current_pcie_speed(rdev) > 0))
5805 
			return;
5806 
 
5807 
#if defined(CONFIG_ACPI)
5808 
		radeon_acpi_pcie_performance_request(rdev, request, false);
5809 
#endif
5810 
	}
5811 
}
5812 
 
5813 
#if 0
5814 
static int si_ds_request(struct radeon_device *rdev,
5815 
			 bool ds_status_on, u32 count_write)
5816 
{
5817 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5818 
 
5819 
	if (eg_pi->sclk_deep_sleep) {
5820 
		if (ds_status_on)
5821 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5822 
				PPSMC_Result_OK) ?
5823 
 
5824 
		else
5825 
			return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5826 
				PPSMC_Result_OK) ? 0 : -EINVAL;
5827 
	}
5828 
	return 0;
5829 
}
5830 
#endif
5831 
 
5832 
static void si_set_max_cu_value(struct radeon_device *rdev)
5833 
{
5834 
	struct si_power_info *si_pi = si_get_pi(rdev);
5835 
 
5836 
	if (rdev->family == CHIP_VERDE) {
5837 
		switch (rdev->pdev->device) {
5838 
		case 0x6820:
5839 
		case 0x6825:
5840 
		case 0x6821:
5841 
		case 0x6823:
5842 
		case 0x6827:
5843 
			si_pi->max_cu = 10;
5844 
			break;
5845 
		case 0x682D:
5846 
		case 0x6824:
5847 
		case 0x682F:
5848 
		case 0x6826:
5849 
			si_pi->max_cu = 8;
5850 
			break;
5851 
		case 0x6828:
5852 
		case 0x6830:
5853 
		case 0x6831:
5854 
		case 0x6838:
5855 
		case 0x6839:
5856 
		case 0x683D:
5857 
			si_pi->max_cu = 10;
5858 
			break;
5859 
		case 0x683B:
5860 
		case 0x683F:
5861 
		case 0x6829:
5862 
			si_pi->max_cu = 8;
5863 
			break;
5864 
		default:
5865 
			si_pi->max_cu = 0;
5866 
			break;
5867 
		}
5868 
	} else {
5869 
		si_pi->max_cu = 0;
5870 
	}
5871 
}
5872 
 
5873 
static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5874 
							     struct radeon_clock_voltage_dependency_table *table)
5875 
{
5876 
	u32 i;
5877 
	int j;
5878 
	u16 leakage_voltage;
5879 
 
5880 
	if (table) {
5881 
		for (i = 0; i < table->count; i++) {
5882 
			switch (si_get_leakage_voltage_from_leakage_index(rdev,
5883 
									  table->entries[i].v,
5884 
									  &leakage_voltage)) {
5885 
			case 0:
5886 
				table->entries[i].v = leakage_voltage;
5887 
				break;
5888 
			case -EAGAIN:
5889 
				return -EINVAL;
5890 
			case -EINVAL:
5891 
			default:
5892 
				break;
5893 
			}
5894 
		}
5895 
 
5896 
		for (j = (table->count - 2); j >= 0; j--) {
5897 
			table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5898 
				table->entries[j].v : table->entries[j + 1].v;
5899 
		}
5900 
	}
5901 
	return 0;
5902 
}
5903 
 
5904 
static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5905 
{
5906 
	int ret = 0;
5907 
 
5908 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5909 
								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5910 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5911 
								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5912 
	ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5913 
								&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5914 
	return ret;
5915 
}
5916 
 
5917 
static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5918 
					  struct radeon_ps *radeon_new_state,
5919 
					  struct radeon_ps *radeon_current_state)
5920 
{
5921 
	u32 lane_width;
5922 
	u32 new_lane_width =
5923 
		(radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5924 
	u32 current_lane_width =
5925 
		(radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5926 
 
5927 
	if (new_lane_width != current_lane_width) {
5928 
		radeon_set_pcie_lanes(rdev, new_lane_width);
5929 
		lane_width = radeon_get_pcie_lanes(rdev);
5930 
		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5931 
	}
5932 
}
5933 
 
6104 serge 5934 
static void si_set_vce_clock(struct radeon_device *rdev,
5935 
			     struct radeon_ps *new_rps,
5936 
			     struct radeon_ps *old_rps)
5937 
{
5938 
	if ((old_rps->evclk != new_rps->evclk) ||
5939 
	    (old_rps->ecclk != new_rps->ecclk)) {
5940 
		/* turn the clocks on when encoding, off otherwise */
5941 
		if (new_rps->evclk || new_rps->ecclk)
5942 
			vce_v1_0_enable_mgcg(rdev, false);
5943 
		else
5944 
			vce_v1_0_enable_mgcg(rdev, true);
5945 
		radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5946 
	}
5947 
}
5948 
 
5078 serge 5949 
void si_dpm_setup_asic(struct radeon_device *rdev)
5950 
{
5951 
	int r;
5952 
 
5953 
	r = si_mc_load_microcode(rdev);
5954 
	if (r)
5955 
		DRM_ERROR("Failed to load MC firmware!\n");
5956 
	rv770_get_memory_type(rdev);
5957 
	si_read_clock_registers(rdev);
5958 
	si_enable_acpi_power_management(rdev);
5959 
}
5960 
 
5271 serge 5961 
static int si_thermal_enable_alert(struct radeon_device *rdev,
5962 
				   bool enable)
5963 
{
5964 
	u32 thermal_int = RREG32(CG_THERMAL_INT);
5965 
 
5966 
	if (enable) {
5967 
		PPSMC_Result result;
5968 
 
5969 
		thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5970 
		WREG32(CG_THERMAL_INT, thermal_int);
5971 
		rdev->irq.dpm_thermal = false;
5972 
		result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5973 
		if (result != PPSMC_Result_OK) {
5974 
			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5975 
			return -EINVAL;
5976 
		}
5977 
	} else {
5978 
		thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5979 
		WREG32(CG_THERMAL_INT, thermal_int);
5980 
		rdev->irq.dpm_thermal = true;
5981 
	}
5982 
 
5983 
	return 0;
5984 
}
5985 
 
5986 
static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6104 serge 5987 
					    int min_temp, int max_temp)
5078 serge 5988 
{
5989 
	int low_temp = 0 * 1000;
5990 
	int high_temp = 255 * 1000;
5991 
 
5992 
	if (low_temp < min_temp)
5993 
		low_temp = min_temp;
5994 
	if (high_temp > max_temp)
5995 
		high_temp = max_temp;
5996 
	if (high_temp < low_temp) {
5997 
		DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5998 
		return -EINVAL;
5999 
	}
6000 
 
6001 
	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6002 
	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6003 
	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6004 
 
6005 
	rdev->pm.dpm.thermal.min_temp = low_temp;
6006 
	rdev->pm.dpm.thermal.max_temp = high_temp;
6007 
 
6008 
	return 0;
6009 
}
6010 
 
5271 serge 6011 
static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6012 
{
6013 
	struct si_power_info *si_pi = si_get_pi(rdev);
6014 
	u32 tmp;
6015 
 
6016 
	if (si_pi->fan_ctrl_is_in_default_mode) {
6017 
		tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6018 
		si_pi->fan_ctrl_default_mode = tmp;
6019 
		tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6020 
		si_pi->t_min = tmp;
6021 
		si_pi->fan_ctrl_is_in_default_mode = false;
6022 
	}
6023 
 
6024 
	tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6025 
	tmp |= TMIN(0);
6026 
	WREG32(CG_FDO_CTRL2, tmp);
6027 
 
6028 
	tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6029 
	tmp |= FDO_PWM_MODE(mode);
6030 
	WREG32(CG_FDO_CTRL2, tmp);
6031 
}
6032 
 
6033 
static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6034 
{
6035 
	struct si_power_info *si_pi = si_get_pi(rdev);
6036 
	PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6037 
	u32 duty100;
6038 
	u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6039 
	u16 fdo_min, slope1, slope2;
6040 
	u32 reference_clock, tmp;
6041 
	int ret;
6042 
	u64 tmp64;
6043 
 
6044 
	if (!si_pi->fan_table_start) {
6045 
		rdev->pm.dpm.fan.ucode_fan_control = false;
6046 
		return 0;
6047 
	}
6048 
 
6049 
	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6050 
 
6051 
	if (duty100 == 0) {
6052 
		rdev->pm.dpm.fan.ucode_fan_control = false;
6053 
		return 0;
6054 
	}
6055 
 
6056 
	tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6057 
	do_div(tmp64, 10000);
6058 
	fdo_min = (u16)tmp64;
6059 
 
6060 
	t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6061 
	t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6062 
 
6063 
	pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6064 
	pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6065 
 
6066 
	slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6067 
	slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6068 
 
6104 serge 6069 
	fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6070 
	fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6071 
	fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6072 
 
5271 serge 6073 
	fan_table.slope1 = cpu_to_be16(slope1);
6074 
	fan_table.slope2 = cpu_to_be16(slope2);
6075 
 
6076 
	fan_table.fdo_min = cpu_to_be16(fdo_min);
6077 
 
6078 
	fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6079 
 
6080 
	fan_table.hys_up = cpu_to_be16(1);
6081 
 
6082 
	fan_table.hys_slope = cpu_to_be16(1);
6083 
 
6084 
	fan_table.temp_resp_lim = cpu_to_be16(5);
6085 
 
6086 
	reference_clock = radeon_get_xclk(rdev);
6087 
 
6088 
	fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6089 
						reference_clock) / 1600);
6090 
 
6091 
	fan_table.fdo_max = cpu_to_be16((u16)duty100);
6092 
 
6093 
	tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6094 
	fan_table.temp_src = (uint8_t)tmp;
6095 
 
6096 
	ret = si_copy_bytes_to_smc(rdev,
6097 
				   si_pi->fan_table_start,
6098 
				   (u8 *)(&fan_table),
6099 
				   sizeof(fan_table),
6100 
				   si_pi->sram_end);
6101 
 
6102 
	if (ret) {
6103 
		DRM_ERROR("Failed to load fan table to the SMC.");
6104 
		rdev->pm.dpm.fan.ucode_fan_control = false;
6105 
	}
6106 
 
6107 
	return 0;
6108 
}
6109 
 
6110 
static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6111 
{
6104 serge 6112 
	struct si_power_info *si_pi = si_get_pi(rdev);
5271 serge 6113 
	PPSMC_Result ret;
6114 
 
6115 
	ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6104 serge 6116 
	if (ret == PPSMC_Result_OK) {
6117 
		si_pi->fan_is_controlled_by_smc = true;
5271 serge 6118 
		return 0;
6104 serge 6119 
	} else {
5271 serge 6120 
		return -EINVAL;
6104 serge 6121 
	}
5271 serge 6122 
}
6123 
 
6124 
static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6125 
{
6104 serge 6126 
	struct si_power_info *si_pi = si_get_pi(rdev);
5271 serge 6127 
	PPSMC_Result ret;
6128 
 
6129 
	ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6104 serge 6130 
 
6131 
	if (ret == PPSMC_Result_OK) {
6132 
		si_pi->fan_is_controlled_by_smc = false;
5271 serge 6133 
		return 0;
6104 serge 6134 
	} else {
5271 serge 6135 
		return -EINVAL;
6104 serge 6136 
	}
5271 serge 6137 
}
6138 
 
6104 serge 6139 
int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6140 
				      u32 *speed)
5271 serge 6141 
{
6142 
	u32 duty, duty100;
6143 
	u64 tmp64;
6144 
 
6145 
	if (rdev->pm.no_fan)
6146 
		return -ENOENT;
6147 
 
6148 
	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6149 
	duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6150 
 
6151 
	if (duty100 == 0)
6152 
		return -EINVAL;
6153 
 
6154 
	tmp64 = (u64)duty * 100;
6155 
	do_div(tmp64, duty100);
6156 
	*speed = (u32)tmp64;
6157 
 
6158 
	if (*speed > 100)
6159 
		*speed = 100;
6160 
 
6161 
	return 0;
6162 
}
6163 
 
6104 serge 6164 
int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6165 
				      u32 speed)
5271 serge 6166 
{
6104 serge 6167 
	struct si_power_info *si_pi = si_get_pi(rdev);
5271 serge 6168 
	u32 tmp;
6169 
	u32 duty, duty100;
6170 
	u64 tmp64;
6171 
 
6172 
	if (rdev->pm.no_fan)
6173 
		return -ENOENT;
6174 
 
6104 serge 6175 
	if (si_pi->fan_is_controlled_by_smc)
6176 
		return -EINVAL;
6177 
 
5271 serge 6178 
	if (speed > 100)
6179 
		return -EINVAL;
6180 
 
6181 
	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6182 
 
6183 
	if (duty100 == 0)
6184 
		return -EINVAL;
6185 
 
6186 
	tmp64 = (u64)speed * duty100;
6187 
	do_div(tmp64, 100);
6188 
	duty = (u32)tmp64;
6189 
 
6190 
	tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6191 
	tmp |= FDO_STATIC_DUTY(duty);
6192 
	WREG32(CG_FDO_CTRL0, tmp);
6193 
 
6194 
	return 0;
6195 
}
6196 
 
6104 serge 6197 
void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6198 
{
6199 
	if (mode) {
6200 
		/* stop auto-manage */
6201 
		if (rdev->pm.dpm.fan.ucode_fan_control)
6202 
			si_fan_ctrl_stop_smc_fan_control(rdev);
6203 
		si_fan_ctrl_set_static_mode(rdev, mode);
6204 
	} else {
6205 
		/* restart auto-manage */
6206 
		if (rdev->pm.dpm.fan.ucode_fan_control)
6207 
			si_thermal_start_smc_fan_control(rdev);
6208 
		else
6209 
			si_fan_ctrl_set_default_mode(rdev);
6210 
	}
6211 
}
6212 
 
6213 
u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6214 
{
6215 
	struct si_power_info *si_pi = si_get_pi(rdev);
6216 
	u32 tmp;
6217 
 
6218 
	if (si_pi->fan_is_controlled_by_smc)
6219 
		return 0;
6220 
 
6221 
	tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6222 
	return (tmp >> FDO_PWM_MODE_SHIFT);
6223 
}
6224 
 
6225 
#if 0
5271 serge 6226 
static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6227 
					 u32 *speed)
6228 
{
6229 
	u32 tach_period;
6230 
	u32 xclk = radeon_get_xclk(rdev);
6231 
 
6232 
	if (rdev->pm.no_fan)
6233 
		return -ENOENT;
6234 
 
6235 
	if (rdev->pm.fan_pulses_per_revolution == 0)
6236 
		return -ENOENT;
6237 
 
6238 
	tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6239 
	if (tach_period == 0)
6240 
		return -ENOENT;
6241 
 
6242 
	*speed = 60 * xclk * 10000 / tach_period;
6243 
 
6244 
	return 0;
6245 
}
6246 
 
6247 
static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6248 
					 u32 speed)
6249 
{
6250 
	u32 tach_period, tmp;
6251 
	u32 xclk = radeon_get_xclk(rdev);
6252 
 
6253 
	if (rdev->pm.no_fan)
6254 
		return -ENOENT;
6255 
 
6256 
	if (rdev->pm.fan_pulses_per_revolution == 0)
6257 
		return -ENOENT;
6258 
 
6259 
	if ((speed < rdev->pm.fan_min_rpm) ||
6260 
	    (speed > rdev->pm.fan_max_rpm))
6261 
		return -EINVAL;
6262 
 
6263 
	if (rdev->pm.dpm.fan.ucode_fan_control)
6264 
		si_fan_ctrl_stop_smc_fan_control(rdev);
6265 
 
6266 
	tach_period = 60 * xclk * 10000 / (8 * speed);
6267 
	tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6268 
	tmp |= TARGET_PERIOD(tach_period);
6269 
	WREG32(CG_TACH_CTRL, tmp);
6270 
 
6271 
	si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6272 
 
6273 
	return 0;
6274 
}
6275 
#endif
6276 
 
6277 
static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6278 
{
6279 
	struct si_power_info *si_pi = si_get_pi(rdev);
6280 
	u32 tmp;
6281 
 
6282 
	if (!si_pi->fan_ctrl_is_in_default_mode) {
6283 
		tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6284 
		tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6285 
		WREG32(CG_FDO_CTRL2, tmp);
6286 
 
6287 
		tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6288 
		tmp |= TMIN(si_pi->t_min);
6289 
		WREG32(CG_FDO_CTRL2, tmp);
6290 
		si_pi->fan_ctrl_is_in_default_mode = true;
6291 
	}
6292 
}
6293 
 
6294 
static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6295 
{
6296 
	if (rdev->pm.dpm.fan.ucode_fan_control) {
6297 
		si_fan_ctrl_start_smc_fan_control(rdev);
6298 
		si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6299 
	}
6300 
}
6301 
 
6302 
static void si_thermal_initialize(struct radeon_device *rdev)
6303 
{
6304 
	u32 tmp;
6305 
 
6306 
	if (rdev->pm.fan_pulses_per_revolution) {
6307 
		tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6308 
		tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6309 
		WREG32(CG_TACH_CTRL, tmp);
6310 
	}
6311 
 
6312 
	tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6313 
	tmp |= TACH_PWM_RESP_RATE(0x28);
6314 
	WREG32(CG_FDO_CTRL2, tmp);
6315 
}
6316 
 
6317 
static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6318 
{
6319 
	int ret;
6320 
 
6321 
	si_thermal_initialize(rdev);
6322 
	ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6323 
	if (ret)
6324 
		return ret;
6325 
	ret = si_thermal_enable_alert(rdev, true);
6326 
	if (ret)
6327 
		return ret;
6328 
	if (rdev->pm.dpm.fan.ucode_fan_control) {
6329 
		ret = si_halt_smc(rdev);
6330 
		if (ret)
6331 
			return ret;
6332 
		ret = si_thermal_setup_fan_table(rdev);
6333 
		if (ret)
6334 
			return ret;
6335 
		ret = si_resume_smc(rdev);
6336 
		if (ret)
6337 
			return ret;
6338 
		si_thermal_start_smc_fan_control(rdev);
6339 
	}
6340 
 
6341 
	return 0;
6342 
}
6343 
 
6344 
static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6345 
{
6346 
	if (!rdev->pm.no_fan) {
6347 
		si_fan_ctrl_set_default_mode(rdev);
6348 
		si_fan_ctrl_stop_smc_fan_control(rdev);
6349 
	}
6350 
}
6351 
 
5078 serge 6352 
int si_dpm_enable(struct radeon_device *rdev)
6353 
{
6354 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6355 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6356 
	struct si_power_info *si_pi = si_get_pi(rdev);
6357 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6358 
	int ret;
6359 
 
6360 
	if (si_is_smc_running(rdev))
6361 
		return -EINVAL;
6362 
	if (pi->voltage_control || si_pi->voltage_control_svi2)
6363 
		si_enable_voltage_control(rdev, true);
6364 
	if (pi->mvdd_control)
6365 
		si_get_mvdd_configuration(rdev);
6366 
	if (pi->voltage_control || si_pi->voltage_control_svi2) {
6367 
		ret = si_construct_voltage_tables(rdev);
6368 
		if (ret) {
6369 
			DRM_ERROR("si_construct_voltage_tables failed\n");
6370 
			return ret;
6371 
		}
6372 
	}
6373 
	if (eg_pi->dynamic_ac_timing) {
6374 
		ret = si_initialize_mc_reg_table(rdev);
6375 
		if (ret)
6376 
			eg_pi->dynamic_ac_timing = false;
6377 
	}
6378 
	if (pi->dynamic_ss)
6379 
		si_enable_spread_spectrum(rdev, true);
6380 
	if (pi->thermal_protection)
6381 
		si_enable_thermal_protection(rdev, true);
6382 
	si_setup_bsp(rdev);
6383 
	si_program_git(rdev);
6384 
	si_program_tp(rdev);
6385 
	si_program_tpp(rdev);
6386 
	si_program_sstp(rdev);
6387 
	si_enable_display_gap(rdev);
6388 
	si_program_vc(rdev);
6389 
	ret = si_upload_firmware(rdev);
6390 
	if (ret) {
6391 
		DRM_ERROR("si_upload_firmware failed\n");
6392 
		return ret;
6393 
	}
6394 
	ret = si_process_firmware_header(rdev);
6395 
	if (ret) {
6396 
		DRM_ERROR("si_process_firmware_header failed\n");
6397 
		return ret;
6398 
	}
6399 
	ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6400 
	if (ret) {
6401 
		DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6402 
		return ret;
6403 
	}
6404 
	ret = si_init_smc_table(rdev);
6405 
	if (ret) {
6406 
		DRM_ERROR("si_init_smc_table failed\n");
6407 
		return ret;
6408 
	}
6409 
	ret = si_init_smc_spll_table(rdev);
6410 
	if (ret) {
6411 
		DRM_ERROR("si_init_smc_spll_table failed\n");
6412 
		return ret;
6413 
	}
6414 
	ret = si_init_arb_table_index(rdev);
6415 
	if (ret) {
6416 
		DRM_ERROR("si_init_arb_table_index failed\n");
6417 
		return ret;
6418 
	}
6419 
	if (eg_pi->dynamic_ac_timing) {
6420 
		ret = si_populate_mc_reg_table(rdev, boot_ps);
6421 
		if (ret) {
6422 
			DRM_ERROR("si_populate_mc_reg_table failed\n");
6423 
			return ret;
6424 
		}
6425 
	}
6426 
	ret = si_initialize_smc_cac_tables(rdev);
6427 
	if (ret) {
6428 
		DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6429 
		return ret;
6430 
	}
6431 
	ret = si_initialize_hardware_cac_manager(rdev);
6432 
	if (ret) {
6433 
		DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6434 
		return ret;
6435 
	}
6436 
	ret = si_initialize_smc_dte_tables(rdev);
6437 
	if (ret) {
6438 
		DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6439 
		return ret;
6440 
	}
6441 
	ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6442 
	if (ret) {
6443 
		DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6444 
		return ret;
6445 
	}
6446 
	ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6447 
	if (ret) {
6448 
		DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6449 
		return ret;
6450 
	}
6451 
	si_program_response_times(rdev);
6452 
	si_program_ds_registers(rdev);
6453 
	si_dpm_start_smc(rdev);
6454 
	ret = si_notify_smc_display_change(rdev, false);
6455 
	if (ret) {
6456 
		DRM_ERROR("si_notify_smc_display_change failed\n");
6457 
		return ret;
6458 
	}
6459 
	si_enable_sclk_control(rdev, true);
6460 
	si_start_dpm(rdev);
6461 
 
6462 
	si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6463 
 
5271 serge 6464 
	si_thermal_start_thermal_controller(rdev);
6465 
 
5078 serge 6466 
	ni_update_current_ps(rdev, boot_ps);
6467 
 
6468 
	return 0;
6469 
}
6470 
 
5271 serge 6471 
static int si_set_temperature_range(struct radeon_device *rdev)
6472 
{
6473 
	int ret;
6474 
 
6475 
	ret = si_thermal_enable_alert(rdev, false);
6476 
	if (ret)
6477 
		return ret;
6478 
	ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6479 
	if (ret)
6480 
		return ret;
6481 
	ret = si_thermal_enable_alert(rdev, true);
6482 
	if (ret)
6483 
		return ret;
6484 
 
6485 
	return ret;
6486 
}
6487 
 
5078 serge 6488 
int si_dpm_late_enable(struct radeon_device *rdev)
6489 
{
6490 
	int ret;
6491 
 
5271 serge 6492 
	ret = si_set_temperature_range(rdev);
6104 serge 6493 
	if (ret)
6494 
		return ret;
5078 serge 6495 
 
5271 serge 6496 
	return ret;
5078 serge 6497 
}
6498 
 
6499 
void si_dpm_disable(struct radeon_device *rdev)
6500 
{
6501 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6502 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6503 
 
6504 
	if (!si_is_smc_running(rdev))
6505 
		return;
5271 serge 6506 
	si_thermal_stop_thermal_controller(rdev);
5078 serge 6507 
	si_disable_ulv(rdev);
6508 
	si_clear_vc(rdev);
6509 
	if (pi->thermal_protection)
6510 
		si_enable_thermal_protection(rdev, false);
6511 
	si_enable_power_containment(rdev, boot_ps, false);
6512 
	si_enable_smc_cac(rdev, boot_ps, false);
6513 
	si_enable_spread_spectrum(rdev, false);
6514 
	si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6515 
	si_stop_dpm(rdev);
6516 
	si_reset_to_default(rdev);
6517 
	si_dpm_stop_smc(rdev);
6518 
	si_force_switch_to_arb_f0(rdev);
6519 
 
6520 
	ni_update_current_ps(rdev, boot_ps);
6521 
}
6522 
 
6523 
int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6524 
{
6525 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6526 
	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6527 
	struct radeon_ps *new_ps = &requested_ps;
6528 
 
6529 
	ni_update_requested_ps(rdev, new_ps);
6530 
 
6531 
	si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6532 
 
6533 
	return 0;
6534 
}
6535 
 
6536 
static int si_power_control_set_level(struct radeon_device *rdev)
6537 
{
6538 
	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6539 
	int ret;
6540 
 
6541 
	ret = si_restrict_performance_levels_before_switch(rdev);
6542 
	if (ret)
6543 
		return ret;
6544 
	ret = si_halt_smc(rdev);
6545 
	if (ret)
6546 
		return ret;
6547 
	ret = si_populate_smc_tdp_limits(rdev, new_ps);
6548 
	if (ret)
6549 
		return ret;
6550 
	ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6551 
	if (ret)
6552 
		return ret;
6553 
	ret = si_resume_smc(rdev);
6554 
	if (ret)
6555 
		return ret;
6556 
	ret = si_set_sw_state(rdev);
6557 
	if (ret)
6558 
		return ret;
6559 
	return 0;
6560 
}
6561 
 
6562 
int si_dpm_set_power_state(struct radeon_device *rdev)
6563 
{
6564 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6565 
	struct radeon_ps *new_ps = &eg_pi->requested_rps;
6566 
	struct radeon_ps *old_ps = &eg_pi->current_rps;
6567 
	int ret;
6568 
 
6569 
	ret = si_disable_ulv(rdev);
6570 
	if (ret) {
6571 
		DRM_ERROR("si_disable_ulv failed\n");
6572 
		return ret;
6573 
	}
6574 
	ret = si_restrict_performance_levels_before_switch(rdev);
6575 
	if (ret) {
6576 
		DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6577 
		return ret;
6578 
	}
6579 
	if (eg_pi->pcie_performance_request)
6580 
		si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6581 
	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6582 
	ret = si_enable_power_containment(rdev, new_ps, false);
6583 
	if (ret) {
6584 
		DRM_ERROR("si_enable_power_containment failed\n");
6585 
		return ret;
6586 
	}
6587 
	ret = si_enable_smc_cac(rdev, new_ps, false);
6588 
	if (ret) {
6589 
		DRM_ERROR("si_enable_smc_cac failed\n");
6590 
		return ret;
6591 
	}
6592 
	ret = si_halt_smc(rdev);
6593 
	if (ret) {
6594 
		DRM_ERROR("si_halt_smc failed\n");
6595 
		return ret;
6596 
	}
6597 
	ret = si_upload_sw_state(rdev, new_ps);
6598 
	if (ret) {
6599 
		DRM_ERROR("si_upload_sw_state failed\n");
6600 
		return ret;
6601 
	}
6602 
	ret = si_upload_smc_data(rdev);
6603 
	if (ret) {
6604 
		DRM_ERROR("si_upload_smc_data failed\n");
6605 
		return ret;
6606 
	}
6607 
	ret = si_upload_ulv_state(rdev);
6608 
	if (ret) {
6609 
		DRM_ERROR("si_upload_ulv_state failed\n");
6610 
		return ret;
6611 
	}
6612 
	if (eg_pi->dynamic_ac_timing) {
6613 
		ret = si_upload_mc_reg_table(rdev, new_ps);
6614 
		if (ret) {
6615 
			DRM_ERROR("si_upload_mc_reg_table failed\n");
6616 
			return ret;
6617 
		}
6618 
	}
6619 
	ret = si_program_memory_timing_parameters(rdev, new_ps);
6620 
	if (ret) {
6621 
		DRM_ERROR("si_program_memory_timing_parameters failed\n");
6622 
		return ret;
6623 
	}
6624 
	si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6625 
 
6626 
	ret = si_resume_smc(rdev);
6627 
	if (ret) {
6628 
		DRM_ERROR("si_resume_smc failed\n");
6629 
		return ret;
6630 
	}
6631 
	ret = si_set_sw_state(rdev);
6632 
	if (ret) {
6633 
		DRM_ERROR("si_set_sw_state failed\n");
6634 
		return ret;
6635 
	}
6636 
	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6104 serge 6637 
	si_set_vce_clock(rdev, new_ps, old_ps);
5078 serge 6638 
	if (eg_pi->pcie_performance_request)
6639 
		si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6640 
	ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6641 
	if (ret) {
6642 
		DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6643 
		return ret;
6644 
	}
6645 
	ret = si_enable_smc_cac(rdev, new_ps, true);
6646 
	if (ret) {
6647 
		DRM_ERROR("si_enable_smc_cac failed\n");
6648 
		return ret;
6649 
	}
6650 
	ret = si_enable_power_containment(rdev, new_ps, true);
6651 
	if (ret) {
6652 
		DRM_ERROR("si_enable_power_containment failed\n");
6653 
		return ret;
6654 
	}
6655 
 
6656 
	ret = si_power_control_set_level(rdev);
6657 
	if (ret) {
6658 
		DRM_ERROR("si_power_control_set_level failed\n");
6659 
		return ret;
6660 
	}
6661 
 
6662 
	return 0;
6663 
}
6664 
 
6665 
void si_dpm_post_set_power_state(struct radeon_device *rdev)
6666 
{
6667 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6668 
	struct radeon_ps *new_ps = &eg_pi->requested_rps;
6669 
 
6670 
	ni_update_current_ps(rdev, new_ps);
6671 
}
6672 
 
6104 serge 6673 
#if 0
5078 serge 6674 
void si_dpm_reset_asic(struct radeon_device *rdev)
6675 
{
6676 
	si_restrict_performance_levels_before_switch(rdev);
6677 
	si_disable_ulv(rdev);
6678 
	si_set_boot_state(rdev);
6679 
}
6104 serge 6680 
#endif
5078 serge 6681 
 
6682 
void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6683 
{
6684 
	si_program_display_gap(rdev);
6685 
}
6686 
 
6687 
union power_info {
6688 
	struct _ATOM_POWERPLAY_INFO info;
6689 
	struct _ATOM_POWERPLAY_INFO_V2 info_2;
6690 
	struct _ATOM_POWERPLAY_INFO_V3 info_3;
6691 
	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6692 
	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6693 
	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6694 
};
6695 
 
6696 
union pplib_clock_info {
6697 
	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6698 
	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6699 
	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6700 
	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6701 
	struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6702 
};
6703 
 
6704 
union pplib_power_state {
6705 
	struct _ATOM_PPLIB_STATE v1;
6706 
	struct _ATOM_PPLIB_STATE_V2 v2;
6707 
};
6708 
 
6709 
static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6710 
					  struct radeon_ps *rps,
6711 
					  struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6712 
					  u8 table_rev)
6713 
{
6714 
	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6715 
	rps->class = le16_to_cpu(non_clock_info->usClassification);
6716 
	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6717 
 
6718 
	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6719 
		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6720 
		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6721 
	} else if (r600_is_uvd_state(rps->class, rps->class2)) {
6722 
		rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6723 
		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6724 
	} else {
6725 
		rps->vclk = 0;
6726 
		rps->dclk = 0;
6727 
	}
6728 
 
6729 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6730 
		rdev->pm.dpm.boot_ps = rps;
6731 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6732 
		rdev->pm.dpm.uvd_ps = rps;
6733 
}
6734 
 
6735 
static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6736 
				      struct radeon_ps *rps, int index,
6737 
				      union pplib_clock_info *clock_info)
6738 
{
6739 
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6740 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6741 
	struct si_power_info *si_pi = si_get_pi(rdev);
6742 
	struct ni_ps *ps = ni_get_ps(rps);
6743 
	u16 leakage_voltage;
6744 
	struct rv7xx_pl *pl = &ps->performance_levels[index];
6745 
	int ret;
6746 
 
6747 
	ps->performance_level_count = index + 1;
6748 
 
6749 
	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6750 
	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6751 
	pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6752 
	pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6753 
 
6754 
	pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6755 
	pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6756 
	pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6757 
	pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6758 
						 si_pi->sys_pcie_mask,
6759 
						 si_pi->boot_pcie_gen,
6760 
						 clock_info->si.ucPCIEGen);
6761 
 
6762 
	/* patch up vddc if necessary */
6763 
	ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6764 
							&leakage_voltage);
6765 
	if (ret == 0)
6766 
		pl->vddc = leakage_voltage;
6767 
 
6768 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6769 
		pi->acpi_vddc = pl->vddc;
6770 
		eg_pi->acpi_vddci = pl->vddci;
6771 
		si_pi->acpi_pcie_gen = pl->pcie_gen;
6772 
	}
6773 
 
6774 
	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6775 
	    index == 0) {
6776 
		/* XXX disable for A0 tahiti */
5179 serge 6777 
		si_pi->ulv.supported = false;
5078 serge 6778 
		si_pi->ulv.pl = *pl;
6779 
		si_pi->ulv.one_pcie_lane_in_ulv = false;
6780 
		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6781 
		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6782 
		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6783 
	}
6784 
 
6785 
	if (pi->min_vddc_in_table > pl->vddc)
6786 
		pi->min_vddc_in_table = pl->vddc;
6787 
 
6788 
	if (pi->max_vddc_in_table < pl->vddc)
6789 
		pi->max_vddc_in_table = pl->vddc;
6790 
 
6791 
	/* patch up boot state */
6792 
	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6793 
		u16 vddc, vddci, mvdd;
6794 
		radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6795 
		pl->mclk = rdev->clock.default_mclk;
6796 
		pl->sclk = rdev->clock.default_sclk;
6797 
		pl->vddc = vddc;
6798 
		pl->vddci = vddci;
6799 
		si_pi->mvdd_bootup_value = mvdd;
6800 
	}
6801 
 
6802 
	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6803 
	    ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6804 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6805 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6806 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6807 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6808 
	}
6809 
}
6810 
 
6811 
static int si_parse_power_table(struct radeon_device *rdev)
6812 
{
6813 
	struct radeon_mode_info *mode_info = &rdev->mode_info;
6814 
	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6815 
	union pplib_power_state *power_state;
6816 
	int i, j, k, non_clock_array_index, clock_array_index;
6817 
	union pplib_clock_info *clock_info;
6818 
	struct _StateArray *state_array;
6819 
	struct _ClockInfoArray *clock_info_array;
6820 
	struct _NonClockInfoArray *non_clock_info_array;
6821 
	union power_info *power_info;
6822 
	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6823 
        u16 data_offset;
6824 
	u8 frev, crev;
6825 
	u8 *power_state_offset;
6826 
	struct ni_ps *ps;
6827 
 
6828 
	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6829 
				   &frev, &crev, &data_offset))
6830 
		return -EINVAL;
6831 
	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6832 
 
6833 
	state_array = (struct _StateArray *)
6834 
		(mode_info->atom_context->bios + data_offset +
6835 
		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6836 
	clock_info_array = (struct _ClockInfoArray *)
6837 
		(mode_info->atom_context->bios + data_offset +
6838 
		 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6839 
	non_clock_info_array = (struct _NonClockInfoArray *)
6840 
		(mode_info->atom_context->bios + data_offset +
6841 
		 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6842 
 
6843 
	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6844 
				  state_array->ucNumEntries, GFP_KERNEL);
6845 
	if (!rdev->pm.dpm.ps)
6846 
		return -ENOMEM;
6847 
	power_state_offset = (u8 *)state_array->states;
6848 
	for (i = 0; i < state_array->ucNumEntries; i++) {
6849 
		u8 *idx;
6850 
		power_state = (union pplib_power_state *)power_state_offset;
6851 
		non_clock_array_index = power_state->v2.nonClockInfoIndex;
6852 
		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6853 
			&non_clock_info_array->nonClockInfo[non_clock_array_index];
6854 
		if (!rdev->pm.power_state[i].clock_info)
6855 
			return -EINVAL;
6856 
		ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6857 
		if (ps == NULL) {
6858 
			kfree(rdev->pm.dpm.ps);
6859 
			return -ENOMEM;
6860 
		}
6861 
		rdev->pm.dpm.ps[i].ps_priv = ps;
6862 
		si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6863 
					      non_clock_info,
6864 
					      non_clock_info_array->ucEntrySize);
6865 
		k = 0;
6866 
		idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6867 
		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6868 
			clock_array_index = idx[j];
6869 
			if (clock_array_index >= clock_info_array->ucNumEntries)
6870 
				continue;
6871 
			if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6872 
				break;
6873 
			clock_info = (union pplib_clock_info *)
6874 
				((u8 *)&clock_info_array->clockInfo[0] +
6875 
				 (clock_array_index * clock_info_array->ucEntrySize));
6876 
			si_parse_pplib_clock_info(rdev,
6877 
						  &rdev->pm.dpm.ps[i], k,
6878 
						  clock_info);
6879 
			k++;
6880 
		}
6881 
		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6882 
	}
6883 
	rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6104 serge 6884 
 
6885 
	/* fill in the vce power states */
6886 
	for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6887 
		u32 sclk, mclk;
6888 
		clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6889 
		clock_info = (union pplib_clock_info *)
6890 
			&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6891 
		sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6892 
		sclk |= clock_info->si.ucEngineClockHigh << 16;
6893 
		mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6894 
		mclk |= clock_info->si.ucMemoryClockHigh << 16;
6895 
		rdev->pm.dpm.vce_states[i].sclk = sclk;
6896 
		rdev->pm.dpm.vce_states[i].mclk = mclk;
6897 
	}
6898 
 
5078 serge 6899 
	return 0;
6900 
}
6901 
 
6902 
int si_dpm_init(struct radeon_device *rdev)
6903 
{
6904 
	struct rv7xx_power_info *pi;
6905 
	struct evergreen_power_info *eg_pi;
6906 
	struct ni_power_info *ni_pi;
6907 
	struct si_power_info *si_pi;
6908 
	struct atom_clock_dividers dividers;
6909 
	int ret;
6910 
	u32 mask;
6911 
 
6912 
	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6913 
	if (si_pi == NULL)
6914 
		return -ENOMEM;
6915 
	rdev->pm.dpm.priv = si_pi;
6916 
	ni_pi = &si_pi->ni;
6917 
	eg_pi = &ni_pi->eg;
6918 
	pi = &eg_pi->rv7xx;
6919 
 
6920 
	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6921 
	if (ret)
6922 
		si_pi->sys_pcie_mask = 0;
6923 
	else
6924 
		si_pi->sys_pcie_mask = mask;
6925 
	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6926 
	si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6927 
 
6928 
	si_set_max_cu_value(rdev);
6929 
 
6930 
	rv770_get_max_vddc(rdev);
6931 
	si_get_leakage_vddc(rdev);
6932 
	si_patch_dependency_tables_based_on_leakage(rdev);
6933 
 
6934 
	pi->acpi_vddc = 0;
6935 
	eg_pi->acpi_vddci = 0;
6936 
	pi->min_vddc_in_table = 0;
6937 
	pi->max_vddc_in_table = 0;
6938 
 
6939 
	ret = r600_get_platform_caps(rdev);
6940 
	if (ret)
6941 
		return ret;
6942 
 
6104 serge 6943 
	ret = r600_parse_extended_power_table(rdev);
5078 serge 6944 
	if (ret)
6945 
		return ret;
6104 serge 6946 
 
6947 
	ret = si_parse_power_table(rdev);
5078 serge 6948 
	if (ret)
6949 
		return ret;
6950 
 
6951 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6952 
		kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6953 
	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6954 
		r600_free_extended_power_table(rdev);
6955 
		return -ENOMEM;
6956 
	}
6957 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6958 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6959 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6960 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6961 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6962 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6963 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6964 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6965 
	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6966 
 
6967 
	if (rdev->pm.dpm.voltage_response_time == 0)
6968 
		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6969 
	if (rdev->pm.dpm.backbias_response_time == 0)
6970 
		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6971 
 
6972 
	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6973 
					     0, false, ÷rs);
6974 
	if (ret)
6975 
		pi->ref_div = dividers.ref_div + 1;
6976 
	else
6977 
		pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6978 
 
6979 
	eg_pi->smu_uvd_hs = false;
6980 
 
6981 
	pi->mclk_strobe_mode_threshold = 40000;
6982 
	if (si_is_special_1gb_platform(rdev))
6983 
		pi->mclk_stutter_mode_threshold = 0;
6984 
	else
6985 
		pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6986 
	pi->mclk_edc_enable_threshold = 40000;
6987 
	eg_pi->mclk_edc_wr_enable_threshold = 40000;
6988 
 
6989 
	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6990 
 
6991 
	pi->voltage_control =
6992 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6993 
					    VOLTAGE_OBJ_GPIO_LUT);
6994 
	if (!pi->voltage_control) {
6995 
		si_pi->voltage_control_svi2 =
6996 
			radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6997 
						    VOLTAGE_OBJ_SVID2);
6998 
		if (si_pi->voltage_control_svi2)
6999 
			radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7000 
						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7001 
	}
7002 
 
7003 
	pi->mvdd_control =
7004 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7005 
					    VOLTAGE_OBJ_GPIO_LUT);
7006 
 
7007 
	eg_pi->vddci_control =
7008 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7009 
					    VOLTAGE_OBJ_GPIO_LUT);
7010 
	if (!eg_pi->vddci_control)
7011 
		si_pi->vddci_control_svi2 =
7012 
			radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7013 
						    VOLTAGE_OBJ_SVID2);
7014 
 
7015 
	si_pi->vddc_phase_shed_control =
7016 
		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7017 
					    VOLTAGE_OBJ_PHASE_LUT);
7018 
 
7019 
	rv770_get_engine_memory_ss(rdev);
7020 
 
7021 
	pi->asi = RV770_ASI_DFLT;
7022 
	pi->pasi = CYPRESS_HASI_DFLT;
7023 
	pi->vrc = SISLANDS_VRC_DFLT;
7024 
 
7025 
	pi->gfx_clock_gating = true;
7026 
 
7027 
	eg_pi->sclk_deep_sleep = true;
7028 
	si_pi->sclk_deep_sleep_above_low = false;
7029 
 
7030 
	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7031 
		pi->thermal_protection = true;
7032 
	else
7033 
		pi->thermal_protection = false;
7034 
 
7035 
	eg_pi->dynamic_ac_timing = true;
7036 
 
7037 
	eg_pi->light_sleep = true;
7038 
#if defined(CONFIG_ACPI)
7039 
	eg_pi->pcie_performance_request =
7040 
		radeon_acpi_is_pcie_performance_request_supported(rdev);
7041 
#else
7042 
	eg_pi->pcie_performance_request = false;
7043 
#endif
7044 
 
7045 
	si_pi->sram_end = SMC_RAM_END;
7046 
 
7047 
	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7048 
	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7049 
	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7050 
	rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7051 
	rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7052 
	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7053 
	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7054 
 
7055 
	si_initialize_powertune_defaults(rdev);
7056 
 
7057 
	/* make sure dc limits are valid */
7058 
	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7059 
	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7060 
		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7061 
			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7062 
 
5271 serge 7063 
	si_pi->fan_ctrl_is_in_default_mode = true;
7064 
 
5078 serge 7065 
	return 0;
7066 
}
7067 
 
7068 
void si_dpm_fini(struct radeon_device *rdev)
7069 
{
7070 
	int i;
7071 
 
7072 
	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7073 
		kfree(rdev->pm.dpm.ps[i].ps_priv);
7074 
	}
7075 
	kfree(rdev->pm.dpm.ps);
7076 
	kfree(rdev->pm.dpm.priv);
7077 
	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7078 
	r600_free_extended_power_table(rdev);
7079 
}
7080 
 
7081 
void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7082 
						    struct seq_file *m)
7083 
{
7084 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7085 
	struct radeon_ps *rps = &eg_pi->current_rps;
7086 
	struct ni_ps *ps = ni_get_ps(rps);
7087 
	struct rv7xx_pl *pl;
7088 
	u32 current_index =
7089 
		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7090 
		CURRENT_STATE_INDEX_SHIFT;
7091 
 
7092 
	if (current_index >= ps->performance_level_count) {
7093 
		seq_printf(m, "invalid dpm profile %d\n", current_index);
7094 
	} else {
7095 
		pl = &ps->performance_levels[current_index];
7096 
		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7097 
		seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7098 
			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7099 
	}
7100 
}
6104 serge 7101 
 
7102 
u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7103 
{
7104 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7105 
	struct radeon_ps *rps = &eg_pi->current_rps;
7106 
	struct ni_ps *ps = ni_get_ps(rps);
7107 
	struct rv7xx_pl *pl;
7108 
	u32 current_index =
7109 
		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7110 
		CURRENT_STATE_INDEX_SHIFT;
7111 
 
7112 
	if (current_index >= ps->performance_level_count) {
7113 
		return 0;
7114 
	} else {
7115 
		pl = &ps->performance_levels[current_index];
7116 
		return pl->sclk;
7117 
	}
7118 
}
7119 
 
7120 
u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7121 
{
7122 
	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7123 
	struct radeon_ps *rps = &eg_pi->current_rps;
7124 
	struct ni_ps *ps = ni_get_ps(rps);
7125 
	struct rv7xx_pl *pl;
7126 
	u32 current_index =
7127 
		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7128 
		CURRENT_STATE_INDEX_SHIFT;
7129 
 
7130 
	if (current_index >= ps->performance_level_count) {
7131 
		return 0;
7132 
	} else {
7133 
		pl = &ps->performance_levels[current_index];
7134 
		return pl->mclk;
7135 
	}
7136 
}