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/*

 * Copyright 2008 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Dave Airlie

 *          Alex Deucher

 *          Jerome Glisse

 */

//#include 

//#include 

#include "drmP.h"

#include "radeon.h"

#include "radeon_drm.h"

#include "rv770d.h"

#include "atom.h"

#include "avivod.h"

#define R700_PFP_UCODE_SIZE 848

#define R700_PM4_UCODE_SIZE 1360

static void rv770_gpu_init(struct radeon_device *rdev);

void rv770_fini(struct radeon_device *rdev);

/*

 * GART

 */

int rv770_pcie_gart_enable(struct radeon_device *rdev)

{

	u32 tmp;

	int r, i;

	if (rdev->gart.table.vram.robj == NULL) {

		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");

		return -EINVAL;

	}

	r = radeon_gart_table_vram_pin(rdev);

	if (r)

		return r;

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

				EFFECTIVE_L2_QUEUE_SIZE(7));

	WREG32(VM_L2_CNTL2, 0);

	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

	/* Setup TLB control */

	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

		SYSTEM_ACCESS_MODE_NOT_IN_SYS |

		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |

		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);

	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

			(u32)(rdev->dummy_page.addr >> 12));

	for (i = 1; i < 7; i++)

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

	r600_pcie_gart_tlb_flush(rdev);

	rdev->gart.ready = true;

	return 0;

}

void rv770_pcie_gart_disable(struct radeon_device *rdev)

{

	u32 tmp;

	int i, r;

	/* Disable all tables */

	for (i = 0; i < 7; i++)

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |

				EFFECTIVE_L2_QUEUE_SIZE(7));

	WREG32(VM_L2_CNTL2, 0);

	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

	/* Setup TLB control */

	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);

	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	if (rdev->gart.table.vram.robj) {

//       radeon_object_kunmap(rdev->gart.table.vram.robj);

//       radeon_object_unpin(rdev->gart.table.vram.robj);

	}

}

void rv770_pcie_gart_fini(struct radeon_device *rdev)

{

	rv770_pcie_gart_disable(rdev);

//   radeon_gart_table_vram_free(rdev);

    radeon_gart_fini(rdev);

}

void rv770_agp_enable(struct radeon_device *rdev)

{

	u32 tmp;

	int i;

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

				EFFECTIVE_L2_QUEUE_SIZE(7));

	WREG32(VM_L2_CNTL2, 0);

	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

	/* Setup TLB control */

	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

		SYSTEM_ACCESS_MODE_NOT_IN_SYS |

		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |

		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);

	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	for (i = 0; i < 7; i++)

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

}

static void rv770_mc_program(struct radeon_device *rdev)

{

	struct rv515_mc_save save;

	u32 tmp;

	int i, j;

	/* Initialize HDP */

	for (i = 0, j = 0; i < 32; i++, j += 0x18) {

		WREG32((0x2c14 + j), 0x00000000);

		WREG32((0x2c18 + j), 0x00000000);

		WREG32((0x2c1c + j), 0x00000000);

		WREG32((0x2c20 + j), 0x00000000);

		WREG32((0x2c24 + j), 0x00000000);

	}

	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);

	rv515_mc_stop(rdev, &save);

	if (r600_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}

	/* Lockout access through VGA aperture*/

	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

	/* Update configuration */

	if (rdev->flags & RADEON_IS_AGP) {

		if (rdev->mc.vram_start < rdev->mc.gtt_start) {

			/* VRAM before AGP */

			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

				rdev->mc.vram_start >> 12);

			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

				rdev->mc.gtt_end >> 12);

		} else {

			/* VRAM after AGP */

			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

				rdev->mc.gtt_start >> 12);

			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

				rdev->mc.vram_end >> 12);

		}

	} else {

		WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

			rdev->mc.vram_start >> 12);

		WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			rdev->mc.vram_end >> 12);

	}

	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);

	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;

	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);

	WREG32(MC_VM_FB_LOCATION, tmp);

	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

	WREG32(HDP_NONSURFACE_INFO, (2 << 7));

	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);

	if (rdev->flags & RADEON_IS_AGP) {

		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);

		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);

		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);

	} else {

		WREG32(MC_VM_AGP_BASE, 0);

		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

	}

	if (r600_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}

	rv515_mc_resume(rdev, &save);

	/* we need to own VRAM, so turn off the VGA renderer here

	 * to stop it overwriting our objects */

	rv515_vga_render_disable(rdev);

}

/*

 * CP.

 */

void r700_cp_stop(struct radeon_device *rdev)

{

	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

}

#if 0

static int rv770_cp_load_microcode(struct radeon_device *rdev)

{

	const __be32 *fw_data;

	int i;

	if (!rdev->me_fw || !rdev->pfp_fw)

		return -EINVAL;

	r700_cp_stop(rdev);

	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));

	/* Reset cp */

	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);

	RREG32(GRBM_SOFT_RESET);

	mdelay(15);

	WREG32(GRBM_SOFT_RESET, 0);

	fw_data = (const __be32 *)rdev->pfp_fw->data;

	WREG32(CP_PFP_UCODE_ADDR, 0);

	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)

		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

	WREG32(CP_PFP_UCODE_ADDR, 0);

	fw_data = (const __be32 *)rdev->me_fw->data;

	WREG32(CP_ME_RAM_WADDR, 0);

	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)

		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

	WREG32(CP_PFP_UCODE_ADDR, 0);

	WREG32(CP_ME_RAM_WADDR, 0);