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1179 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
#ifndef __RV515D_H__
29
#define __RV515D_H__
30
 
31
/*
32
 * RV515 registers
33
 */
34
#define PCIE_INDEX			0x0030
35
#define PCIE_DATA			0x0034
36
#define	MC_IND_INDEX			0x0070
37
#define		MC_IND_WR_EN				(1 << 24)
38
#define	MC_IND_DATA			0x0074
39
#define	RBBM_SOFT_RESET			0x00F0
40
#define	CONFIG_MEMSIZE			0x00F8
41
#define HDP_FB_LOCATION			0x0134
42
#define	CP_CSQ_CNTL			0x0740
43
#define	CP_CSQ_MODE			0x0744
44
#define	CP_CSQ_ADDR			0x07F0
45
#define	CP_CSQ_DATA			0x07F4
46
#define	CP_CSQ_STAT			0x07F8
47
#define	CP_CSQ2_STAT			0x07FC
48
#define	RBBM_STATUS			0x0E40
49
#define	DST_PIPE_CONFIG			0x170C
50
#define	WAIT_UNTIL			0x1720
51
#define		WAIT_2D_IDLE				(1 << 14)
52
#define		WAIT_3D_IDLE				(1 << 15)
53
#define		WAIT_2D_IDLECLEAN			(1 << 16)
54
#define		WAIT_3D_IDLECLEAN			(1 << 17)
55
#define	ISYNC_CNTL			0x1724
56
#define		ISYNC_ANY2D_IDLE3D			(1 << 0)
57
#define		ISYNC_ANY3D_IDLE2D			(1 << 1)
58
#define		ISYNC_TRIG2D_IDLE3D			(1 << 2)
59
#define		ISYNC_TRIG3D_IDLE2D			(1 << 3)
60
#define		ISYNC_WAIT_IDLEGUI			(1 << 4)
61
#define		ISYNC_CPSCRATCH_IDLEGUI			(1 << 5)
62
#define	VAP_INDEX_OFFSET		0x208C
63
#define	VAP_PVS_STATE_FLUSH_REG		0x2284
64
#define	GB_ENABLE			0x4008
65
#define	GB_MSPOS0			0x4010
66
#define		MS_X0_SHIFT				0
67
#define		MS_Y0_SHIFT				4
68
#define		MS_X1_SHIFT				8
69
#define		MS_Y1_SHIFT				12
70
#define		MS_X2_SHIFT				16
71
#define		MS_Y2_SHIFT				20
72
#define		MSBD0_Y_SHIFT				24
73
#define		MSBD0_X_SHIFT				28
74
#define	GB_MSPOS1			0x4014
75
#define		MS_X3_SHIFT				0
76
#define		MS_Y3_SHIFT				4
77
#define		MS_X4_SHIFT				8
78
#define		MS_Y4_SHIFT				12
79
#define		MS_X5_SHIFT				16
80
#define		MS_Y5_SHIFT				20
81
#define		MSBD1_SHIFT				24
82
#define GB_TILE_CONFIG			0x4018
83
#define		ENABLE_TILING				(1 << 0)
84
#define		PIPE_COUNT_MASK				0x0000000E
85
#define		PIPE_COUNT_SHIFT			1
86
#define		TILE_SIZE_8				(0 << 4)
87
#define		TILE_SIZE_16				(1 << 4)
88
#define		TILE_SIZE_32				(2 << 4)
89
#define		SUBPIXEL_1_12				(0 << 16)
90
#define		SUBPIXEL_1_16				(1 << 16)
91
#define	GB_SELECT			0x401C
92
#define	GB_AA_CONFIG			0x4020
93
#define	GB_PIPE_SELECT			0x402C
94
#define	GA_ENHANCE			0x4274
95
#define		GA_DEADLOCK_CNTL			(1 << 0)
96
#define		GA_FASTSYNC_CNTL			(1 << 1)
97
#define	GA_POLY_MODE			0x4288
98
#define		FRONT_PTYPE_POINT			(0 << 4)
99
#define		FRONT_PTYPE_LINE			(1 << 4)
100
#define		FRONT_PTYPE_TRIANGE			(2 << 4)
101
#define		BACK_PTYPE_POINT			(0 << 7)
102
#define		BACK_PTYPE_LINE				(1 << 7)
103
#define		BACK_PTYPE_TRIANGE			(2 << 7)
104
#define	GA_ROUND_MODE			0x428C
105
#define		GEOMETRY_ROUND_TRUNC			(0 << 0)
106
#define		GEOMETRY_ROUND_NEAREST			(1 << 0)
107
#define		COLOR_ROUND_TRUNC			(0 << 2)
108
#define		COLOR_ROUND_NEAREST			(1 << 2)
109
#define	SU_REG_DEST			0x42C8
110
#define	RB3D_DSTCACHE_CTLSTAT		0x4E4C
111
#define		RB3D_DC_FLUSH				(2 << 0)
112
#define		RB3D_DC_FREE				(2 << 2)
113
#define		RB3D_DC_FINISH				(1 << 4)
114
#define ZB_ZCACHE_CTLSTAT		0x4F18
115
#define		ZC_FLUSH				(1 << 0)
116
#define		ZC_FREE					(1 << 1)
117
#define DC_LB_MEMORY_SPLIT		0x6520
118
#define		DC_LB_MEMORY_SPLIT_MASK			0x00000003
119
#define		DC_LB_MEMORY_SPLIT_SHIFT		0
120
#define		DC_LB_MEMORY_SPLIT_D1HALF_D2HALF	0
121
#define		DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q		1
122
#define		DC_LB_MEMORY_SPLIT_D1_ONLY		2
123
#define		DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q		3
124
#define		DC_LB_MEMORY_SPLIT_SHIFT_MODE		(1 << 2)
125
#define		DC_LB_DISP1_END_ADR_SHIFT		4
126
#define		DC_LB_DISP1_END_ADR_MASK		0x00007FF0
127
#define D1MODE_PRIORITY_A_CNT		0x6548
128
#define		MODE_PRIORITY_MARK_MASK			0x00007FFF
129
#define		MODE_PRIORITY_OFF			(1 << 16)
130
#define		MODE_PRIORITY_ALWAYS_ON			(1 << 20)
131
#define		MODE_PRIORITY_FORCE_MASK		(1 << 24)
132
#define D1MODE_PRIORITY_B_CNT		0x654C
133
#define LB_MAX_REQ_OUTSTANDING		0x6D58
134
#define		LB_D1_MAX_REQ_OUTSTANDING_MASK		0x0000000F
135
#define		LB_D1_MAX_REQ_OUTSTANDING_SHIFT		0
136
#define		LB_D2_MAX_REQ_OUTSTANDING_MASK		0x000F0000
137
#define		LB_D2_MAX_REQ_OUTSTANDING_SHIFT		16
138
#define D2MODE_PRIORITY_A_CNT		0x6D48
139
#define D2MODE_PRIORITY_B_CNT		0x6D4C
140
 
141
/* ix[MC] registers */
142
#define MC_FB_LOCATION			0x01
143
#define		MC_FB_START_MASK			0x0000FFFF
144
#define		MC_FB_START_SHIFT			0
145
#define		MC_FB_TOP_MASK				0xFFFF0000
146
#define		MC_FB_TOP_SHIFT				16
147
#define MC_AGP_LOCATION			0x02
148
#define		MC_AGP_START_MASK			0x0000FFFF
149
#define		MC_AGP_START_SHIFT			0
150
#define		MC_AGP_TOP_MASK				0xFFFF0000
151
#define		MC_AGP_TOP_SHIFT			16
152
#define MC_AGP_BASE			0x03
153
#define MC_AGP_BASE_2			0x04
154
#define	MC_CNTL				0x5
155
#define		MEM_NUM_CHANNELS_MASK			0x00000003
156
#define	MC_STATUS			0x08
157
#define		MC_STATUS_IDLE				(1 << 4)
158
#define	MC_MISC_LAT_TIMER		0x09
159
#define		MC_CPR_INIT_LAT_MASK			0x0000000F
160
#define		MC_VF_INIT_LAT_MASK			0x000000F0
161
#define		MC_DISP0R_INIT_LAT_MASK			0x00000F00
162
#define		MC_DISP0R_INIT_LAT_SHIFT		8
163
#define		MC_DISP1R_INIT_LAT_MASK			0x0000F000
164
#define		MC_DISP1R_INIT_LAT_SHIFT		12
165
#define		MC_FIXED_INIT_LAT_MASK			0x000F0000
166
#define		MC_E2R_INIT_LAT_MASK			0x00F00000
167
#define		SAME_PAGE_PRIO_MASK			0x0F000000
168
#define		MC_GLOBW_INIT_LAT_MASK			0xF0000000
169
 
170
 
171
/*
172
 * PM4 packet
173
 */
174
#define CP_PACKET0			0x00000000
175
#define		PACKET0_BASE_INDEX_SHIFT	0
176
#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
177
#define		PACKET0_COUNT_SHIFT		16
178
#define		PACKET0_COUNT_MASK		(0x3fff << 16)
179
#define CP_PACKET1			0x40000000
180
#define CP_PACKET2			0x80000000
181
#define		PACKET2_PAD_SHIFT		0
182
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
183
#define CP_PACKET3			0xC0000000
184
#define		PACKET3_IT_OPCODE_SHIFT		8
185
#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
186
#define		PACKET3_COUNT_SHIFT		16
187
#define		PACKET3_COUNT_MASK		(0x3fff << 16)
188
/* PACKET3 op code */
189
#define		PACKET3_NOP			0x10
190
#define		PACKET3_3D_DRAW_VBUF		0x28
191
#define		PACKET3_3D_DRAW_IMMD		0x29
192
#define		PACKET3_3D_DRAW_INDX		0x2A
193
#define		PACKET3_3D_LOAD_VBPNTR		0x2F
194
#define		PACKET3_INDX_BUFFER		0x33
195
#define		PACKET3_3D_DRAW_VBUF_2		0x34
196
#define		PACKET3_3D_DRAW_IMMD_2		0x35
197
#define		PACKET3_3D_DRAW_INDX_2		0x36
198
#define		PACKET3_BITBLT_MULTI		0x9B
199
 
200
#define PACKET0(reg, n)	(CP_PACKET0 |					\
201
			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
202
			 REG_SET(PACKET0_COUNT, (n)))
203
#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
204
#define PACKET3(op, n)	(CP_PACKET3 |					\
205
			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
206
			 REG_SET(PACKET3_COUNT, (n)))
207
 
208
#define	PACKET_TYPE0	0
209
#define	PACKET_TYPE1	1
210
#define	PACKET_TYPE2	2
211
#define	PACKET_TYPE3	3
212
 
213
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
214
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
215
#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
216
#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
217
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
218
 
1221 serge 219
/* Registers */
1963 serge 220
#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
221
#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
222
#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
223
#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
224
#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
225
#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
226
#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
227
#define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)
228
#define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)
229
#define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB
230
#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
231
#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
232
#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
233
#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
234
#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
235
#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
236
#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
237
#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
238
#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
239
#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
240
#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
241
#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
242
#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
243
#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
244
#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
245
#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
246
#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
247
#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
248
#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
249
#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
250
#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
251
#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
252
#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
253
#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
254
#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
255
#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
256
#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
257
#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
258
#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
259
#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
260
#define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)
261
#define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)
262
#define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF
263
#define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)
264
#define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)
265
#define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF
1221 serge 266
#define R_0000F8_CONFIG_MEMSIZE                      0x0000F8
267
#define   S_0000F8_CONFIG_MEMSIZE(x)                   (((x) & 0xFFFFFFFF) << 0)
268
#define   G_0000F8_CONFIG_MEMSIZE(x)                   (((x) >> 0) & 0xFFFFFFFF)
269
#define   C_0000F8_CONFIG_MEMSIZE                      0x00000000
270
#define R_000134_HDP_FB_LOCATION                     0x000134
271
#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
272
#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
273
#define   C_000134_HDP_FB_START                        0xFFFF0000
274
#define R_000300_VGA_RENDER_CONTROL                  0x000300
275
#define   S_000300_VGA_BLINK_RATE(x)                   (((x) & 0x1F) << 0)
276
#define   G_000300_VGA_BLINK_RATE(x)                   (((x) >> 0) & 0x1F)
277
#define   C_000300_VGA_BLINK_RATE                      0xFFFFFFE0
278
#define   S_000300_VGA_BLINK_MODE(x)                   (((x) & 0x3) << 5)
279
#define   G_000300_VGA_BLINK_MODE(x)                   (((x) >> 5) & 0x3)
280
#define   C_000300_VGA_BLINK_MODE                      0xFFFFFF9F
281
#define   S_000300_VGA_CURSOR_BLINK_INVERT(x)          (((x) & 0x1) << 7)
282
#define   G_000300_VGA_CURSOR_BLINK_INVERT(x)          (((x) >> 7) & 0x1)
283
#define   C_000300_VGA_CURSOR_BLINK_INVERT             0xFFFFFF7F
284
#define   S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x)       (((x) & 0x1) << 8)
285
#define   G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x)       (((x) >> 8) & 0x1)
286
#define   C_000300_VGA_EXTD_ADDR_COUNT_ENABLE          0xFFFFFEFF
287
#define   S_000300_VGA_VSTATUS_CNTL(x)                 (((x) & 0x3) << 16)
288
#define   G_000300_VGA_VSTATUS_CNTL(x)                 (((x) >> 16) & 0x3)
289
#define   C_000300_VGA_VSTATUS_CNTL                    0xFFFCFFFF
290
#define   S_000300_VGA_LOCK_8DOT(x)                    (((x) & 0x1) << 24)
291
#define   G_000300_VGA_LOCK_8DOT(x)                    (((x) >> 24) & 0x1)
292
#define   C_000300_VGA_LOCK_8DOT                       0xFEFFFFFF
293
#define   S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25)
294
#define   G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1)
295
#define   C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL    0xFDFFFFFF
296
#define R_000310_VGA_MEMORY_BASE_ADDRESS             0x000310
297
#define   S_000310_VGA_MEMORY_BASE_ADDRESS(x)          (((x) & 0xFFFFFFFF) << 0)
298
#define   G_000310_VGA_MEMORY_BASE_ADDRESS(x)          (((x) >> 0) & 0xFFFFFFFF)
299
#define   C_000310_VGA_MEMORY_BASE_ADDRESS             0x00000000
300
#define R_000328_VGA_HDP_CONTROL                     0x000328
301
#define   S_000328_VGA_MEM_PAGE_SELECT_EN(x)           (((x) & 0x1) << 0)
302
#define   G_000328_VGA_MEM_PAGE_SELECT_EN(x)           (((x) >> 0) & 0x1)
303
#define   C_000328_VGA_MEM_PAGE_SELECT_EN              0xFFFFFFFE
304
#define   S_000328_VGA_RBBM_LOCK_DISABLE(x)            (((x) & 0x1) << 8)
305
#define   G_000328_VGA_RBBM_LOCK_DISABLE(x)            (((x) >> 8) & 0x1)
306
#define   C_000328_VGA_RBBM_LOCK_DISABLE               0xFFFFFEFF
307
#define   S_000328_VGA_SOFT_RESET(x)                   (((x) & 0x1) << 16)
308
#define   G_000328_VGA_SOFT_RESET(x)                   (((x) >> 16) & 0x1)
309
#define   C_000328_VGA_SOFT_RESET                      0xFFFEFFFF
310
#define   S_000328_VGA_TEST_RESET_CONTROL(x)           (((x) & 0x1) << 24)
311
#define   G_000328_VGA_TEST_RESET_CONTROL(x)           (((x) >> 24) & 0x1)
312
#define   C_000328_VGA_TEST_RESET_CONTROL              0xFEFFFFFF
313
#define R_000330_D1VGA_CONTROL                       0x000330
314
#define   S_000330_D1VGA_MODE_ENABLE(x)                (((x) & 0x1) << 0)
315
#define   G_000330_D1VGA_MODE_ENABLE(x)                (((x) >> 0) & 0x1)
316
#define   C_000330_D1VGA_MODE_ENABLE                   0xFFFFFFFE
317
#define   S_000330_D1VGA_TIMING_SELECT(x)              (((x) & 0x1) << 8)
318
#define   G_000330_D1VGA_TIMING_SELECT(x)              (((x) >> 8) & 0x1)
319
#define   C_000330_D1VGA_TIMING_SELECT                 0xFFFFFEFF
320
#define   S_000330_D1VGA_SYNC_POLARITY_SELECT(x)       (((x) & 0x1) << 9)
321
#define   G_000330_D1VGA_SYNC_POLARITY_SELECT(x)       (((x) >> 9) & 0x1)
322
#define   C_000330_D1VGA_SYNC_POLARITY_SELECT          0xFFFFFDFF
323
#define   S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x)     (((x) & 0x1) << 10)
324
#define   G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x)     (((x) >> 10) & 0x1)
325
#define   C_000330_D1VGA_OVERSCAN_TIMING_SELECT        0xFFFFFBFF
326
#define   S_000330_D1VGA_OVERSCAN_COLOR_EN(x)          (((x) & 0x1) << 16)
327
#define   G_000330_D1VGA_OVERSCAN_COLOR_EN(x)          (((x) >> 16) & 0x1)
328
#define   C_000330_D1VGA_OVERSCAN_COLOR_EN             0xFFFEFFFF
329
#define   S_000330_D1VGA_ROTATE(x)                     (((x) & 0x3) << 24)
330
#define   G_000330_D1VGA_ROTATE(x)                     (((x) >> 24) & 0x3)
331
#define   C_000330_D1VGA_ROTATE                        0xFCFFFFFF
332
#define R_000338_D2VGA_CONTROL                       0x000338
333
#define   S_000338_D2VGA_MODE_ENABLE(x)                (((x) & 0x1) << 0)
334
#define   G_000338_D2VGA_MODE_ENABLE(x)                (((x) >> 0) & 0x1)
335
#define   C_000338_D2VGA_MODE_ENABLE                   0xFFFFFFFE
336
#define   S_000338_D2VGA_TIMING_SELECT(x)              (((x) & 0x1) << 8)
337
#define   G_000338_D2VGA_TIMING_SELECT(x)              (((x) >> 8) & 0x1)
338
#define   C_000338_D2VGA_TIMING_SELECT                 0xFFFFFEFF
339
#define   S_000338_D2VGA_SYNC_POLARITY_SELECT(x)       (((x) & 0x1) << 9)
340
#define   G_000338_D2VGA_SYNC_POLARITY_SELECT(x)       (((x) >> 9) & 0x1)
341
#define   C_000338_D2VGA_SYNC_POLARITY_SELECT          0xFFFFFDFF
342
#define   S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x)     (((x) & 0x1) << 10)
343
#define   G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x)     (((x) >> 10) & 0x1)
344
#define   C_000338_D2VGA_OVERSCAN_TIMING_SELECT        0xFFFFFBFF
345
#define   S_000338_D2VGA_OVERSCAN_COLOR_EN(x)          (((x) & 0x1) << 16)
346
#define   G_000338_D2VGA_OVERSCAN_COLOR_EN(x)          (((x) >> 16) & 0x1)
347
#define   C_000338_D2VGA_OVERSCAN_COLOR_EN             0xFFFEFFFF
348
#define   S_000338_D2VGA_ROTATE(x)                     (((x) & 0x3) << 24)
349
#define   G_000338_D2VGA_ROTATE(x)                     (((x) >> 24) & 0x3)
350
#define   C_000338_D2VGA_ROTATE                        0xFCFFFFFF
351
#define R_0007C0_CP_STAT                             0x0007C0
352
#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
353
#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
354
#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
355
#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
356
#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
357
#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
358
#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
359
#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
360
#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
361
#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
362
#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
363
#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
364
#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
365
#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
366
#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
367
#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
368
#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
369
#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
370
#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
371
#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
372
#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
373
#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
374
#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
375
#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
376
#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
377
#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
378
#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
379
#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
380
#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
381
#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
382
#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
383
#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
384
#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
385
#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
386
#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
387
#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
388
#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
389
#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
390
#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
391
#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
392
#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
393
#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
394
#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
395
#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
396
#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
397
#define R_000E40_RBBM_STATUS                         0x000E40
398
#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
399
#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
400
#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
401
#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
402
#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
403
#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
404
#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
405
#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
406
#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
407
#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
408
#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
409
#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
410
#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
411
#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
412
#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
413
#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
414
#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
415
#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
416
#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
417
#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
418
#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
419
#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
420
#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
421
#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
422
#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
423
#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
424
#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
425
#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
426
#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
427
#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
428
#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
429
#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
430
#define   C_000E40_E2_BUSY                             0xFFFDFFFF
431
#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
432
#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
433
#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
434
#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
435
#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
436
#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
437
#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
438
#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
439
#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
440
#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
441
#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
442
#define   C_000E40_RE_BUSY                             0xFFDFFFFF
443
#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
444
#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
445
#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
446
#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
447
#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
448
#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
449
#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
450
#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
451
#define   C_000E40_PB_BUSY                             0xFEFFFFFF
452
#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
453
#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
454
#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
455
#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
456
#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
457
#define   C_000E40_GA_BUSY                             0xFBFFFFFF
458
#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
459
#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
460
#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
461
#define   S_000E40_RBBM_HIBUSY(x)                      (((x) & 0x1) << 28)
462
#define   G_000E40_RBBM_HIBUSY(x)                      (((x) >> 28) & 0x1)
463
#define   C_000E40_RBBM_HIBUSY                         0xEFFFFFFF
464
#define   S_000E40_SKID_CFBUSY(x)                      (((x) & 0x1) << 29)
465
#define   G_000E40_SKID_CFBUSY(x)                      (((x) >> 29) & 0x1)
466
#define   C_000E40_SKID_CFBUSY                         0xDFFFFFFF
467
#define   S_000E40_VAP_VF_BUSY(x)                      (((x) & 0x1) << 30)
468
#define   G_000E40_VAP_VF_BUSY(x)                      (((x) >> 30) & 0x1)
469
#define   C_000E40_VAP_VF_BUSY                         0xBFFFFFFF
470
#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
471
#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
472
#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
473
#define R_006080_D1CRTC_CONTROL                      0x006080
474
#define   S_006080_D1CRTC_MASTER_EN(x)                 (((x) & 0x1) << 0)
475
#define   G_006080_D1CRTC_MASTER_EN(x)                 (((x) >> 0) & 0x1)
476
#define   C_006080_D1CRTC_MASTER_EN                    0xFFFFFFFE
477
#define   S_006080_D1CRTC_SYNC_RESET_SEL(x)            (((x) & 0x1) << 4)
478
#define   G_006080_D1CRTC_SYNC_RESET_SEL(x)            (((x) >> 4) & 0x1)
479
#define   C_006080_D1CRTC_SYNC_RESET_SEL               0xFFFFFFEF
480
#define   S_006080_D1CRTC_DISABLE_POINT_CNTL(x)        (((x) & 0x3) << 8)
481
#define   G_006080_D1CRTC_DISABLE_POINT_CNTL(x)        (((x) >> 8) & 0x3)
482
#define   C_006080_D1CRTC_DISABLE_POINT_CNTL           0xFFFFFCFF
483
#define   S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) & 0x1) << 16)
484
#define   G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) >> 16) & 0x1)
485
#define   C_006080_D1CRTC_CURRENT_MASTER_EN_STATE      0xFFFEFFFF
486
#define   S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
487
#define   G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
488
#define   C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE    0xFEFFFFFF
489
#define R_0060E8_D1CRTC_UPDATE_LOCK                  0x0060E8
490
#define   S_0060E8_D1CRTC_UPDATE_LOCK(x)               (((x) & 0x1) << 0)
491
#define   G_0060E8_D1CRTC_UPDATE_LOCK(x)               (((x) >> 0) & 0x1)
492
#define   C_0060E8_D1CRTC_UPDATE_LOCK                  0xFFFFFFFE
493
#define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS      0x006110
494
#define   S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) & 0xFFFFFFFF) << 0)
495
#define   G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) >> 0) & 0xFFFFFFFF)
496
#define   C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS      0x00000000
497
#define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS    0x006118
498
#define   S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
499
#define   G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
500
#define   C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS    0x00000000
501
#define R_006880_D2CRTC_CONTROL                      0x006880
502
#define   S_006880_D2CRTC_MASTER_EN(x)                 (((x) & 0x1) << 0)
503
#define   G_006880_D2CRTC_MASTER_EN(x)                 (((x) >> 0) & 0x1)
504
#define   C_006880_D2CRTC_MASTER_EN                    0xFFFFFFFE
505
#define   S_006880_D2CRTC_SYNC_RESET_SEL(x)            (((x) & 0x1) << 4)
506
#define   G_006880_D2CRTC_SYNC_RESET_SEL(x)            (((x) >> 4) & 0x1)
507
#define   C_006880_D2CRTC_SYNC_RESET_SEL               0xFFFFFFEF
508
#define   S_006880_D2CRTC_DISABLE_POINT_CNTL(x)        (((x) & 0x3) << 8)
509
#define   G_006880_D2CRTC_DISABLE_POINT_CNTL(x)        (((x) >> 8) & 0x3)
510
#define   C_006880_D2CRTC_DISABLE_POINT_CNTL           0xFFFFFCFF
511
#define   S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) & 0x1) << 16)
512
#define   G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) >> 16) & 0x1)
513
#define   C_006880_D2CRTC_CURRENT_MASTER_EN_STATE      0xFFFEFFFF
514
#define   S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
515
#define   G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
516
#define   C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE    0xFEFFFFFF
517
#define R_0068E8_D2CRTC_UPDATE_LOCK                  0x0068E8
518
#define   S_0068E8_D2CRTC_UPDATE_LOCK(x)               (((x) & 0x1) << 0)
519
#define   G_0068E8_D2CRTC_UPDATE_LOCK(x)               (((x) >> 0) & 0x1)
520
#define   C_0068E8_D2CRTC_UPDATE_LOCK                  0xFFFFFFFE
521
#define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS      0x006910
522
#define   S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) & 0xFFFFFFFF) << 0)
523
#define   G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) >> 0) & 0xFFFFFFFF)
524
#define   C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS      0x00000000
525
#define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS    0x006918
526
#define   S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
527
#define   G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
528
#define   C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS    0x00000000
529
 
530
 
531
#define R_000001_MC_FB_LOCATION                      0x000001
532
#define   S_000001_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
533
#define   G_000001_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
534
#define   C_000001_MC_FB_START                         0xFFFF0000
535
#define   S_000001_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
536
#define   G_000001_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
537
#define   C_000001_MC_FB_TOP                           0x0000FFFF
538
#define R_000002_MC_AGP_LOCATION                     0x000002
539
#define   S_000002_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
540
#define   G_000002_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
541
#define   C_000002_MC_AGP_START                        0xFFFF0000
542
#define   S_000002_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
543
#define   G_000002_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
544
#define   C_000002_MC_AGP_TOP                          0x0000FFFF
545
#define R_000003_MC_AGP_BASE                         0x000003
546
#define   S_000003_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
547
#define   G_000003_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
548
#define   C_000003_AGP_BASE_ADDR                       0x00000000
549
#define R_000004_MC_AGP_BASE_2                       0x000004
550
#define   S_000004_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
551
#define   G_000004_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
552
#define   C_000004_AGP_BASE_ADDR_2                     0xFFFFFFF0
553
 
554
 
555
#define R_00000F_CP_DYN_CNTL                         0x00000F
556
#define   S_00000F_CP_FORCEON(x)                       (((x) & 0x1) << 0)
557
#define   G_00000F_CP_FORCEON(x)                       (((x) >> 0) & 0x1)
558
#define   C_00000F_CP_FORCEON                          0xFFFFFFFE
559
#define   S_00000F_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 1)
560
#define   G_00000F_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 1) & 0x1)
561
#define   C_00000F_CP_MAX_DYN_STOP_LAT                 0xFFFFFFFD
562
#define   S_00000F_CP_CLOCK_STATUS(x)                  (((x) & 0x1) << 2)
563
#define   G_00000F_CP_CLOCK_STATUS(x)                  (((x) >> 2) & 0x1)
564
#define   C_00000F_CP_CLOCK_STATUS                     0xFFFFFFFB
565
#define   S_00000F_CP_PROG_SHUTOFF(x)                  (((x) & 0x1) << 3)
566
#define   G_00000F_CP_PROG_SHUTOFF(x)                  (((x) >> 3) & 0x1)
567
#define   C_00000F_CP_PROG_SHUTOFF                     0xFFFFFFF7
568
#define   S_00000F_CP_PROG_DELAY_VALUE(x)              (((x) & 0xFF) << 4)
569
#define   G_00000F_CP_PROG_DELAY_VALUE(x)              (((x) >> 4) & 0xFF)
570
#define   C_00000F_CP_PROG_DELAY_VALUE                 0xFFFFF00F
571
#define   S_00000F_CP_LOWER_POWER_IDLE(x)              (((x) & 0xFF) << 12)
572
#define   G_00000F_CP_LOWER_POWER_IDLE(x)              (((x) >> 12) & 0xFF)
573
#define   C_00000F_CP_LOWER_POWER_IDLE                 0xFFF00FFF
574
#define   S_00000F_CP_LOWER_POWER_IGNORE(x)            (((x) & 0x1) << 20)
575
#define   G_00000F_CP_LOWER_POWER_IGNORE(x)            (((x) >> 20) & 0x1)
576
#define   C_00000F_CP_LOWER_POWER_IGNORE               0xFFEFFFFF
577
#define   S_00000F_CP_NORMAL_POWER_IGNORE(x)           (((x) & 0x1) << 21)
578
#define   G_00000F_CP_NORMAL_POWER_IGNORE(x)           (((x) >> 21) & 0x1)
579
#define   C_00000F_CP_NORMAL_POWER_IGNORE              0xFFDFFFFF
580
#define   S_00000F_SPARE(x)                            (((x) & 0x3) << 22)
581
#define   G_00000F_SPARE(x)                            (((x) >> 22) & 0x3)
582
#define   C_00000F_SPARE                               0xFF3FFFFF
583
#define   S_00000F_CP_NORMAL_POWER_BUSY(x)             (((x) & 0xFF) << 24)
584
#define   G_00000F_CP_NORMAL_POWER_BUSY(x)             (((x) >> 24) & 0xFF)
585
#define   C_00000F_CP_NORMAL_POWER_BUSY                0x00FFFFFF
586
#define R_000011_E2_DYN_CNTL                         0x000011
587
#define   S_000011_E2_FORCEON(x)                       (((x) & 0x1) << 0)
588
#define   G_000011_E2_FORCEON(x)                       (((x) >> 0) & 0x1)
589
#define   C_000011_E2_FORCEON                          0xFFFFFFFE
590
#define   S_000011_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 1)
591
#define   G_000011_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 1) & 0x1)
592
#define   C_000011_E2_MAX_DYN_STOP_LAT                 0xFFFFFFFD
593
#define   S_000011_E2_CLOCK_STATUS(x)                  (((x) & 0x1) << 2)
594
#define   G_000011_E2_CLOCK_STATUS(x)                  (((x) >> 2) & 0x1)
595
#define   C_000011_E2_CLOCK_STATUS                     0xFFFFFFFB
596
#define   S_000011_E2_PROG_SHUTOFF(x)                  (((x) & 0x1) << 3)
597
#define   G_000011_E2_PROG_SHUTOFF(x)                  (((x) >> 3) & 0x1)
598
#define   C_000011_E2_PROG_SHUTOFF                     0xFFFFFFF7
599
#define   S_000011_E2_PROG_DELAY_VALUE(x)              (((x) & 0xFF) << 4)
600
#define   G_000011_E2_PROG_DELAY_VALUE(x)              (((x) >> 4) & 0xFF)
601
#define   C_000011_E2_PROG_DELAY_VALUE                 0xFFFFF00F
602
#define   S_000011_E2_LOWER_POWER_IDLE(x)              (((x) & 0xFF) << 12)
603
#define   G_000011_E2_LOWER_POWER_IDLE(x)              (((x) >> 12) & 0xFF)
604
#define   C_000011_E2_LOWER_POWER_IDLE                 0xFFF00FFF
605
#define   S_000011_E2_LOWER_POWER_IGNORE(x)            (((x) & 0x1) << 20)
606
#define   G_000011_E2_LOWER_POWER_IGNORE(x)            (((x) >> 20) & 0x1)
607
#define   C_000011_E2_LOWER_POWER_IGNORE               0xFFEFFFFF
608
#define   S_000011_E2_NORMAL_POWER_IGNORE(x)           (((x) & 0x1) << 21)
609
#define   G_000011_E2_NORMAL_POWER_IGNORE(x)           (((x) >> 21) & 0x1)
610
#define   C_000011_E2_NORMAL_POWER_IGNORE              0xFFDFFFFF
611
#define   S_000011_SPARE(x)                            (((x) & 0x3) << 22)
612
#define   G_000011_SPARE(x)                            (((x) >> 22) & 0x3)
613
#define   C_000011_SPARE                               0xFF3FFFFF
614
#define   S_000011_E2_NORMAL_POWER_BUSY(x)             (((x) & 0xFF) << 24)
615
#define   G_000011_E2_NORMAL_POWER_BUSY(x)             (((x) >> 24) & 0xFF)
616
#define   C_000011_E2_NORMAL_POWER_BUSY                0x00FFFFFF
617
#define R_000013_IDCT_DYN_CNTL                       0x000013
618
#define   S_000013_IDCT_FORCEON(x)                     (((x) & 0x1) << 0)
619
#define   G_000013_IDCT_FORCEON(x)                     (((x) >> 0) & 0x1)
620
#define   C_000013_IDCT_FORCEON                        0xFFFFFFFE
621
#define   S_000013_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 1)
622
#define   G_000013_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 1) & 0x1)
623
#define   C_000013_IDCT_MAX_DYN_STOP_LAT               0xFFFFFFFD
624
#define   S_000013_IDCT_CLOCK_STATUS(x)                (((x) & 0x1) << 2)
625
#define   G_000013_IDCT_CLOCK_STATUS(x)                (((x) >> 2) & 0x1)
626
#define   C_000013_IDCT_CLOCK_STATUS                   0xFFFFFFFB
627
#define   S_000013_IDCT_PROG_SHUTOFF(x)                (((x) & 0x1) << 3)
628
#define   G_000013_IDCT_PROG_SHUTOFF(x)                (((x) >> 3) & 0x1)
629
#define   C_000013_IDCT_PROG_SHUTOFF                   0xFFFFFFF7
630
#define   S_000013_IDCT_PROG_DELAY_VALUE(x)            (((x) & 0xFF) << 4)
631
#define   G_000013_IDCT_PROG_DELAY_VALUE(x)            (((x) >> 4) & 0xFF)
632
#define   C_000013_IDCT_PROG_DELAY_VALUE               0xFFFFF00F
633
#define   S_000013_IDCT_LOWER_POWER_IDLE(x)            (((x) & 0xFF) << 12)
634
#define   G_000013_IDCT_LOWER_POWER_IDLE(x)            (((x) >> 12) & 0xFF)
635
#define   C_000013_IDCT_LOWER_POWER_IDLE               0xFFF00FFF
636
#define   S_000013_IDCT_LOWER_POWER_IGNORE(x)          (((x) & 0x1) << 20)
637
#define   G_000013_IDCT_LOWER_POWER_IGNORE(x)          (((x) >> 20) & 0x1)
638
#define   C_000013_IDCT_LOWER_POWER_IGNORE             0xFFEFFFFF
639
#define   S_000013_IDCT_NORMAL_POWER_IGNORE(x)         (((x) & 0x1) << 21)
640
#define   G_000013_IDCT_NORMAL_POWER_IGNORE(x)         (((x) >> 21) & 0x1)
641
#define   C_000013_IDCT_NORMAL_POWER_IGNORE            0xFFDFFFFF
642
#define   S_000013_SPARE(x)                            (((x) & 0x3) << 22)
643
#define   G_000013_SPARE(x)                            (((x) >> 22) & 0x3)
644
#define   C_000013_SPARE                               0xFF3FFFFF
645
#define   S_000013_IDCT_NORMAL_POWER_BUSY(x)           (((x) & 0xFF) << 24)
646
#define   G_000013_IDCT_NORMAL_POWER_BUSY(x)           (((x) >> 24) & 0xFF)
647
#define   C_000013_IDCT_NORMAL_POWER_BUSY              0x00FFFFFF
648
 
1179 serge 649
#endif