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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1179 | serge | 28 | #include |
| 1986 | serge | 29 | #include |
| 2997 | Serge | 30 | #include |
| 1179 | serge | 31 | #include "rv515d.h" |
| 1117 | serge | 32 | #include "radeon.h" |
| 1963 | serge | 33 | #include "radeon_asic.h" |
| 1221 | serge | 34 | #include "atom.h" |
| 1179 | serge | 35 | #include "rv515_reg_safe.h" |
| 1117 | serge | 36 | |
| 1221 | serge | 37 | /* This files gather functions specifics to: rv515 */ |
| 2997 | Serge | 38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| 39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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| 40 | static void rv515_gpu_init(struct radeon_device *rdev); |
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| 1117 | serge | 41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 42 | |||
| 3192 | Serge | 43 | static const u32 crtc_offsets[2] = |
| 44 | { |
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| 45 | 0, |
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| 46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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| 47 | }; |
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| 48 | |||
| 1221 | serge | 49 | void rv515_debugfs(struct radeon_device *rdev) |
| 1117 | serge | 50 | { |
| 1129 | serge | 51 | if (r100_debugfs_rbbm_init(rdev)) { |
| 52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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| 53 | } |
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| 54 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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| 55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 56 | } |
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| 57 | if (rv515_debugfs_ga_info_init(rdev)) { |
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| 58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 59 | } |
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| 1117 | serge | 60 | } |
| 61 | |||
| 2997 | Serge | 62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
| 1117 | serge | 63 | { |
| 64 | int r; |
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| 65 | |||
| 2997 | Serge | 66 | r = radeon_ring_lock(rdev, ring, 64); |
| 1117 | serge | 67 | if (r) { |
| 68 | return; |
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| 69 | } |
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| 2997 | Serge | 70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
| 71 | radeon_ring_write(ring, |
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| 1179 | serge | 72 | ISYNC_ANY2D_IDLE3D | |
| 73 | ISYNC_ANY3D_IDLE2D | |
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| 74 | ISYNC_WAIT_IDLEGUI | |
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| 75 | ISYNC_CPSCRATCH_IDLEGUI); |
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| 2997 | Serge | 76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
| 77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
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| 79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
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| 80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); |
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| 81 | radeon_ring_write(ring, 0); |
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| 82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); |
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| 83 | radeon_ring_write(ring, 0); |
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| 84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); |
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| 85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); |
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| 86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); |
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| 87 | radeon_ring_write(ring, 0); |
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| 88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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| 92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
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| 93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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| 94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); |
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| 95 | radeon_ring_write(ring, 0); |
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| 96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
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| 97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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| 98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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| 99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
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| 100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); |
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| 101 | radeon_ring_write(ring, |
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| 1179 | serge | 102 | ((6 << MS_X0_SHIFT) | |
| 103 | (6 << MS_Y0_SHIFT) | |
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| 104 | (6 << MS_X1_SHIFT) | |
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| 105 | (6 << MS_Y1_SHIFT) | |
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| 106 | (6 << MS_X2_SHIFT) | |
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| 107 | (6 << MS_Y2_SHIFT) | |
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| 108 | (6 << MSBD0_Y_SHIFT) | |
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| 109 | (6 << MSBD0_X_SHIFT))); |
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| 2997 | Serge | 110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
| 111 | radeon_ring_write(ring, |
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| 1179 | serge | 112 | ((6 << MS_X3_SHIFT) | |
| 113 | (6 << MS_Y3_SHIFT) | |
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| 114 | (6 << MS_X4_SHIFT) | |
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| 115 | (6 << MS_Y4_SHIFT) | |
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| 116 | (6 << MS_X5_SHIFT) | |
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| 117 | (6 << MS_Y5_SHIFT) | |
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| 118 | (6 << MSBD1_SHIFT))); |
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| 2997 | Serge | 119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
| 120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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| 121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); |
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| 122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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| 123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
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| 124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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| 125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
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| 126 | radeon_ring_write(ring, 0); |
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| 5078 | serge | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
| 1117 | serge | 128 | } |
| 129 | |||
| 130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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| 131 | { |
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| 132 | unsigned i; |
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| 133 | uint32_t tmp; |
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| 134 | |||
| 135 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 136 | /* read MC_STATUS */ |
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| 1179 | serge | 137 | tmp = RREG32_MC(MC_STATUS); |
| 138 | if (tmp & MC_STATUS_IDLE) { |
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| 1117 | serge | 139 | return 0; |
| 140 | } |
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| 141 | DRM_UDELAY(1); |
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| 142 | } |
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| 143 | return -1; |
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| 144 | } |
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| 145 | |||
| 1221 | serge | 146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
| 147 | { |
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| 148 | WREG32(R_000300_VGA_RENDER_CONTROL, |
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| 149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
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| 150 | } |
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| 151 | |||
| 2997 | Serge | 152 | static void rv515_gpu_init(struct radeon_device *rdev) |
| 1117 | serge | 153 | { |
| 154 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 155 | |||
| 156 | if (r100_gui_wait_for_idle(rdev)) { |
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| 157 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 2997 | Serge | 158 | "resetting GPU. Bad things might happen.\n"); |
| 1117 | serge | 159 | } |
| 1221 | serge | 160 | rv515_vga_render_disable(rdev); |
| 1117 | serge | 161 | r420_pipes_init(rdev); |
| 1963 | serge | 162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
| 163 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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| 1117 | serge | 164 | pipe_select_current = (tmp >> 2) & 3; |
| 165 | tmp = (1 << pipe_select_current) | |
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| 166 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 167 | WREG32_PLL(0x000D, tmp); |
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| 168 | if (r100_gui_wait_for_idle(rdev)) { |
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| 169 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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| 2997 | Serge | 170 | "resetting GPU. Bad things might happen.\n"); |
| 1117 | serge | 171 | } |
| 172 | if (rv515_mc_wait_for_idle(rdev)) { |
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| 173 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 174 | "programming pipes. Bad things might happen.\n"); |
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| 175 | } |
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| 176 | } |
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| 177 | |||
| 178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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| 179 | { |
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| 180 | uint32_t tmp; |
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| 181 | |||
| 182 | rdev->mc.vram_width = 128; |
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| 183 | rdev->mc.vram_is_ddr = true; |
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| 1179 | serge | 184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
| 1117 | serge | 185 | switch (tmp) { |
| 186 | case 0: |
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| 187 | rdev->mc.vram_width = 64; |
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| 188 | break; |
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| 189 | case 1: |
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| 190 | rdev->mc.vram_width = 128; |
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| 191 | break; |
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| 192 | default: |
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| 193 | rdev->mc.vram_width = 128; |
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| 194 | break; |
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| 195 | } |
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| 196 | } |
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| 197 | |||
| 2997 | Serge | 198 | static void rv515_mc_init(struct radeon_device *rdev) |
| 1117 | serge | 199 | { |
| 1179 | serge | 200 | |
| 1117 | serge | 201 | rv515_vram_get_type(rdev); |
| 1179 | serge | 202 | r100_vram_init_sizes(rdev); |
| 1430 | serge | 203 | radeon_vram_location(rdev, &rdev->mc, 0); |
| 1963 | serge | 204 | rdev->mc.gtt_base_align = 0; |
| 1430 | serge | 205 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 206 | radeon_gtt_location(rdev, &rdev->mc); |
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| 1963 | serge | 207 | radeon_update_bandwidth_info(rdev); |
| 1117 | serge | 208 | } |
| 209 | |||
| 210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 211 | { |
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| 5078 | serge | 212 | unsigned long flags; |
| 1117 | serge | 213 | uint32_t r; |
| 214 | |||
| 5078 | serge | 215 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
| 1179 | serge | 216 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
| 217 | r = RREG32(MC_IND_DATA); |
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| 218 | WREG32(MC_IND_INDEX, 0); |
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| 5078 | serge | 219 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| 220 | |||
| 1117 | serge | 221 | return r; |
| 222 | } |
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| 223 | |||
| 224 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 225 | { |
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| 5078 | serge | 226 | unsigned long flags; |
| 227 | |||
| 228 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
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| 1179 | serge | 229 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
| 230 | WREG32(MC_IND_DATA, (v)); |
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| 231 | WREG32(MC_IND_INDEX, 0); |
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| 5078 | serge | 232 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| 1117 | serge | 233 | } |
| 234 | |||
| 235 | #if defined(CONFIG_DEBUG_FS) |
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| 236 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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| 237 | { |
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| 238 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 239 | struct drm_device *dev = node->minor->dev; |
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| 240 | struct radeon_device *rdev = dev->dev_private; |
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| 241 | uint32_t tmp; |
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| 242 | |||
| 1179 | serge | 243 | tmp = RREG32(GB_PIPE_SELECT); |
| 1117 | serge | 244 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
| 1179 | serge | 245 | tmp = RREG32(SU_REG_DEST); |
| 1117 | serge | 246 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
| 1179 | serge | 247 | tmp = RREG32(GB_TILE_CONFIG); |
| 1117 | serge | 248 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
| 1179 | serge | 249 | tmp = RREG32(DST_PIPE_CONFIG); |
| 1117 | serge | 250 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
| 251 | return 0; |
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| 252 | } |
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| 253 | |||
| 254 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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| 255 | { |
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| 256 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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| 257 | struct drm_device *dev = node->minor->dev; |
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| 258 | struct radeon_device *rdev = dev->dev_private; |
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| 259 | uint32_t tmp; |
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| 260 | |||
| 261 | tmp = RREG32(0x2140); |
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| 262 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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| 1963 | serge | 263 | radeon_asic_reset(rdev); |
| 1117 | serge | 264 | tmp = RREG32(0x425C); |
| 265 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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| 266 | return 0; |
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| 267 | } |
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| 268 | |||
| 269 | static struct drm_info_list rv515_pipes_info_list[] = { |
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| 270 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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| 271 | }; |
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| 272 | |||
| 273 | static struct drm_info_list rv515_ga_info_list[] = { |
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| 274 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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| 275 | }; |
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| 276 | #endif |
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| 277 | |||
| 2997 | Serge | 278 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
| 1117 | serge | 279 | { |
| 280 | #if defined(CONFIG_DEBUG_FS) |
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| 281 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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| 282 | #else |
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| 283 | return 0; |
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| 284 | #endif |
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| 285 | } |
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| 286 | |||
| 2997 | Serge | 287 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
| 1117 | serge | 288 | { |
| 289 | #if defined(CONFIG_DEBUG_FS) |
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| 290 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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| 291 | #else |
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| 292 | return 0; |
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| 293 | #endif |
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| 294 | } |
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| 295 | |||
| 1221 | serge | 296 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
| 1179 | serge | 297 | { |
| 3192 | Serge | 298 | u32 crtc_enabled, tmp, frame_count, blackout; |
| 299 | int i, j; |
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| 300 | |||
| 1221 | serge | 301 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
| 302 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
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| 1179 | serge | 303 | |
| 3192 | Serge | 304 | /* disable VGA render */ |
| 1221 | serge | 305 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
| 3192 | Serge | 306 | /* blank the display controllers */ |
| 307 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 308 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; |
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| 309 | if (crtc_enabled) { |
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| 310 | save->crtc_enabled[i] = true; |
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| 311 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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| 312 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
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| 313 | radeon_wait_for_vblank(rdev, i); |
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| 3764 | Serge | 314 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| 3192 | Serge | 315 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
| 316 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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| 3764 | Serge | 317 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| 3192 | Serge | 318 | } |
| 319 | /* wait for the next frame */ |
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| 320 | frame_count = radeon_get_vblank_counter(rdev, i); |
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| 321 | for (j = 0; j < rdev->usec_timeout; j++) { |
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| 322 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
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| 323 | break; |
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| 324 | udelay(1); |
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| 325 | } |
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| 3764 | Serge | 326 | |
| 327 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
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| 328 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
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| 329 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
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| 330 | tmp &= ~AVIVO_CRTC_EN; |
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| 331 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
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| 332 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
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| 333 | save->crtc_enabled[i] = false; |
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| 334 | /* ***** */ |
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| 3192 | Serge | 335 | } else { |
| 336 | save->crtc_enabled[i] = false; |
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| 337 | } |
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| 338 | } |
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| 339 | |||
| 340 | radeon_mc_wait_for_idle(rdev); |
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| 341 | |||
| 342 | if (rdev->family >= CHIP_R600) { |
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| 343 | if (rdev->family >= CHIP_RV770) |
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| 344 | blackout = RREG32(R700_MC_CITF_CNTL); |
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| 345 | else |
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| 346 | blackout = RREG32(R600_CITF_CNTL); |
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| 347 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { |
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| 348 | /* Block CPU access */ |
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| 349 | WREG32(R600_BIF_FB_EN, 0); |
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| 350 | /* blackout the MC */ |
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| 351 | blackout |= R600_BLACKOUT_MASK; |
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| 352 | if (rdev->family >= CHIP_RV770) |
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| 353 | WREG32(R700_MC_CITF_CNTL, blackout); |
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| 354 | else |
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| 355 | WREG32(R600_CITF_CNTL, blackout); |
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| 356 | } |
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| 357 | } |
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| 3764 | Serge | 358 | /* wait for the MC to settle */ |
| 359 | udelay(100); |
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| 360 | |||
| 361 | /* lock double buffered regs */ |
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| 362 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 363 | if (save->crtc_enabled[i]) { |
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| 364 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
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| 365 | if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { |
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| 366 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
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| 367 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
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| 368 | } |
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| 369 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
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| 370 | if (!(tmp & 1)) { |
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| 371 | tmp |= 1; |
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| 372 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
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| 373 | } |
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| 374 | } |
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| 375 | } |
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| 1221 | serge | 376 | } |
| 377 | |||
| 378 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
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| 379 | { |
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| 3192 | Serge | 380 | u32 tmp, frame_count; |
| 381 | int i, j; |
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| 382 | |||
| 383 | /* update crtc base addresses */ |
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| 384 | for (i = 0; i < rdev->num_crtc; i++) { |
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| 385 | if (rdev->family >= CHIP_RV770) { |
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| 3764 | Serge | 386 | if (i == 0) { |
| 3192 | Serge | 387 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
| 388 | upper_32_bits(rdev->mc.vram_start)); |
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| 389 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
||
| 390 | upper_32_bits(rdev->mc.vram_start)); |
||
| 391 | } else { |
||
| 392 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
||
| 393 | upper_32_bits(rdev->mc.vram_start)); |
||
| 394 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
||
| 395 | upper_32_bits(rdev->mc.vram_start)); |
||
| 396 | } |
||
| 397 | } |
||
| 398 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
||
| 399 | (u32)rdev->mc.vram_start); |
||
| 400 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
||
| 401 | (u32)rdev->mc.vram_start); |
||
| 402 | } |
||
| 403 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
||
| 404 | |||
| 3764 | Serge | 405 | /* unlock regs and wait for update */ |
| 406 | for (i = 0; i < rdev->num_crtc; i++) { |
||
| 407 | if (save->crtc_enabled[i]) { |
||
| 408 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
||
| 5078 | serge | 409 | if ((tmp & 0x7) != 3) { |
| 410 | tmp &= ~0x7; |
||
| 411 | tmp |= 0x3; |
||
| 3764 | Serge | 412 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
| 413 | } |
||
| 414 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
||
| 415 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
||
| 416 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
||
| 417 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
||
| 418 | } |
||
| 419 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
||
| 420 | if (tmp & 1) { |
||
| 421 | tmp &= ~1; |
||
| 422 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
||
| 423 | } |
||
| 424 | for (j = 0; j < rdev->usec_timeout; j++) { |
||
| 425 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
||
| 426 | if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) |
||
| 427 | break; |
||
| 428 | udelay(1); |
||
| 429 | } |
||
| 430 | } |
||
| 431 | } |
||
| 432 | |||
| 3192 | Serge | 433 | if (rdev->family >= CHIP_R600) { |
| 434 | /* unblackout the MC */ |
||
| 435 | if (rdev->family >= CHIP_RV770) |
||
| 436 | tmp = RREG32(R700_MC_CITF_CNTL); |
||
| 437 | else |
||
| 438 | tmp = RREG32(R600_CITF_CNTL); |
||
| 439 | tmp &= ~R600_BLACKOUT_MASK; |
||
| 440 | if (rdev->family >= CHIP_RV770) |
||
| 441 | WREG32(R700_MC_CITF_CNTL, tmp); |
||
| 442 | else |
||
| 443 | WREG32(R600_CITF_CNTL, tmp); |
||
| 444 | /* allow CPU access */ |
||
| 445 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); |
||
| 446 | } |
||
| 447 | |||
| 448 | for (i = 0; i < rdev->num_crtc; i++) { |
||
| 449 | if (save->crtc_enabled[i]) { |
||
| 450 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
||
| 451 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
||
| 452 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
||
| 453 | /* wait for the next frame */ |
||
| 454 | frame_count = radeon_get_vblank_counter(rdev, i); |
||
| 455 | for (j = 0; j < rdev->usec_timeout; j++) { |
||
| 456 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
||
| 457 | break; |
||
| 458 | udelay(1); |
||
| 459 | } |
||
| 460 | } |
||
| 461 | } |
||
| 462 | /* Unlock vga access */ |
||
| 1221 | serge | 463 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
| 464 | mdelay(1); |
||
| 465 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
||
| 466 | } |
||
| 467 | |||
| 2997 | Serge | 468 | static void rv515_mc_program(struct radeon_device *rdev) |
| 1221 | serge | 469 | { |
| 470 | struct rv515_mc_save save; |
||
| 471 | |||
| 472 | /* Stops all mc clients */ |
||
| 473 | rv515_mc_stop(rdev, &save); |
||
| 474 | |||
| 475 | /* Wait for mc idle */ |
||
| 476 | if (rv515_mc_wait_for_idle(rdev)) |
||
| 477 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
| 478 | /* Write VRAM size in case we are limiting it */ |
||
| 479 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
| 480 | /* Program MC, should be a 32bits limited address space */ |
||
| 481 | WREG32_MC(R_000001_MC_FB_LOCATION, |
||
| 482 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
| 483 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
| 484 | WREG32(R_000134_HDP_FB_LOCATION, |
||
| 485 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
| 486 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 487 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
||
| 488 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
| 489 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
| 490 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
| 491 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
||
| 492 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
||
| 493 | } else { |
||
| 494 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
||
| 495 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
||
| 496 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
||
| 497 | } |
||
| 498 | |||
| 499 | rv515_mc_resume(rdev, &save); |
||
| 500 | } |
||
| 501 | |||
| 502 | void rv515_clock_startup(struct radeon_device *rdev) |
||
| 503 | { |
||
| 504 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
| 505 | radeon_atom_set_clock_gating(rdev, 1); |
||
| 506 | /* We need to force on some of the block */ |
||
| 507 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
||
| 508 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
||
| 509 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
||
| 510 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
||
| 511 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
||
| 512 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
||
| 513 | } |
||
| 514 | |||
| 515 | static int rv515_startup(struct radeon_device *rdev) |
||
| 516 | { |
||
| 517 | int r; |
||
| 518 | |||
| 519 | rv515_mc_program(rdev); |
||
| 520 | /* Resume clock */ |
||
| 521 | rv515_clock_startup(rdev); |
||
| 522 | /* Initialize GPU configuration (# pipes, ...) */ |
||
| 523 | rv515_gpu_init(rdev); |
||
| 524 | /* Initialize GART (initialize after TTM so we can allocate |
||
| 525 | * memory through TTM but finalize after TTM) */ |
||
| 526 | if (rdev->flags & RADEON_IS_PCIE) { |
||
| 527 | r = rv370_pcie_gart_enable(rdev); |
||
| 528 | if (r) |
||
| 529 | return r; |
||
| 530 | } |
||
| 2005 | serge | 531 | |
| 532 | /* allocate wb buffer */ |
||
| 533 | r = radeon_wb_init(rdev); |
||
| 534 | if (r) |
||
| 535 | return r; |
||
| 536 | |||
| 3120 | serge | 537 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 538 | if (r) { |
||
| 539 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
| 540 | return r; |
||
| 541 | } |
||
| 542 | |||
| 1221 | serge | 543 | /* Enable IRQ */ |
| 3764 | Serge | 544 | if (!rdev->irq.installed) { |
| 545 | r = radeon_irq_kms_init(rdev); |
||
| 546 | if (r) |
||
| 547 | return r; |
||
| 548 | } |
||
| 549 | |||
| 2005 | serge | 550 | rs600_irq_set(rdev); |
| 1403 | serge | 551 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| 1221 | serge | 552 | /* 1M ring buffer */ |
| 1413 | serge | 553 | r = r100_cp_init(rdev, 1024 * 1024); |
| 554 | if (r) { |
||
| 1963 | serge | 555 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| 1413 | serge | 556 | return r; |
| 557 | } |
||
| 2997 | Serge | 558 | |
| 559 | r = radeon_ib_pool_init(rdev); |
||
| 2005 | serge | 560 | if (r) { |
| 2997 | Serge | 561 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 2005 | serge | 562 | return r; |
| 563 | } |
||
| 2997 | Serge | 564 | |
| 1221 | serge | 565 | return 0; |
| 566 | } |
||
| 567 | |||
| 568 | |||
| 569 | void rv515_set_safe_registers(struct radeon_device *rdev) |
||
| 570 | { |
||
| 1179 | serge | 571 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
| 572 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
| 1221 | serge | 573 | } |
| 574 | |||
| 6104 | serge | 575 | void rv515_fini(struct radeon_device *rdev) |
| 576 | { |
||
| 577 | radeon_pm_fini(rdev); |
||
| 578 | r100_cp_fini(rdev); |
||
| 579 | radeon_wb_fini(rdev); |
||
| 580 | radeon_ib_pool_fini(rdev); |
||
| 581 | radeon_gem_fini(rdev); |
||
| 582 | rv370_pcie_gart_fini(rdev); |
||
| 583 | radeon_agp_fini(rdev); |
||
| 584 | radeon_irq_kms_fini(rdev); |
||
| 585 | radeon_fence_driver_fini(rdev); |
||
| 586 | radeon_bo_fini(rdev); |
||
| 587 | radeon_atombios_fini(rdev); |
||
| 588 | kfree(rdev->bios); |
||
| 589 | rdev->bios = NULL; |
||
| 590 | } |
||
| 591 | |||
| 1221 | serge | 592 | int rv515_init(struct radeon_device *rdev) |
| 593 | { |
||
| 594 | int r; |
||
| 595 | |||
| 596 | /* Initialize scratch registers */ |
||
| 597 | radeon_scratch_init(rdev); |
||
| 598 | /* Initialize surface registers */ |
||
| 599 | radeon_surface_init(rdev); |
||
| 600 | /* TODO: disable VGA need to use VGA request */ |
||
| 1963 | serge | 601 | /* restore some register to sane defaults */ |
| 602 | r100_restore_sanity(rdev); |
||
| 1221 | serge | 603 | /* BIOS*/ |
| 604 | if (!radeon_get_bios(rdev)) { |
||
| 605 | if (ASIC_IS_AVIVO(rdev)) |
||
| 606 | return -EINVAL; |
||
| 607 | } |
||
| 608 | if (rdev->is_atom_bios) { |
||
| 609 | r = radeon_atombios_init(rdev); |
||
| 610 | if (r) |
||
| 611 | return r; |
||
| 612 | } else { |
||
| 613 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
| 614 | return -EINVAL; |
||
| 615 | } |
||
| 616 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
| 1963 | serge | 617 | if (radeon_asic_reset(rdev)) { |
| 1221 | serge | 618 | dev_warn(rdev->dev, |
| 619 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
| 620 | RREG32(R_000E40_RBBM_STATUS), |
||
| 621 | RREG32(R_0007C0_CP_STAT)); |
||
| 622 | } |
||
| 623 | /* check if cards are posted or not */ |
||
| 1403 | serge | 624 | if (radeon_boot_test_post_card(rdev) == false) |
| 625 | return -EINVAL; |
||
| 1221 | serge | 626 | /* Initialize clocks */ |
| 627 | radeon_get_clock_info(rdev->ddev); |
||
| 1430 | serge | 628 | /* initialize AGP */ |
| 629 | if (rdev->flags & RADEON_IS_AGP) { |
||
| 630 | r = radeon_agp_init(rdev); |
||
| 631 | if (r) { |
||
| 632 | radeon_agp_disable(rdev); |
||
| 633 | } |
||
| 634 | } |
||
| 635 | /* initialize memory controller */ |
||
| 636 | rv515_mc_init(rdev); |
||
| 1221 | serge | 637 | rv515_debugfs(rdev); |
| 638 | /* Fence driver */ |
||
| 2005 | serge | 639 | r = radeon_fence_driver_init(rdev); |
| 640 | if (r) |
||
| 641 | return r; |
||
| 1221 | serge | 642 | /* Memory manager */ |
| 1403 | serge | 643 | r = radeon_bo_init(rdev); |
| 1221 | serge | 644 | if (r) |
| 645 | return r; |
||
| 646 | r = rv370_pcie_gart_init(rdev); |
||
| 647 | if (r) |
||
| 648 | return r; |
||
| 649 | rv515_set_safe_registers(rdev); |
||
| 2997 | Serge | 650 | |
| 5078 | serge | 651 | /* Initialize power management */ |
| 652 | radeon_pm_init(rdev); |
||
| 653 | |||
| 1221 | serge | 654 | rdev->accel_working = true; |
| 655 | r = rv515_startup(rdev); |
||
| 656 | if (r) { |
||
| 657 | /* Somethings want wront with the accel init stop accel */ |
||
| 658 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
| 6104 | serge | 659 | r100_cp_fini(rdev); |
| 660 | radeon_wb_fini(rdev); |
||
| 661 | radeon_ib_pool_fini(rdev); |
||
| 662 | radeon_irq_kms_fini(rdev); |
||
| 663 | rv370_pcie_gart_fini(rdev); |
||
| 664 | radeon_agp_fini(rdev); |
||
| 1221 | serge | 665 | rdev->accel_working = false; |
| 666 | } |
||
| 1179 | serge | 667 | return 0; |
| 668 | } |
||
| 669 | |||
| 670 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
| 671 | { |
||
| 672 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
| 673 | int data_reg = 0x657c + crtc->crtc_offset; |
||
| 674 | |||
| 675 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
| 676 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
| 677 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
| 678 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
| 679 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
| 680 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
| 681 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
| 682 | WREG32(index_reg, 0x0); |
||
| 683 | WREG32(data_reg, 0x841880A8); |
||
| 684 | WREG32(index_reg, 0x1); |
||
| 685 | WREG32(data_reg, 0x84208680); |
||
| 686 | WREG32(index_reg, 0x2); |
||
| 687 | WREG32(data_reg, 0xBFF880B0); |
||
| 688 | WREG32(index_reg, 0x100); |
||
| 689 | WREG32(data_reg, 0x83D88088); |
||
| 690 | WREG32(index_reg, 0x101); |
||
| 691 | WREG32(data_reg, 0x84608680); |
||
| 692 | WREG32(index_reg, 0x102); |
||
| 693 | WREG32(data_reg, 0xBFF080D0); |
||
| 694 | WREG32(index_reg, 0x200); |
||
| 695 | WREG32(data_reg, 0x83988068); |
||
| 696 | WREG32(index_reg, 0x201); |
||
| 697 | WREG32(data_reg, 0x84A08680); |
||
| 698 | WREG32(index_reg, 0x202); |
||
| 699 | WREG32(data_reg, 0xBFF080F8); |
||
| 700 | WREG32(index_reg, 0x300); |
||
| 701 | WREG32(data_reg, 0x83588058); |
||
| 702 | WREG32(index_reg, 0x301); |
||
| 703 | WREG32(data_reg, 0x84E08660); |
||
| 704 | WREG32(index_reg, 0x302); |
||
| 705 | WREG32(data_reg, 0xBFF88120); |
||
| 706 | WREG32(index_reg, 0x400); |
||
| 707 | WREG32(data_reg, 0x83188040); |
||
| 708 | WREG32(index_reg, 0x401); |
||
| 709 | WREG32(data_reg, 0x85008660); |
||
| 710 | WREG32(index_reg, 0x402); |
||
| 711 | WREG32(data_reg, 0xBFF88150); |
||
| 712 | WREG32(index_reg, 0x500); |
||
| 713 | WREG32(data_reg, 0x82D88030); |
||
| 714 | WREG32(index_reg, 0x501); |
||
| 715 | WREG32(data_reg, 0x85408640); |
||
| 716 | WREG32(index_reg, 0x502); |
||
| 717 | WREG32(data_reg, 0xBFF88180); |
||
| 718 | WREG32(index_reg, 0x600); |
||
| 719 | WREG32(data_reg, 0x82A08018); |
||
| 720 | WREG32(index_reg, 0x601); |
||
| 721 | WREG32(data_reg, 0x85808620); |
||
| 722 | WREG32(index_reg, 0x602); |
||
| 723 | WREG32(data_reg, 0xBFF081B8); |
||
| 724 | WREG32(index_reg, 0x700); |
||
| 725 | WREG32(data_reg, 0x82608010); |
||
| 726 | WREG32(index_reg, 0x701); |
||
| 727 | WREG32(data_reg, 0x85A08600); |
||
| 728 | WREG32(index_reg, 0x702); |
||
| 729 | WREG32(data_reg, 0x800081F0); |
||
| 730 | WREG32(index_reg, 0x800); |
||
| 731 | WREG32(data_reg, 0x8228BFF8); |
||
| 732 | WREG32(index_reg, 0x801); |
||
| 733 | WREG32(data_reg, 0x85E085E0); |
||
| 734 | WREG32(index_reg, 0x802); |
||
| 735 | WREG32(data_reg, 0xBFF88228); |
||
| 736 | WREG32(index_reg, 0x10000); |
||
| 737 | WREG32(data_reg, 0x82A8BF00); |
||
| 738 | WREG32(index_reg, 0x10001); |
||
| 739 | WREG32(data_reg, 0x82A08CC0); |
||
| 740 | WREG32(index_reg, 0x10002); |
||
| 741 | WREG32(data_reg, 0x8008BEF8); |
||
| 742 | WREG32(index_reg, 0x10100); |
||
| 743 | WREG32(data_reg, 0x81F0BF28); |
||
| 744 | WREG32(index_reg, 0x10101); |
||
| 745 | WREG32(data_reg, 0x83608CA0); |
||
| 746 | WREG32(index_reg, 0x10102); |
||
| 747 | WREG32(data_reg, 0x8018BED0); |
||
| 748 | WREG32(index_reg, 0x10200); |
||
| 749 | WREG32(data_reg, 0x8148BF38); |
||
| 750 | WREG32(index_reg, 0x10201); |
||
| 751 | WREG32(data_reg, 0x84408C80); |
||
| 752 | WREG32(index_reg, 0x10202); |
||
| 753 | WREG32(data_reg, 0x8008BEB8); |
||
| 754 | WREG32(index_reg, 0x10300); |
||
| 755 | WREG32(data_reg, 0x80B0BF78); |
||
| 756 | WREG32(index_reg, 0x10301); |
||
| 757 | WREG32(data_reg, 0x85008C20); |
||
| 758 | WREG32(index_reg, 0x10302); |
||
| 759 | WREG32(data_reg, 0x8020BEA0); |
||
| 760 | WREG32(index_reg, 0x10400); |
||
| 761 | WREG32(data_reg, 0x8028BF90); |
||
| 762 | WREG32(index_reg, 0x10401); |
||
| 763 | WREG32(data_reg, 0x85E08BC0); |
||
| 764 | WREG32(index_reg, 0x10402); |
||
| 765 | WREG32(data_reg, 0x8018BE90); |
||
| 766 | WREG32(index_reg, 0x10500); |
||
| 767 | WREG32(data_reg, 0xBFB8BFB0); |
||
| 768 | WREG32(index_reg, 0x10501); |
||
| 769 | WREG32(data_reg, 0x86C08B40); |
||
| 770 | WREG32(index_reg, 0x10502); |
||
| 771 | WREG32(data_reg, 0x8010BE90); |
||
| 772 | WREG32(index_reg, 0x10600); |
||
| 773 | WREG32(data_reg, 0xBF58BFC8); |
||
| 774 | WREG32(index_reg, 0x10601); |
||
| 775 | WREG32(data_reg, 0x87A08AA0); |
||
| 776 | WREG32(index_reg, 0x10602); |
||
| 777 | WREG32(data_reg, 0x8010BE98); |
||
| 778 | WREG32(index_reg, 0x10700); |
||
| 779 | WREG32(data_reg, 0xBF10BFF0); |
||
| 780 | WREG32(index_reg, 0x10701); |
||
| 781 | WREG32(data_reg, 0x886089E0); |
||
| 782 | WREG32(index_reg, 0x10702); |
||
| 783 | WREG32(data_reg, 0x8018BEB0); |
||
| 784 | WREG32(index_reg, 0x10800); |
||
| 785 | WREG32(data_reg, 0xBED8BFE8); |
||
| 786 | WREG32(index_reg, 0x10801); |
||
| 787 | WREG32(data_reg, 0x89408940); |
||
| 788 | WREG32(index_reg, 0x10802); |
||
| 789 | WREG32(data_reg, 0xBFE8BED8); |
||
| 790 | WREG32(index_reg, 0x20000); |
||
| 791 | WREG32(data_reg, 0x80008000); |
||
| 792 | WREG32(index_reg, 0x20001); |
||
| 793 | WREG32(data_reg, 0x90008000); |
||
| 794 | WREG32(index_reg, 0x20002); |
||
| 795 | WREG32(data_reg, 0x80008000); |
||
| 796 | WREG32(index_reg, 0x20003); |
||
| 797 | WREG32(data_reg, 0x80008000); |
||
| 798 | WREG32(index_reg, 0x20100); |
||
| 799 | WREG32(data_reg, 0x80108000); |
||
| 800 | WREG32(index_reg, 0x20101); |
||
| 801 | WREG32(data_reg, 0x8FE0BF70); |
||
| 802 | WREG32(index_reg, 0x20102); |
||
| 803 | WREG32(data_reg, 0xBFE880C0); |
||
| 804 | WREG32(index_reg, 0x20103); |
||
| 805 | WREG32(data_reg, 0x80008000); |
||
| 806 | WREG32(index_reg, 0x20200); |
||
| 807 | WREG32(data_reg, 0x8018BFF8); |
||
| 808 | WREG32(index_reg, 0x20201); |
||
| 809 | WREG32(data_reg, 0x8F80BF08); |
||
| 810 | WREG32(index_reg, 0x20202); |
||
| 811 | WREG32(data_reg, 0xBFD081A0); |
||
| 812 | WREG32(index_reg, 0x20203); |
||
| 813 | WREG32(data_reg, 0xBFF88000); |
||
| 814 | WREG32(index_reg, 0x20300); |
||
| 815 | WREG32(data_reg, 0x80188000); |
||
| 816 | WREG32(index_reg, 0x20301); |
||
| 817 | WREG32(data_reg, 0x8EE0BEC0); |
||
| 818 | WREG32(index_reg, 0x20302); |
||
| 819 | WREG32(data_reg, 0xBFB082A0); |
||
| 820 | WREG32(index_reg, 0x20303); |
||
| 821 | WREG32(data_reg, 0x80008000); |
||
| 822 | WREG32(index_reg, 0x20400); |
||
| 823 | WREG32(data_reg, 0x80188000); |
||
| 824 | WREG32(index_reg, 0x20401); |
||
| 825 | WREG32(data_reg, 0x8E00BEA0); |
||
| 826 | WREG32(index_reg, 0x20402); |
||
| 827 | WREG32(data_reg, 0xBF8883C0); |
||
| 828 | WREG32(index_reg, 0x20403); |
||
| 829 | WREG32(data_reg, 0x80008000); |
||
| 830 | WREG32(index_reg, 0x20500); |
||
| 831 | WREG32(data_reg, 0x80188000); |
||
| 832 | WREG32(index_reg, 0x20501); |
||
| 833 | WREG32(data_reg, 0x8D00BE90); |
||
| 834 | WREG32(index_reg, 0x20502); |
||
| 835 | WREG32(data_reg, 0xBF588500); |
||
| 836 | WREG32(index_reg, 0x20503); |
||
| 837 | WREG32(data_reg, 0x80008008); |
||
| 838 | WREG32(index_reg, 0x20600); |
||
| 839 | WREG32(data_reg, 0x80188000); |
||
| 840 | WREG32(index_reg, 0x20601); |
||
| 841 | WREG32(data_reg, 0x8BC0BE98); |
||
| 842 | WREG32(index_reg, 0x20602); |
||
| 843 | WREG32(data_reg, 0xBF308660); |
||
| 844 | WREG32(index_reg, 0x20603); |
||
| 845 | WREG32(data_reg, 0x80008008); |
||
| 846 | WREG32(index_reg, 0x20700); |
||
| 847 | WREG32(data_reg, 0x80108000); |
||
| 848 | WREG32(index_reg, 0x20701); |
||
| 849 | WREG32(data_reg, 0x8A80BEB0); |
||
| 850 | WREG32(index_reg, 0x20702); |
||
| 851 | WREG32(data_reg, 0xBF0087C0); |
||
| 852 | WREG32(index_reg, 0x20703); |
||
| 853 | WREG32(data_reg, 0x80008008); |
||
| 854 | WREG32(index_reg, 0x20800); |
||
| 855 | WREG32(data_reg, 0x80108000); |
||
| 856 | WREG32(index_reg, 0x20801); |
||
| 857 | WREG32(data_reg, 0x8920BED0); |
||
| 858 | WREG32(index_reg, 0x20802); |
||
| 859 | WREG32(data_reg, 0xBED08920); |
||
| 860 | WREG32(index_reg, 0x20803); |
||
| 861 | WREG32(data_reg, 0x80008010); |
||
| 862 | WREG32(index_reg, 0x30000); |
||
| 863 | WREG32(data_reg, 0x90008000); |
||
| 864 | WREG32(index_reg, 0x30001); |
||
| 865 | WREG32(data_reg, 0x80008000); |
||
| 866 | WREG32(index_reg, 0x30100); |
||
| 867 | WREG32(data_reg, 0x8FE0BF90); |
||
| 868 | WREG32(index_reg, 0x30101); |
||
| 869 | WREG32(data_reg, 0xBFF880A0); |
||
| 870 | WREG32(index_reg, 0x30200); |
||
| 871 | WREG32(data_reg, 0x8F60BF40); |
||
| 872 | WREG32(index_reg, 0x30201); |
||
| 873 | WREG32(data_reg, 0xBFE88180); |
||
| 874 | WREG32(index_reg, 0x30300); |
||
| 875 | WREG32(data_reg, 0x8EC0BF00); |
||
| 876 | WREG32(index_reg, 0x30301); |
||
| 877 | WREG32(data_reg, 0xBFC88280); |
||
| 878 | WREG32(index_reg, 0x30400); |
||
| 879 | WREG32(data_reg, 0x8DE0BEE0); |
||
| 880 | WREG32(index_reg, 0x30401); |
||
| 881 | WREG32(data_reg, 0xBFA083A0); |
||
| 882 | WREG32(index_reg, 0x30500); |
||
| 883 | WREG32(data_reg, 0x8CE0BED0); |
||
| 884 | WREG32(index_reg, 0x30501); |
||
| 885 | WREG32(data_reg, 0xBF7884E0); |
||
| 886 | WREG32(index_reg, 0x30600); |
||
| 887 | WREG32(data_reg, 0x8BA0BED8); |
||
| 888 | WREG32(index_reg, 0x30601); |
||
| 889 | WREG32(data_reg, 0xBF508640); |
||
| 890 | WREG32(index_reg, 0x30700); |
||
| 891 | WREG32(data_reg, 0x8A60BEE8); |
||
| 892 | WREG32(index_reg, 0x30701); |
||
| 893 | WREG32(data_reg, 0xBF2087A0); |
||
| 894 | WREG32(index_reg, 0x30800); |
||
| 895 | WREG32(data_reg, 0x8900BF00); |
||
| 896 | WREG32(index_reg, 0x30801); |
||
| 897 | WREG32(data_reg, 0xBF008900); |
||
| 898 | } |
||
| 899 | |||
| 900 | struct rv515_watermark { |
||
| 901 | u32 lb_request_fifo_depth; |
||
| 902 | fixed20_12 num_line_pair; |
||
| 903 | fixed20_12 estimated_width; |
||
| 904 | fixed20_12 worst_case_latency; |
||
| 905 | fixed20_12 consumption_rate; |
||
| 906 | fixed20_12 active_time; |
||
| 907 | fixed20_12 dbpp; |
||
| 908 | fixed20_12 priority_mark_max; |
||
| 909 | fixed20_12 priority_mark; |
||
| 910 | fixed20_12 sclk; |
||
| 1117 | serge | 911 | }; |
| 912 | |||
| 2997 | Serge | 913 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
| 6104 | serge | 914 | struct radeon_crtc *crtc, |
| 5078 | serge | 915 | struct rv515_watermark *wm, |
| 916 | bool low) |
||
| 1179 | serge | 917 | { |
| 918 | struct drm_display_mode *mode = &crtc->base.mode; |
||
| 919 | fixed20_12 a, b, c; |
||
| 920 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
| 921 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
| 5078 | serge | 922 | fixed20_12 sclk; |
| 923 | u32 selected_sclk; |
||
| 1117 | serge | 924 | |
| 1179 | serge | 925 | if (!crtc->base.enabled) { |
| 926 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
| 927 | wm->lb_request_fifo_depth = 4; |
||
| 928 | return; |
||
| 929 | } |
||
| 1117 | serge | 930 | |
| 5078 | serge | 931 | /* rv6xx, rv7xx */ |
| 932 | if ((rdev->family >= CHIP_RV610) && |
||
| 933 | (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
||
| 934 | selected_sclk = radeon_dpm_get_sclk(rdev, low); |
||
| 935 | else |
||
| 936 | selected_sclk = rdev->pm.current_sclk; |
||
| 937 | |||
| 938 | /* sclk in Mhz */ |
||
| 939 | a.full = dfixed_const(100); |
||
| 940 | sclk.full = dfixed_const(selected_sclk); |
||
| 941 | sclk.full = dfixed_div(sclk, a); |
||
| 942 | |||
| 1963 | serge | 943 | if (crtc->vsc.full > dfixed_const(2)) |
| 944 | wm->num_line_pair.full = dfixed_const(2); |
||
| 1179 | serge | 945 | else |
| 1963 | serge | 946 | wm->num_line_pair.full = dfixed_const(1); |
| 1179 | serge | 947 | |
| 1963 | serge | 948 | b.full = dfixed_const(mode->crtc_hdisplay); |
| 949 | c.full = dfixed_const(256); |
||
| 950 | a.full = dfixed_div(b, c); |
||
| 951 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
||
| 952 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
||
| 953 | if (a.full < dfixed_const(4)) { |
||
| 1179 | serge | 954 | wm->lb_request_fifo_depth = 4; |
| 955 | } else { |
||
| 1963 | serge | 956 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
| 1179 | serge | 957 | } |
| 958 | |||
| 959 | /* Determine consumption rate |
||
| 960 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
| 961 | * vtaps = number of vertical taps, |
||
| 962 | * vsc = vertical scaling ratio, defined as source/destination |
||
| 963 | * hsc = horizontal scaling ration, defined as source/destination |
||
| 964 | */ |
||
| 1963 | serge | 965 | a.full = dfixed_const(mode->clock); |
| 966 | b.full = dfixed_const(1000); |
||
| 967 | a.full = dfixed_div(a, b); |
||
| 968 | pclk.full = dfixed_div(b, a); |
||
| 1179 | serge | 969 | if (crtc->rmx_type != RMX_OFF) { |
| 1963 | serge | 970 | b.full = dfixed_const(2); |
| 1179 | serge | 971 | if (crtc->vsc.full > b.full) |
| 972 | b.full = crtc->vsc.full; |
||
| 1963 | serge | 973 | b.full = dfixed_mul(b, crtc->hsc); |
| 974 | c.full = dfixed_const(2); |
||
| 975 | b.full = dfixed_div(b, c); |
||
| 976 | consumption_time.full = dfixed_div(pclk, b); |
||
| 1179 | serge | 977 | } else { |
| 978 | consumption_time.full = pclk.full; |
||
| 979 | } |
||
| 1963 | serge | 980 | a.full = dfixed_const(1); |
| 981 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
||
| 1179 | serge | 982 | |
| 983 | |||
| 984 | /* Determine line time |
||
| 985 | * LineTime = total time for one line of displayhtotal |
||
| 986 | * LineTime = total number of horizontal pixels |
||
| 987 | * pclk = pixel clock period(ns) |
||
| 988 | */ |
||
| 1963 | serge | 989 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
| 990 | line_time.full = dfixed_mul(a, pclk); |
||
| 1179 | serge | 991 | |
| 992 | /* Determine active time |
||
| 993 | * ActiveTime = time of active region of display within one line, |
||
| 994 | * hactive = total number of horizontal active pixels |
||
| 995 | * htotal = total number of horizontal pixels |
||
| 996 | */ |
||
| 1963 | serge | 997 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
| 998 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 999 | wm->active_time.full = dfixed_mul(line_time, b); |
||
| 1000 | wm->active_time.full = dfixed_div(wm->active_time, a); |
||
| 1179 | serge | 1001 | |
| 1002 | /* Determine chunk time |
||
| 1003 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
| 1004 | * to the LB which consists of pipeline delay and inter chunk gap |
||
| 1005 | * sclk = system clock(Mhz) |
||
| 1006 | */ |
||
| 1963 | serge | 1007 | a.full = dfixed_const(600 * 1000); |
| 5078 | serge | 1008 | chunk_time.full = dfixed_div(a, sclk); |
| 1963 | serge | 1009 | read_delay_latency.full = dfixed_const(1000); |
| 1179 | serge | 1010 | |
| 1011 | /* Determine the worst case latency |
||
| 1012 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
| 1013 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
| 1014 | * to return data |
||
| 1015 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
| 1016 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
| 1017 | * which consists of pipeline delay and inter chunk gap |
||
| 1018 | */ |
||
| 1963 | serge | 1019 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
| 1020 | a.full = dfixed_const(3); |
||
| 1021 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
||
| 1179 | serge | 1022 | wm->worst_case_latency.full += read_delay_latency.full; |
| 1023 | } else { |
||
| 1024 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
| 1025 | } |
||
| 1026 | |||
| 1027 | /* Determine the tolerable latency |
||
| 1028 | * TolerableLatency = Any given request has only 1 line time |
||
| 1029 | * for the data to be returned |
||
| 1030 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
| 1031 | * put into the request FIFO for a display |
||
| 1032 | * LineTime = total time for one line of display |
||
| 1033 | * ChunkTime = the time it takes the DCP to send one chunk |
||
| 1034 | * of data to the LB which consists of |
||
| 1035 | * pipeline delay and inter chunk gap |
||
| 1036 | */ |
||
| 1963 | serge | 1037 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
| 1179 | serge | 1038 | tolerable_latency.full = line_time.full; |
| 1039 | } else { |
||
| 1963 | serge | 1040 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
| 1179 | serge | 1041 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
| 1963 | serge | 1042 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
| 1179 | serge | 1043 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
| 1044 | } |
||
| 1045 | /* We assume worst case 32bits (4 bytes) */ |
||
| 1963 | serge | 1046 | wm->dbpp.full = dfixed_const(2 * 16); |
| 1179 | serge | 1047 | |
| 1048 | /* Determine the maximum priority mark |
||
| 1049 | * width = viewport width in pixels |
||
| 1050 | */ |
||
| 1963 | serge | 1051 | a.full = dfixed_const(16); |
| 1052 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
| 1053 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
||
| 1054 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
||
| 1179 | serge | 1055 | |
| 1056 | /* Determine estimated width */ |
||
| 1057 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
| 1963 | serge | 1058 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
| 1059 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
| 1403 | serge | 1060 | wm->priority_mark.full = wm->priority_mark_max.full; |
| 1179 | serge | 1061 | } else { |
| 1963 | serge | 1062 | a.full = dfixed_const(16); |
| 1063 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
||
| 1064 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
||
| 1179 | serge | 1065 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
| 1066 | } |
||
| 1067 | } |
||
| 1068 | |||
| 5078 | serge | 1069 | static void rv515_compute_mode_priority(struct radeon_device *rdev, |
| 1070 | struct rv515_watermark *wm0, |
||
| 1071 | struct rv515_watermark *wm1, |
||
| 1072 | struct drm_display_mode *mode0, |
||
| 1073 | struct drm_display_mode *mode1, |
||
| 1074 | u32 *d1mode_priority_a_cnt, |
||
| 1075 | u32 *d2mode_priority_a_cnt) |
||
| 1117 | serge | 1076 | { |
| 1179 | serge | 1077 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
| 1078 | fixed20_12 a, b; |
||
| 1117 | serge | 1079 | |
| 5078 | serge | 1080 | *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
| 1081 | *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
||
| 1179 | serge | 1082 | |
| 1083 | if (mode0 && mode1) { |
||
| 5078 | serge | 1084 | if (dfixed_trunc(wm0->dbpp) > 64) |
| 1085 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
||
| 1179 | serge | 1086 | else |
| 5078 | serge | 1087 | a.full = wm0->num_line_pair.full; |
| 1088 | if (dfixed_trunc(wm1->dbpp) > 64) |
||
| 1089 | b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
||
| 1179 | serge | 1090 | else |
| 5078 | serge | 1091 | b.full = wm1->num_line_pair.full; |
| 1179 | serge | 1092 | a.full += b.full; |
| 5078 | serge | 1093 | fill_rate.full = dfixed_div(wm0->sclk, a); |
| 1094 | if (wm0->consumption_rate.full > fill_rate.full) { |
||
| 1095 | b.full = wm0->consumption_rate.full - fill_rate.full; |
||
| 1096 | b.full = dfixed_mul(b, wm0->active_time); |
||
| 1963 | serge | 1097 | a.full = dfixed_const(16); |
| 1098 | b.full = dfixed_div(b, a); |
||
| 5078 | serge | 1099 | a.full = dfixed_mul(wm0->worst_case_latency, |
| 1100 | wm0->consumption_rate); |
||
| 1179 | serge | 1101 | priority_mark02.full = a.full + b.full; |
| 1102 | } else { |
||
| 5078 | serge | 1103 | a.full = dfixed_mul(wm0->worst_case_latency, |
| 1104 | wm0->consumption_rate); |
||
| 1963 | serge | 1105 | b.full = dfixed_const(16 * 1000); |
| 1106 | priority_mark02.full = dfixed_div(a, b); |
||
| 1179 | serge | 1107 | } |
| 5078 | serge | 1108 | if (wm1->consumption_rate.full > fill_rate.full) { |
| 1109 | b.full = wm1->consumption_rate.full - fill_rate.full; |
||
| 1110 | b.full = dfixed_mul(b, wm1->active_time); |
||
| 1963 | serge | 1111 | a.full = dfixed_const(16); |
| 1112 | b.full = dfixed_div(b, a); |
||
| 5078 | serge | 1113 | a.full = dfixed_mul(wm1->worst_case_latency, |
| 1114 | wm1->consumption_rate); |
||
| 1179 | serge | 1115 | priority_mark12.full = a.full + b.full; |
| 1116 | } else { |
||
| 5078 | serge | 1117 | a.full = dfixed_mul(wm1->worst_case_latency, |
| 1118 | wm1->consumption_rate); |
||
| 1963 | serge | 1119 | b.full = dfixed_const(16 * 1000); |
| 1120 | priority_mark12.full = dfixed_div(a, b); |
||
| 1179 | serge | 1121 | } |
| 5078 | serge | 1122 | if (wm0->priority_mark.full > priority_mark02.full) |
| 1123 | priority_mark02.full = wm0->priority_mark.full; |
||
| 1124 | if (wm0->priority_mark_max.full > priority_mark02.full) |
||
| 1125 | priority_mark02.full = wm0->priority_mark_max.full; |
||
| 1126 | if (wm1->priority_mark.full > priority_mark12.full) |
||
| 1127 | priority_mark12.full = wm1->priority_mark.full; |
||
| 1128 | if (wm1->priority_mark_max.full > priority_mark12.full) |
||
| 1129 | priority_mark12.full = wm1->priority_mark_max.full; |
||
| 1130 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
||
| 1131 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
| 1963 | serge | 1132 | if (rdev->disp_priority == 2) { |
| 5078 | serge | 1133 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
| 1134 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
| 1963 | serge | 1135 | } |
| 1179 | serge | 1136 | } else if (mode0) { |
| 5078 | serge | 1137 | if (dfixed_trunc(wm0->dbpp) > 64) |
| 1138 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
||
| 1179 | serge | 1139 | else |
| 5078 | serge | 1140 | a.full = wm0->num_line_pair.full; |
| 1141 | fill_rate.full = dfixed_div(wm0->sclk, a); |
||
| 1142 | if (wm0->consumption_rate.full > fill_rate.full) { |
||
| 1143 | b.full = wm0->consumption_rate.full - fill_rate.full; |
||
| 1144 | b.full = dfixed_mul(b, wm0->active_time); |
||
| 1963 | serge | 1145 | a.full = dfixed_const(16); |
| 1146 | b.full = dfixed_div(b, a); |
||
| 5078 | serge | 1147 | a.full = dfixed_mul(wm0->worst_case_latency, |
| 1148 | wm0->consumption_rate); |
||
| 1179 | serge | 1149 | priority_mark02.full = a.full + b.full; |
| 1150 | } else { |
||
| 5078 | serge | 1151 | a.full = dfixed_mul(wm0->worst_case_latency, |
| 1152 | wm0->consumption_rate); |
||
| 1963 | serge | 1153 | b.full = dfixed_const(16); |
| 1154 | priority_mark02.full = dfixed_div(a, b); |
||
| 1179 | serge | 1155 | } |
| 5078 | serge | 1156 | if (wm0->priority_mark.full > priority_mark02.full) |
| 1157 | priority_mark02.full = wm0->priority_mark.full; |
||
| 1158 | if (wm0->priority_mark_max.full > priority_mark02.full) |
||
| 1159 | priority_mark02.full = wm0->priority_mark_max.full; |
||
| 1160 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
||
| 1963 | serge | 1161 | if (rdev->disp_priority == 2) |
| 5078 | serge | 1162 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
| 1963 | serge | 1163 | } else if (mode1) { |
| 5078 | serge | 1164 | if (dfixed_trunc(wm1->dbpp) > 64) |
| 1165 | a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
||
| 1179 | serge | 1166 | else |
| 5078 | serge | 1167 | a.full = wm1->num_line_pair.full; |
| 1168 | fill_rate.full = dfixed_div(wm1->sclk, a); |
||
| 1169 | if (wm1->consumption_rate.full > fill_rate.full) { |
||
| 1170 | b.full = wm1->consumption_rate.full - fill_rate.full; |
||
| 1171 | b.full = dfixed_mul(b, wm1->active_time); |
||
| 1963 | serge | 1172 | a.full = dfixed_const(16); |
| 1173 | b.full = dfixed_div(b, a); |
||
| 5078 | serge | 1174 | a.full = dfixed_mul(wm1->worst_case_latency, |
| 1175 | wm1->consumption_rate); |
||
| 1179 | serge | 1176 | priority_mark12.full = a.full + b.full; |
| 1177 | } else { |
||
| 5078 | serge | 1178 | a.full = dfixed_mul(wm1->worst_case_latency, |
| 1179 | wm1->consumption_rate); |
||
| 1963 | serge | 1180 | b.full = dfixed_const(16 * 1000); |
| 1181 | priority_mark12.full = dfixed_div(a, b); |
||
| 1179 | serge | 1182 | } |
| 5078 | serge | 1183 | if (wm1->priority_mark.full > priority_mark12.full) |
| 1184 | priority_mark12.full = wm1->priority_mark.full; |
||
| 1185 | if (wm1->priority_mark_max.full > priority_mark12.full) |
||
| 1186 | priority_mark12.full = wm1->priority_mark_max.full; |
||
| 1187 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
| 1963 | serge | 1188 | if (rdev->disp_priority == 2) |
| 5078 | serge | 1189 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
| 1179 | serge | 1190 | } |
| 5078 | serge | 1191 | } |
| 1963 | serge | 1192 | |
| 5078 | serge | 1193 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
| 1194 | { |
||
| 1195 | struct drm_display_mode *mode0 = NULL; |
||
| 1196 | struct drm_display_mode *mode1 = NULL; |
||
| 1197 | struct rv515_watermark wm0_high, wm0_low; |
||
| 1198 | struct rv515_watermark wm1_high, wm1_low; |
||
| 1199 | u32 tmp; |
||
| 1200 | u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; |
||
| 1201 | u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; |
||
| 1202 | |||
| 1203 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
| 1204 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 1205 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 1206 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 1207 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
| 1208 | |||
| 1209 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); |
||
| 1210 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); |
||
| 1211 | |||
| 1212 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); |
||
| 1213 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); |
||
| 1214 | |||
| 1215 | tmp = wm0_high.lb_request_fifo_depth; |
||
| 1216 | tmp |= wm1_high.lb_request_fifo_depth << 16; |
||
| 1217 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
| 1218 | |||
| 1219 | rv515_compute_mode_priority(rdev, |
||
| 1220 | &wm0_high, &wm1_high, |
||
| 1221 | mode0, mode1, |
||
| 1222 | &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); |
||
| 1223 | rv515_compute_mode_priority(rdev, |
||
| 1224 | &wm0_low, &wm1_low, |
||
| 1225 | mode0, mode1, |
||
| 1226 | &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); |
||
| 1227 | |||
| 1963 | serge | 1228 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
| 5078 | serge | 1229 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); |
| 6104 | serge | 1230 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
| 5078 | serge | 1231 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); |
| 1117 | serge | 1232 | } |
| 1179 | serge | 1233 | |
| 1234 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
| 1235 | { |
||
| 1236 | uint32_t tmp; |
||
| 1237 | struct drm_display_mode *mode0 = NULL; |
||
| 1238 | struct drm_display_mode *mode1 = NULL; |
||
| 1239 | |||
| 5271 | serge | 1240 | if (!rdev->mode_info.mode_config_initialized) |
| 1241 | return; |
||
| 1242 | |||
| 1963 | serge | 1243 | radeon_update_display_priority(rdev); |
| 1244 | |||
| 1179 | serge | 1245 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 1246 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
| 1247 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
| 1248 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
| 1249 | /* |
||
| 1250 | * Set display0/1 priority up in the memory controller for |
||
| 1251 | * modes if the user specifies HIGH for displaypriority |
||
| 1252 | * option. |
||
| 1253 | */ |
||
| 1963 | serge | 1254 | if ((rdev->disp_priority == 2) && |
| 1255 | (rdev->family == CHIP_RV515)) { |
||
| 1179 | serge | 1256 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
| 1257 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
| 1258 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
| 1259 | if (mode1) |
||
| 1260 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
| 1261 | if (mode0) |
||
| 1262 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
| 1263 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
| 1264 | } |
||
| 1265 | rv515_bandwidth_avivo_update(rdev); |
||
| 1266 | } |