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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
1179 | serge | 30 | #include "rv515d.h" |
1117 | serge | 31 | #include "radeon.h" |
1963 | serge | 32 | #include "radeon_asic.h" |
1221 | serge | 33 | #include "atom.h" |
1179 | serge | 34 | #include "rv515_reg_safe.h" |
1117 | serge | 35 | |
1221 | serge | 36 | /* This files gather functions specifics to: rv515 */ |
1117 | serge | 37 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
38 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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39 | void rv515_gpu_init(struct radeon_device *rdev); |
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40 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
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41 | |||
1221 | serge | 42 | void rv515_debugfs(struct radeon_device *rdev) |
1117 | serge | 43 | { |
1129 | serge | 44 | if (r100_debugfs_rbbm_init(rdev)) { |
45 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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46 | } |
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47 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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48 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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49 | } |
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50 | if (rv515_debugfs_ga_info_init(rdev)) { |
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51 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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52 | } |
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1117 | serge | 53 | } |
54 | |||
55 | void rv515_ring_start(struct radeon_device *rdev) |
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56 | { |
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57 | int r; |
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58 | |||
59 | r = radeon_ring_lock(rdev, 64); |
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60 | if (r) { |
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61 | return; |
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62 | } |
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1179 | serge | 63 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
1117 | serge | 64 | radeon_ring_write(rdev, |
1179 | serge | 65 | ISYNC_ANY2D_IDLE3D | |
66 | ISYNC_ANY3D_IDLE2D | |
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67 | ISYNC_WAIT_IDLEGUI | |
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68 | ISYNC_CPSCRATCH_IDLEGUI); |
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69 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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70 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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1963 | serge | 71 | radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
72 | radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); |
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1179 | serge | 73 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
1117 | serge | 74 | radeon_ring_write(rdev, 0); |
1179 | serge | 75 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
1117 | serge | 76 | radeon_ring_write(rdev, 0); |
1963 | serge | 77 | radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0)); |
1117 | serge | 78 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
1179 | serge | 79 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
1117 | serge | 80 | radeon_ring_write(rdev, 0); |
1179 | serge | 81 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
82 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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83 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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84 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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85 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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86 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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87 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); |
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1117 | serge | 88 | radeon_ring_write(rdev, 0); |
1179 | serge | 89 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
90 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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91 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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92 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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93 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); |
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1117 | serge | 94 | radeon_ring_write(rdev, |
1179 | serge | 95 | ((6 << MS_X0_SHIFT) | |
96 | (6 << MS_Y0_SHIFT) | |
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97 | (6 << MS_X1_SHIFT) | |
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98 | (6 << MS_Y1_SHIFT) | |
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99 | (6 << MS_X2_SHIFT) | |
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100 | (6 << MS_Y2_SHIFT) | |
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101 | (6 << MSBD0_Y_SHIFT) | |
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102 | (6 << MSBD0_X_SHIFT))); |
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103 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); |
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1117 | serge | 104 | radeon_ring_write(rdev, |
1179 | serge | 105 | ((6 << MS_X3_SHIFT) | |
106 | (6 << MS_Y3_SHIFT) | |
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107 | (6 << MS_X4_SHIFT) | |
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108 | (6 << MS_Y4_SHIFT) | |
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109 | (6 << MS_X5_SHIFT) | |
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110 | (6 << MS_Y5_SHIFT) | |
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111 | (6 << MSBD1_SHIFT))); |
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112 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); |
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113 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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114 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); |
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115 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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116 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
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117 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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1117 | serge | 118 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
119 | radeon_ring_write(rdev, 0); |
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120 | radeon_ring_unlock_commit(rdev); |
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121 | } |
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122 | |||
123 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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124 | { |
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125 | unsigned i; |
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126 | uint32_t tmp; |
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127 | |||
128 | for (i = 0; i < rdev->usec_timeout; i++) { |
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129 | /* read MC_STATUS */ |
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1179 | serge | 130 | tmp = RREG32_MC(MC_STATUS); |
131 | if (tmp & MC_STATUS_IDLE) { |
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1117 | serge | 132 | return 0; |
133 | } |
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134 | DRM_UDELAY(1); |
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135 | } |
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136 | return -1; |
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137 | } |
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138 | |||
1221 | serge | 139 | void rv515_vga_render_disable(struct radeon_device *rdev) |
140 | { |
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141 | WREG32(R_000300_VGA_RENDER_CONTROL, |
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142 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
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143 | } |
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144 | |||
1117 | serge | 145 | void rv515_gpu_init(struct radeon_device *rdev) |
146 | { |
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147 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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148 | |||
149 | if (r100_gui_wait_for_idle(rdev)) { |
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150 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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151 | "reseting GPU. Bad things might happen.\n"); |
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152 | } |
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1221 | serge | 153 | rv515_vga_render_disable(rdev); |
1117 | serge | 154 | r420_pipes_init(rdev); |
1963 | serge | 155 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
156 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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1117 | serge | 157 | pipe_select_current = (tmp >> 2) & 3; |
158 | tmp = (1 << pipe_select_current) | |
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159 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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160 | WREG32_PLL(0x000D, tmp); |
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161 | if (r100_gui_wait_for_idle(rdev)) { |
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162 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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163 | "reseting GPU. Bad things might happen.\n"); |
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164 | } |
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165 | if (rv515_mc_wait_for_idle(rdev)) { |
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166 | printk(KERN_WARNING "Failed to wait MC idle while " |
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167 | "programming pipes. Bad things might happen.\n"); |
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168 | } |
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169 | } |
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170 | |||
171 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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172 | { |
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173 | uint32_t tmp; |
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174 | |||
175 | rdev->mc.vram_width = 128; |
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176 | rdev->mc.vram_is_ddr = true; |
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1179 | serge | 177 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
1117 | serge | 178 | switch (tmp) { |
179 | case 0: |
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180 | rdev->mc.vram_width = 64; |
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181 | break; |
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182 | case 1: |
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183 | rdev->mc.vram_width = 128; |
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184 | break; |
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185 | default: |
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186 | rdev->mc.vram_width = 128; |
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187 | break; |
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188 | } |
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189 | } |
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190 | |||
1430 | serge | 191 | void rv515_mc_init(struct radeon_device *rdev) |
1117 | serge | 192 | { |
1179 | serge | 193 | |
1117 | serge | 194 | rv515_vram_get_type(rdev); |
1179 | serge | 195 | r100_vram_init_sizes(rdev); |
1430 | serge | 196 | radeon_vram_location(rdev, &rdev->mc, 0); |
1963 | serge | 197 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 198 | if (!(rdev->flags & RADEON_IS_AGP)) |
199 | radeon_gtt_location(rdev, &rdev->mc); |
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1963 | serge | 200 | radeon_update_bandwidth_info(rdev); |
1117 | serge | 201 | } |
202 | |||
203 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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204 | { |
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205 | uint32_t r; |
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206 | |||
1179 | serge | 207 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
208 | r = RREG32(MC_IND_DATA); |
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209 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 210 | return r; |
211 | } |
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212 | |||
213 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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214 | { |
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1179 | serge | 215 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
216 | WREG32(MC_IND_DATA, (v)); |
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217 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 218 | } |
219 | |||
220 | #if defined(CONFIG_DEBUG_FS) |
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221 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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222 | { |
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223 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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224 | struct drm_device *dev = node->minor->dev; |
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225 | struct radeon_device *rdev = dev->dev_private; |
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226 | uint32_t tmp; |
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227 | |||
1179 | serge | 228 | tmp = RREG32(GB_PIPE_SELECT); |
1117 | serge | 229 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
1179 | serge | 230 | tmp = RREG32(SU_REG_DEST); |
1117 | serge | 231 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
1179 | serge | 232 | tmp = RREG32(GB_TILE_CONFIG); |
1117 | serge | 233 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
1179 | serge | 234 | tmp = RREG32(DST_PIPE_CONFIG); |
1117 | serge | 235 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
236 | return 0; |
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237 | } |
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238 | |||
239 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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240 | { |
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241 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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242 | struct drm_device *dev = node->minor->dev; |
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243 | struct radeon_device *rdev = dev->dev_private; |
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244 | uint32_t tmp; |
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245 | |||
246 | tmp = RREG32(0x2140); |
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247 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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1963 | serge | 248 | radeon_asic_reset(rdev); |
1117 | serge | 249 | tmp = RREG32(0x425C); |
250 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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251 | return 0; |
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252 | } |
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253 | |||
254 | static struct drm_info_list rv515_pipes_info_list[] = { |
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255 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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256 | }; |
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257 | |||
258 | static struct drm_info_list rv515_ga_info_list[] = { |
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259 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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260 | }; |
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261 | #endif |
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262 | |||
263 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
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264 | { |
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265 | #if defined(CONFIG_DEBUG_FS) |
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266 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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267 | #else |
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268 | return 0; |
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269 | #endif |
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270 | } |
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271 | |||
272 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
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273 | { |
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274 | #if defined(CONFIG_DEBUG_FS) |
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275 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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276 | #else |
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277 | return 0; |
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278 | #endif |
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279 | } |
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280 | |||
1221 | serge | 281 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
1179 | serge | 282 | { |
1221 | serge | 283 | save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); |
284 | save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); |
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285 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
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286 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
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287 | save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); |
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288 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); |
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1179 | serge | 289 | |
1221 | serge | 290 | /* Stop all video */ |
291 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
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292 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
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293 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
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294 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
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295 | WREG32(R_006080_D1CRTC_CONTROL, 0); |
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296 | WREG32(R_006880_D2CRTC_CONTROL, 0); |
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297 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
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298 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
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1313 | serge | 299 | WREG32(R_000330_D1VGA_CONTROL, 0); |
300 | WREG32(R_000338_D2VGA_CONTROL, 0); |
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1221 | serge | 301 | } |
302 | |||
303 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
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304 | { |
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305 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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306 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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307 | WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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308 | WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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309 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); |
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310 | /* Unlock host access */ |
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311 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
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312 | mdelay(1); |
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313 | /* Restore video state */ |
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1313 | serge | 314 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
315 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); |
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1221 | serge | 316 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
317 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
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318 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); |
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319 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); |
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320 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
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321 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
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322 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
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323 | } |
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324 | |||
325 | void rv515_mc_program(struct radeon_device *rdev) |
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326 | { |
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327 | struct rv515_mc_save save; |
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328 | |||
329 | /* Stops all mc clients */ |
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330 | rv515_mc_stop(rdev, &save); |
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331 | |||
332 | /* Wait for mc idle */ |
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333 | if (rv515_mc_wait_for_idle(rdev)) |
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334 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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335 | /* Write VRAM size in case we are limiting it */ |
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336 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
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337 | /* Program MC, should be a 32bits limited address space */ |
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338 | WREG32_MC(R_000001_MC_FB_LOCATION, |
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339 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
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340 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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341 | WREG32(R_000134_HDP_FB_LOCATION, |
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342 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
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343 | if (rdev->flags & RADEON_IS_AGP) { |
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344 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
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345 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
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346 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
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347 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
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348 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
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349 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
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350 | } else { |
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351 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
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352 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
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353 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
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354 | } |
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355 | |||
356 | rv515_mc_resume(rdev, &save); |
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357 | } |
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358 | |||
359 | void rv515_clock_startup(struct radeon_device *rdev) |
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360 | { |
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361 | if (radeon_dynclks != -1 && radeon_dynclks) |
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362 | radeon_atom_set_clock_gating(rdev, 1); |
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363 | /* We need to force on some of the block */ |
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364 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
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365 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
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366 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
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367 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
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368 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
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369 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
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370 | } |
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371 | |||
372 | static int rv515_startup(struct radeon_device *rdev) |
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373 | { |
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374 | int r; |
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375 | |||
376 | rv515_mc_program(rdev); |
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377 | /* Resume clock */ |
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378 | rv515_clock_startup(rdev); |
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379 | /* Initialize GPU configuration (# pipes, ...) */ |
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380 | rv515_gpu_init(rdev); |
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381 | /* Initialize GART (initialize after TTM so we can allocate |
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382 | * memory through TTM but finalize after TTM) */ |
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383 | if (rdev->flags & RADEON_IS_PCIE) { |
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384 | r = rv370_pcie_gart_enable(rdev); |
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385 | if (r) |
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386 | return r; |
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387 | } |
||
388 | /* Enable IRQ */ |
||
389 | // rs600_irq_set(rdev); |
||
1403 | serge | 390 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 391 | /* 1M ring buffer */ |
1413 | serge | 392 | r = r100_cp_init(rdev, 1024 * 1024); |
393 | if (r) { |
||
1963 | serge | 394 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 395 | return r; |
396 | } |
||
1221 | serge | 397 | // r = r100_ib_init(rdev); |
398 | // if (r) { |
||
399 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
||
400 | // return r; |
||
401 | // } |
||
402 | return 0; |
||
403 | } |
||
404 | |||
405 | |||
406 | void rv515_set_safe_registers(struct radeon_device *rdev) |
||
407 | { |
||
1179 | serge | 408 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
409 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
1221 | serge | 410 | } |
411 | |||
412 | int rv515_init(struct radeon_device *rdev) |
||
413 | { |
||
414 | int r; |
||
415 | |||
416 | /* Initialize scratch registers */ |
||
417 | radeon_scratch_init(rdev); |
||
418 | /* Initialize surface registers */ |
||
419 | radeon_surface_init(rdev); |
||
420 | /* TODO: disable VGA need to use VGA request */ |
||
1963 | serge | 421 | /* restore some register to sane defaults */ |
422 | r100_restore_sanity(rdev); |
||
1221 | serge | 423 | /* BIOS*/ |
424 | if (!radeon_get_bios(rdev)) { |
||
425 | if (ASIC_IS_AVIVO(rdev)) |
||
426 | return -EINVAL; |
||
427 | } |
||
428 | if (rdev->is_atom_bios) { |
||
429 | r = radeon_atombios_init(rdev); |
||
430 | if (r) |
||
431 | return r; |
||
432 | } else { |
||
433 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
434 | return -EINVAL; |
||
435 | } |
||
436 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 437 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 438 | dev_warn(rdev->dev, |
439 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
440 | RREG32(R_000E40_RBBM_STATUS), |
||
441 | RREG32(R_0007C0_CP_STAT)); |
||
442 | } |
||
443 | /* check if cards are posted or not */ |
||
1403 | serge | 444 | if (radeon_boot_test_post_card(rdev) == false) |
445 | return -EINVAL; |
||
1221 | serge | 446 | /* Initialize clocks */ |
447 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 448 | /* initialize AGP */ |
449 | if (rdev->flags & RADEON_IS_AGP) { |
||
450 | r = radeon_agp_init(rdev); |
||
451 | if (r) { |
||
452 | radeon_agp_disable(rdev); |
||
453 | } |
||
454 | } |
||
455 | /* initialize memory controller */ |
||
456 | rv515_mc_init(rdev); |
||
1221 | serge | 457 | rv515_debugfs(rdev); |
458 | /* Fence driver */ |
||
459 | // r = radeon_fence_driver_init(rdev); |
||
460 | // if (r) |
||
461 | // return r; |
||
462 | // r = radeon_irq_kms_init(rdev); |
||
463 | // if (r) |
||
464 | // return r; |
||
465 | /* Memory manager */ |
||
1403 | serge | 466 | r = radeon_bo_init(rdev); |
1221 | serge | 467 | if (r) |
468 | return r; |
||
469 | r = rv370_pcie_gart_init(rdev); |
||
470 | if (r) |
||
471 | return r; |
||
472 | rv515_set_safe_registers(rdev); |
||
473 | rdev->accel_working = true; |
||
474 | r = rv515_startup(rdev); |
||
475 | if (r) { |
||
476 | /* Somethings want wront with the accel init stop accel */ |
||
477 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
478 | // r100_cp_fini(rdev); |
||
479 | // r100_wb_fini(rdev); |
||
480 | // r100_ib_fini(rdev); |
||
481 | rv370_pcie_gart_fini(rdev); |
||
482 | // radeon_agp_fini(rdev); |
||
483 | rdev->accel_working = false; |
||
484 | } |
||
1179 | serge | 485 | return 0; |
486 | } |
||
487 | |||
488 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
489 | { |
||
490 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
491 | int data_reg = 0x657c + crtc->crtc_offset; |
||
492 | |||
493 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
494 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
495 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
496 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
497 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
498 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
499 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
500 | WREG32(index_reg, 0x0); |
||
501 | WREG32(data_reg, 0x841880A8); |
||
502 | WREG32(index_reg, 0x1); |
||
503 | WREG32(data_reg, 0x84208680); |
||
504 | WREG32(index_reg, 0x2); |
||
505 | WREG32(data_reg, 0xBFF880B0); |
||
506 | WREG32(index_reg, 0x100); |
||
507 | WREG32(data_reg, 0x83D88088); |
||
508 | WREG32(index_reg, 0x101); |
||
509 | WREG32(data_reg, 0x84608680); |
||
510 | WREG32(index_reg, 0x102); |
||
511 | WREG32(data_reg, 0xBFF080D0); |
||
512 | WREG32(index_reg, 0x200); |
||
513 | WREG32(data_reg, 0x83988068); |
||
514 | WREG32(index_reg, 0x201); |
||
515 | WREG32(data_reg, 0x84A08680); |
||
516 | WREG32(index_reg, 0x202); |
||
517 | WREG32(data_reg, 0xBFF080F8); |
||
518 | WREG32(index_reg, 0x300); |
||
519 | WREG32(data_reg, 0x83588058); |
||
520 | WREG32(index_reg, 0x301); |
||
521 | WREG32(data_reg, 0x84E08660); |
||
522 | WREG32(index_reg, 0x302); |
||
523 | WREG32(data_reg, 0xBFF88120); |
||
524 | WREG32(index_reg, 0x400); |
||
525 | WREG32(data_reg, 0x83188040); |
||
526 | WREG32(index_reg, 0x401); |
||
527 | WREG32(data_reg, 0x85008660); |
||
528 | WREG32(index_reg, 0x402); |
||
529 | WREG32(data_reg, 0xBFF88150); |
||
530 | WREG32(index_reg, 0x500); |
||
531 | WREG32(data_reg, 0x82D88030); |
||
532 | WREG32(index_reg, 0x501); |
||
533 | WREG32(data_reg, 0x85408640); |
||
534 | WREG32(index_reg, 0x502); |
||
535 | WREG32(data_reg, 0xBFF88180); |
||
536 | WREG32(index_reg, 0x600); |
||
537 | WREG32(data_reg, 0x82A08018); |
||
538 | WREG32(index_reg, 0x601); |
||
539 | WREG32(data_reg, 0x85808620); |
||
540 | WREG32(index_reg, 0x602); |
||
541 | WREG32(data_reg, 0xBFF081B8); |
||
542 | WREG32(index_reg, 0x700); |
||
543 | WREG32(data_reg, 0x82608010); |
||
544 | WREG32(index_reg, 0x701); |
||
545 | WREG32(data_reg, 0x85A08600); |
||
546 | WREG32(index_reg, 0x702); |
||
547 | WREG32(data_reg, 0x800081F0); |
||
548 | WREG32(index_reg, 0x800); |
||
549 | WREG32(data_reg, 0x8228BFF8); |
||
550 | WREG32(index_reg, 0x801); |
||
551 | WREG32(data_reg, 0x85E085E0); |
||
552 | WREG32(index_reg, 0x802); |
||
553 | WREG32(data_reg, 0xBFF88228); |
||
554 | WREG32(index_reg, 0x10000); |
||
555 | WREG32(data_reg, 0x82A8BF00); |
||
556 | WREG32(index_reg, 0x10001); |
||
557 | WREG32(data_reg, 0x82A08CC0); |
||
558 | WREG32(index_reg, 0x10002); |
||
559 | WREG32(data_reg, 0x8008BEF8); |
||
560 | WREG32(index_reg, 0x10100); |
||
561 | WREG32(data_reg, 0x81F0BF28); |
||
562 | WREG32(index_reg, 0x10101); |
||
563 | WREG32(data_reg, 0x83608CA0); |
||
564 | WREG32(index_reg, 0x10102); |
||
565 | WREG32(data_reg, 0x8018BED0); |
||
566 | WREG32(index_reg, 0x10200); |
||
567 | WREG32(data_reg, 0x8148BF38); |
||
568 | WREG32(index_reg, 0x10201); |
||
569 | WREG32(data_reg, 0x84408C80); |
||
570 | WREG32(index_reg, 0x10202); |
||
571 | WREG32(data_reg, 0x8008BEB8); |
||
572 | WREG32(index_reg, 0x10300); |
||
573 | WREG32(data_reg, 0x80B0BF78); |
||
574 | WREG32(index_reg, 0x10301); |
||
575 | WREG32(data_reg, 0x85008C20); |
||
576 | WREG32(index_reg, 0x10302); |
||
577 | WREG32(data_reg, 0x8020BEA0); |
||
578 | WREG32(index_reg, 0x10400); |
||
579 | WREG32(data_reg, 0x8028BF90); |
||
580 | WREG32(index_reg, 0x10401); |
||
581 | WREG32(data_reg, 0x85E08BC0); |
||
582 | WREG32(index_reg, 0x10402); |
||
583 | WREG32(data_reg, 0x8018BE90); |
||
584 | WREG32(index_reg, 0x10500); |
||
585 | WREG32(data_reg, 0xBFB8BFB0); |
||
586 | WREG32(index_reg, 0x10501); |
||
587 | WREG32(data_reg, 0x86C08B40); |
||
588 | WREG32(index_reg, 0x10502); |
||
589 | WREG32(data_reg, 0x8010BE90); |
||
590 | WREG32(index_reg, 0x10600); |
||
591 | WREG32(data_reg, 0xBF58BFC8); |
||
592 | WREG32(index_reg, 0x10601); |
||
593 | WREG32(data_reg, 0x87A08AA0); |
||
594 | WREG32(index_reg, 0x10602); |
||
595 | WREG32(data_reg, 0x8010BE98); |
||
596 | WREG32(index_reg, 0x10700); |
||
597 | WREG32(data_reg, 0xBF10BFF0); |
||
598 | WREG32(index_reg, 0x10701); |
||
599 | WREG32(data_reg, 0x886089E0); |
||
600 | WREG32(index_reg, 0x10702); |
||
601 | WREG32(data_reg, 0x8018BEB0); |
||
602 | WREG32(index_reg, 0x10800); |
||
603 | WREG32(data_reg, 0xBED8BFE8); |
||
604 | WREG32(index_reg, 0x10801); |
||
605 | WREG32(data_reg, 0x89408940); |
||
606 | WREG32(index_reg, 0x10802); |
||
607 | WREG32(data_reg, 0xBFE8BED8); |
||
608 | WREG32(index_reg, 0x20000); |
||
609 | WREG32(data_reg, 0x80008000); |
||
610 | WREG32(index_reg, 0x20001); |
||
611 | WREG32(data_reg, 0x90008000); |
||
612 | WREG32(index_reg, 0x20002); |
||
613 | WREG32(data_reg, 0x80008000); |
||
614 | WREG32(index_reg, 0x20003); |
||
615 | WREG32(data_reg, 0x80008000); |
||
616 | WREG32(index_reg, 0x20100); |
||
617 | WREG32(data_reg, 0x80108000); |
||
618 | WREG32(index_reg, 0x20101); |
||
619 | WREG32(data_reg, 0x8FE0BF70); |
||
620 | WREG32(index_reg, 0x20102); |
||
621 | WREG32(data_reg, 0xBFE880C0); |
||
622 | WREG32(index_reg, 0x20103); |
||
623 | WREG32(data_reg, 0x80008000); |
||
624 | WREG32(index_reg, 0x20200); |
||
625 | WREG32(data_reg, 0x8018BFF8); |
||
626 | WREG32(index_reg, 0x20201); |
||
627 | WREG32(data_reg, 0x8F80BF08); |
||
628 | WREG32(index_reg, 0x20202); |
||
629 | WREG32(data_reg, 0xBFD081A0); |
||
630 | WREG32(index_reg, 0x20203); |
||
631 | WREG32(data_reg, 0xBFF88000); |
||
632 | WREG32(index_reg, 0x20300); |
||
633 | WREG32(data_reg, 0x80188000); |
||
634 | WREG32(index_reg, 0x20301); |
||
635 | WREG32(data_reg, 0x8EE0BEC0); |
||
636 | WREG32(index_reg, 0x20302); |
||
637 | WREG32(data_reg, 0xBFB082A0); |
||
638 | WREG32(index_reg, 0x20303); |
||
639 | WREG32(data_reg, 0x80008000); |
||
640 | WREG32(index_reg, 0x20400); |
||
641 | WREG32(data_reg, 0x80188000); |
||
642 | WREG32(index_reg, 0x20401); |
||
643 | WREG32(data_reg, 0x8E00BEA0); |
||
644 | WREG32(index_reg, 0x20402); |
||
645 | WREG32(data_reg, 0xBF8883C0); |
||
646 | WREG32(index_reg, 0x20403); |
||
647 | WREG32(data_reg, 0x80008000); |
||
648 | WREG32(index_reg, 0x20500); |
||
649 | WREG32(data_reg, 0x80188000); |
||
650 | WREG32(index_reg, 0x20501); |
||
651 | WREG32(data_reg, 0x8D00BE90); |
||
652 | WREG32(index_reg, 0x20502); |
||
653 | WREG32(data_reg, 0xBF588500); |
||
654 | WREG32(index_reg, 0x20503); |
||
655 | WREG32(data_reg, 0x80008008); |
||
656 | WREG32(index_reg, 0x20600); |
||
657 | WREG32(data_reg, 0x80188000); |
||
658 | WREG32(index_reg, 0x20601); |
||
659 | WREG32(data_reg, 0x8BC0BE98); |
||
660 | WREG32(index_reg, 0x20602); |
||
661 | WREG32(data_reg, 0xBF308660); |
||
662 | WREG32(index_reg, 0x20603); |
||
663 | WREG32(data_reg, 0x80008008); |
||
664 | WREG32(index_reg, 0x20700); |
||
665 | WREG32(data_reg, 0x80108000); |
||
666 | WREG32(index_reg, 0x20701); |
||
667 | WREG32(data_reg, 0x8A80BEB0); |
||
668 | WREG32(index_reg, 0x20702); |
||
669 | WREG32(data_reg, 0xBF0087C0); |
||
670 | WREG32(index_reg, 0x20703); |
||
671 | WREG32(data_reg, 0x80008008); |
||
672 | WREG32(index_reg, 0x20800); |
||
673 | WREG32(data_reg, 0x80108000); |
||
674 | WREG32(index_reg, 0x20801); |
||
675 | WREG32(data_reg, 0x8920BED0); |
||
676 | WREG32(index_reg, 0x20802); |
||
677 | WREG32(data_reg, 0xBED08920); |
||
678 | WREG32(index_reg, 0x20803); |
||
679 | WREG32(data_reg, 0x80008010); |
||
680 | WREG32(index_reg, 0x30000); |
||
681 | WREG32(data_reg, 0x90008000); |
||
682 | WREG32(index_reg, 0x30001); |
||
683 | WREG32(data_reg, 0x80008000); |
||
684 | WREG32(index_reg, 0x30100); |
||
685 | WREG32(data_reg, 0x8FE0BF90); |
||
686 | WREG32(index_reg, 0x30101); |
||
687 | WREG32(data_reg, 0xBFF880A0); |
||
688 | WREG32(index_reg, 0x30200); |
||
689 | WREG32(data_reg, 0x8F60BF40); |
||
690 | WREG32(index_reg, 0x30201); |
||
691 | WREG32(data_reg, 0xBFE88180); |
||
692 | WREG32(index_reg, 0x30300); |
||
693 | WREG32(data_reg, 0x8EC0BF00); |
||
694 | WREG32(index_reg, 0x30301); |
||
695 | WREG32(data_reg, 0xBFC88280); |
||
696 | WREG32(index_reg, 0x30400); |
||
697 | WREG32(data_reg, 0x8DE0BEE0); |
||
698 | WREG32(index_reg, 0x30401); |
||
699 | WREG32(data_reg, 0xBFA083A0); |
||
700 | WREG32(index_reg, 0x30500); |
||
701 | WREG32(data_reg, 0x8CE0BED0); |
||
702 | WREG32(index_reg, 0x30501); |
||
703 | WREG32(data_reg, 0xBF7884E0); |
||
704 | WREG32(index_reg, 0x30600); |
||
705 | WREG32(data_reg, 0x8BA0BED8); |
||
706 | WREG32(index_reg, 0x30601); |
||
707 | WREG32(data_reg, 0xBF508640); |
||
708 | WREG32(index_reg, 0x30700); |
||
709 | WREG32(data_reg, 0x8A60BEE8); |
||
710 | WREG32(index_reg, 0x30701); |
||
711 | WREG32(data_reg, 0xBF2087A0); |
||
712 | WREG32(index_reg, 0x30800); |
||
713 | WREG32(data_reg, 0x8900BF00); |
||
714 | WREG32(index_reg, 0x30801); |
||
715 | WREG32(data_reg, 0xBF008900); |
||
716 | } |
||
717 | |||
718 | struct rv515_watermark { |
||
719 | u32 lb_request_fifo_depth; |
||
720 | fixed20_12 num_line_pair; |
||
721 | fixed20_12 estimated_width; |
||
722 | fixed20_12 worst_case_latency; |
||
723 | fixed20_12 consumption_rate; |
||
724 | fixed20_12 active_time; |
||
725 | fixed20_12 dbpp; |
||
726 | fixed20_12 priority_mark_max; |
||
727 | fixed20_12 priority_mark; |
||
728 | fixed20_12 sclk; |
||
1117 | serge | 729 | }; |
730 | |||
1179 | serge | 731 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
732 | struct radeon_crtc *crtc, |
||
733 | struct rv515_watermark *wm) |
||
734 | { |
||
735 | struct drm_display_mode *mode = &crtc->base.mode; |
||
736 | fixed20_12 a, b, c; |
||
737 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
738 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
1117 | serge | 739 | |
1179 | serge | 740 | if (!crtc->base.enabled) { |
741 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
742 | wm->lb_request_fifo_depth = 4; |
||
743 | return; |
||
744 | } |
||
1117 | serge | 745 | |
1963 | serge | 746 | if (crtc->vsc.full > dfixed_const(2)) |
747 | wm->num_line_pair.full = dfixed_const(2); |
||
1179 | serge | 748 | else |
1963 | serge | 749 | wm->num_line_pair.full = dfixed_const(1); |
1179 | serge | 750 | |
1963 | serge | 751 | b.full = dfixed_const(mode->crtc_hdisplay); |
752 | c.full = dfixed_const(256); |
||
753 | a.full = dfixed_div(b, c); |
||
754 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
||
755 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
||
756 | if (a.full < dfixed_const(4)) { |
||
1179 | serge | 757 | wm->lb_request_fifo_depth = 4; |
758 | } else { |
||
1963 | serge | 759 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
1179 | serge | 760 | } |
761 | |||
762 | /* Determine consumption rate |
||
763 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
764 | * vtaps = number of vertical taps, |
||
765 | * vsc = vertical scaling ratio, defined as source/destination |
||
766 | * hsc = horizontal scaling ration, defined as source/destination |
||
767 | */ |
||
1963 | serge | 768 | a.full = dfixed_const(mode->clock); |
769 | b.full = dfixed_const(1000); |
||
770 | a.full = dfixed_div(a, b); |
||
771 | pclk.full = dfixed_div(b, a); |
||
1179 | serge | 772 | if (crtc->rmx_type != RMX_OFF) { |
1963 | serge | 773 | b.full = dfixed_const(2); |
1179 | serge | 774 | if (crtc->vsc.full > b.full) |
775 | b.full = crtc->vsc.full; |
||
1963 | serge | 776 | b.full = dfixed_mul(b, crtc->hsc); |
777 | c.full = dfixed_const(2); |
||
778 | b.full = dfixed_div(b, c); |
||
779 | consumption_time.full = dfixed_div(pclk, b); |
||
1179 | serge | 780 | } else { |
781 | consumption_time.full = pclk.full; |
||
782 | } |
||
1963 | serge | 783 | a.full = dfixed_const(1); |
784 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
||
1179 | serge | 785 | |
786 | |||
787 | /* Determine line time |
||
788 | * LineTime = total time for one line of displayhtotal |
||
789 | * LineTime = total number of horizontal pixels |
||
790 | * pclk = pixel clock period(ns) |
||
791 | */ |
||
1963 | serge | 792 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
793 | line_time.full = dfixed_mul(a, pclk); |
||
1179 | serge | 794 | |
795 | /* Determine active time |
||
796 | * ActiveTime = time of active region of display within one line, |
||
797 | * hactive = total number of horizontal active pixels |
||
798 | * htotal = total number of horizontal pixels |
||
799 | */ |
||
1963 | serge | 800 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
801 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
802 | wm->active_time.full = dfixed_mul(line_time, b); |
||
803 | wm->active_time.full = dfixed_div(wm->active_time, a); |
||
1179 | serge | 804 | |
805 | /* Determine chunk time |
||
806 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
807 | * to the LB which consists of pipeline delay and inter chunk gap |
||
808 | * sclk = system clock(Mhz) |
||
809 | */ |
||
1963 | serge | 810 | a.full = dfixed_const(600 * 1000); |
811 | chunk_time.full = dfixed_div(a, rdev->pm.sclk); |
||
812 | read_delay_latency.full = dfixed_const(1000); |
||
1179 | serge | 813 | |
814 | /* Determine the worst case latency |
||
815 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
816 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
817 | * to return data |
||
818 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
819 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
820 | * which consists of pipeline delay and inter chunk gap |
||
821 | */ |
||
1963 | serge | 822 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
823 | a.full = dfixed_const(3); |
||
824 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
||
1179 | serge | 825 | wm->worst_case_latency.full += read_delay_latency.full; |
826 | } else { |
||
827 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
828 | } |
||
829 | |||
830 | /* Determine the tolerable latency |
||
831 | * TolerableLatency = Any given request has only 1 line time |
||
832 | * for the data to be returned |
||
833 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
834 | * put into the request FIFO for a display |
||
835 | * LineTime = total time for one line of display |
||
836 | * ChunkTime = the time it takes the DCP to send one chunk |
||
837 | * of data to the LB which consists of |
||
838 | * pipeline delay and inter chunk gap |
||
839 | */ |
||
1963 | serge | 840 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
1179 | serge | 841 | tolerable_latency.full = line_time.full; |
842 | } else { |
||
1963 | serge | 843 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
1179 | serge | 844 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
1963 | serge | 845 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
1179 | serge | 846 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
847 | } |
||
848 | /* We assume worst case 32bits (4 bytes) */ |
||
1963 | serge | 849 | wm->dbpp.full = dfixed_const(2 * 16); |
1179 | serge | 850 | |
851 | /* Determine the maximum priority mark |
||
852 | * width = viewport width in pixels |
||
853 | */ |
||
1963 | serge | 854 | a.full = dfixed_const(16); |
855 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
856 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
||
857 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
||
1179 | serge | 858 | |
859 | /* Determine estimated width */ |
||
860 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
1963 | serge | 861 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
862 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
1403 | serge | 863 | wm->priority_mark.full = wm->priority_mark_max.full; |
1179 | serge | 864 | } else { |
1963 | serge | 865 | a.full = dfixed_const(16); |
866 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
||
867 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
||
1179 | serge | 868 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
869 | } |
||
870 | } |
||
871 | |||
872 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
||
1117 | serge | 873 | { |
1179 | serge | 874 | struct drm_display_mode *mode0 = NULL; |
875 | struct drm_display_mode *mode1 = NULL; |
||
876 | struct rv515_watermark wm0; |
||
877 | struct rv515_watermark wm1; |
||
878 | u32 tmp; |
||
1963 | serge | 879 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
880 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
||
1179 | serge | 881 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
882 | fixed20_12 a, b; |
||
1117 | serge | 883 | |
1179 | serge | 884 | if (rdev->mode_info.crtcs[0]->base.enabled) |
885 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
886 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
887 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
888 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
889 | |||
890 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
891 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
892 | |||
893 | tmp = wm0.lb_request_fifo_depth; |
||
894 | tmp |= wm1.lb_request_fifo_depth << 16; |
||
895 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
896 | |||
897 | if (mode0 && mode1) { |
||
1963 | serge | 898 | if (dfixed_trunc(wm0.dbpp) > 64) |
899 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 900 | else |
901 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 902 | if (dfixed_trunc(wm1.dbpp) > 64) |
903 | b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 904 | else |
905 | b.full = wm1.num_line_pair.full; |
||
906 | a.full += b.full; |
||
1963 | serge | 907 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 908 | if (wm0.consumption_rate.full > fill_rate.full) { |
909 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 910 | b.full = dfixed_mul(b, wm0.active_time); |
911 | a.full = dfixed_const(16); |
||
912 | b.full = dfixed_div(b, a); |
||
913 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 914 | wm0.consumption_rate); |
915 | priority_mark02.full = a.full + b.full; |
||
916 | } else { |
||
1963 | serge | 917 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 918 | wm0.consumption_rate); |
1963 | serge | 919 | b.full = dfixed_const(16 * 1000); |
920 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 921 | } |
922 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
923 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 924 | b.full = dfixed_mul(b, wm1.active_time); |
925 | a.full = dfixed_const(16); |
||
926 | b.full = dfixed_div(b, a); |
||
927 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 928 | wm1.consumption_rate); |
929 | priority_mark12.full = a.full + b.full; |
||
930 | } else { |
||
1963 | serge | 931 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 932 | wm1.consumption_rate); |
1963 | serge | 933 | b.full = dfixed_const(16 * 1000); |
934 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 935 | } |
936 | if (wm0.priority_mark.full > priority_mark02.full) |
||
937 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 938 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 939 | priority_mark02.full = 0; |
940 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
941 | priority_mark02.full = wm0.priority_mark_max.full; |
||
942 | if (wm1.priority_mark.full > priority_mark12.full) |
||
943 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 944 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 945 | priority_mark12.full = 0; |
946 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
947 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 948 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
949 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
950 | if (rdev->disp_priority == 2) { |
||
951 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
952 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
953 | } |
||
1179 | serge | 954 | } else if (mode0) { |
1963 | serge | 955 | if (dfixed_trunc(wm0.dbpp) > 64) |
956 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 957 | else |
958 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 959 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 960 | if (wm0.consumption_rate.full > fill_rate.full) { |
961 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 962 | b.full = dfixed_mul(b, wm0.active_time); |
963 | a.full = dfixed_const(16); |
||
964 | b.full = dfixed_div(b, a); |
||
965 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 966 | wm0.consumption_rate); |
967 | priority_mark02.full = a.full + b.full; |
||
968 | } else { |
||
1963 | serge | 969 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 970 | wm0.consumption_rate); |
1963 | serge | 971 | b.full = dfixed_const(16); |
972 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 973 | } |
974 | if (wm0.priority_mark.full > priority_mark02.full) |
||
975 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 976 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 977 | priority_mark02.full = 0; |
978 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
979 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1963 | serge | 980 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
981 | if (rdev->disp_priority == 2) |
||
982 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
983 | } else if (mode1) { |
||
984 | if (dfixed_trunc(wm1.dbpp) > 64) |
||
985 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 986 | else |
987 | a.full = wm1.num_line_pair.full; |
||
1963 | serge | 988 | fill_rate.full = dfixed_div(wm1.sclk, a); |
1179 | serge | 989 | if (wm1.consumption_rate.full > fill_rate.full) { |
990 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 991 | b.full = dfixed_mul(b, wm1.active_time); |
992 | a.full = dfixed_const(16); |
||
993 | b.full = dfixed_div(b, a); |
||
994 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 995 | wm1.consumption_rate); |
996 | priority_mark12.full = a.full + b.full; |
||
997 | } else { |
||
1963 | serge | 998 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 999 | wm1.consumption_rate); |
1963 | serge | 1000 | b.full = dfixed_const(16 * 1000); |
1001 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 1002 | } |
1003 | if (wm1.priority_mark.full > priority_mark12.full) |
||
1004 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 1005 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 1006 | priority_mark12.full = 0; |
1007 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
1008 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 1009 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1010 | if (rdev->disp_priority == 2) |
||
1011 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
||
1179 | serge | 1012 | } |
1963 | serge | 1013 | |
1014 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
1015 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
1016 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
1017 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
1117 | serge | 1018 | } |
1179 | serge | 1019 | |
1020 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
1021 | { |
||
1022 | uint32_t tmp; |
||
1023 | struct drm_display_mode *mode0 = NULL; |
||
1024 | struct drm_display_mode *mode1 = NULL; |
||
1025 | |||
1963 | serge | 1026 | radeon_update_display_priority(rdev); |
1027 | |||
1179 | serge | 1028 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1029 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
1030 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
1031 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
1032 | /* |
||
1033 | * Set display0/1 priority up in the memory controller for |
||
1034 | * modes if the user specifies HIGH for displaypriority |
||
1035 | * option. |
||
1036 | */ |
||
1963 | serge | 1037 | if ((rdev->disp_priority == 2) && |
1038 | (rdev->family == CHIP_RV515)) { |
||
1179 | serge | 1039 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1040 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
1041 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
1042 | if (mode1) |
||
1043 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
1044 | if (mode0) |
||
1045 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
1046 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
1047 | } |
||
1048 | rv515_bandwidth_avivo_update(rdev); |
||
1049 | }><>><>>>>>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |