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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
1179 | serge | 30 | #include "rv515d.h" |
1117 | serge | 31 | #include "radeon.h" |
1221 | serge | 32 | #include "atom.h" |
1179 | serge | 33 | #include "rv515_reg_safe.h" |
1117 | serge | 34 | |
1221 | serge | 35 | /* This files gather functions specifics to: rv515 */ |
1117 | serge | 36 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
37 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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38 | void rv515_gpu_init(struct radeon_device *rdev); |
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39 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
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40 | |||
1221 | serge | 41 | void rv515_debugfs(struct radeon_device *rdev) |
1117 | serge | 42 | { |
1129 | serge | 43 | if (r100_debugfs_rbbm_init(rdev)) { |
44 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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45 | } |
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46 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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47 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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48 | } |
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49 | if (rv515_debugfs_ga_info_init(rdev)) { |
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50 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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51 | } |
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1117 | serge | 52 | } |
53 | |||
54 | void rv515_ring_start(struct radeon_device *rdev) |
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55 | { |
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56 | int r; |
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57 | |||
58 | r = radeon_ring_lock(rdev, 64); |
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59 | if (r) { |
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60 | return; |
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61 | } |
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1179 | serge | 62 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
1117 | serge | 63 | radeon_ring_write(rdev, |
1179 | serge | 64 | ISYNC_ANY2D_IDLE3D | |
65 | ISYNC_ANY3D_IDLE2D | |
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66 | ISYNC_WAIT_IDLEGUI | |
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67 | ISYNC_CPSCRATCH_IDLEGUI); |
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68 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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69 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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1117 | serge | 70 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
71 | radeon_ring_write(rdev, 1 << 31); |
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1179 | serge | 72 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
1117 | serge | 73 | radeon_ring_write(rdev, 0); |
1179 | serge | 74 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
1117 | serge | 75 | radeon_ring_write(rdev, 0); |
76 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
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77 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
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1179 | serge | 78 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
1117 | serge | 79 | radeon_ring_write(rdev, 0); |
1179 | serge | 80 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
81 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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82 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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83 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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84 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
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85 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
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86 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); |
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1117 | serge | 87 | radeon_ring_write(rdev, 0); |
1179 | serge | 88 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
89 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
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90 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
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91 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
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92 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); |
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1117 | serge | 93 | radeon_ring_write(rdev, |
1179 | serge | 94 | ((6 << MS_X0_SHIFT) | |
95 | (6 << MS_Y0_SHIFT) | |
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96 | (6 << MS_X1_SHIFT) | |
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97 | (6 << MS_Y1_SHIFT) | |
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98 | (6 << MS_X2_SHIFT) | |
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99 | (6 << MS_Y2_SHIFT) | |
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100 | (6 << MSBD0_Y_SHIFT) | |
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101 | (6 << MSBD0_X_SHIFT))); |
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102 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); |
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1117 | serge | 103 | radeon_ring_write(rdev, |
1179 | serge | 104 | ((6 << MS_X3_SHIFT) | |
105 | (6 << MS_Y3_SHIFT) | |
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106 | (6 << MS_X4_SHIFT) | |
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107 | (6 << MS_Y4_SHIFT) | |
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108 | (6 << MS_X5_SHIFT) | |
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109 | (6 << MS_Y5_SHIFT) | |
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110 | (6 << MSBD1_SHIFT))); |
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111 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); |
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112 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
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113 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); |
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114 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
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115 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
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116 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
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1117 | serge | 117 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
118 | radeon_ring_write(rdev, 0); |
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119 | radeon_ring_unlock_commit(rdev); |
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120 | } |
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121 | |||
122 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
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123 | { |
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124 | unsigned i; |
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125 | uint32_t tmp; |
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126 | |||
127 | for (i = 0; i < rdev->usec_timeout; i++) { |
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128 | /* read MC_STATUS */ |
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1179 | serge | 129 | tmp = RREG32_MC(MC_STATUS); |
130 | if (tmp & MC_STATUS_IDLE) { |
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1117 | serge | 131 | return 0; |
132 | } |
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133 | DRM_UDELAY(1); |
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134 | } |
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135 | return -1; |
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136 | } |
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137 | |||
1221 | serge | 138 | void rv515_vga_render_disable(struct radeon_device *rdev) |
139 | { |
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140 | WREG32(R_000300_VGA_RENDER_CONTROL, |
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141 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
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142 | } |
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143 | |||
1117 | serge | 144 | void rv515_gpu_init(struct radeon_device *rdev) |
145 | { |
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146 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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147 | |||
148 | r100_hdp_reset(rdev); |
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149 | r100_rb2d_reset(rdev); |
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150 | |||
151 | if (r100_gui_wait_for_idle(rdev)) { |
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152 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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153 | "reseting GPU. Bad things might happen.\n"); |
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154 | } |
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155 | |||
1221 | serge | 156 | rv515_vga_render_disable(rdev); |
1117 | serge | 157 | |
158 | r420_pipes_init(rdev); |
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159 | gb_pipe_select = RREG32(0x402C); |
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160 | tmp = RREG32(0x170C); |
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161 | pipe_select_current = (tmp >> 2) & 3; |
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162 | tmp = (1 << pipe_select_current) | |
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163 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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164 | WREG32_PLL(0x000D, tmp); |
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165 | if (r100_gui_wait_for_idle(rdev)) { |
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166 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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167 | "reseting GPU. Bad things might happen.\n"); |
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168 | } |
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169 | if (rv515_mc_wait_for_idle(rdev)) { |
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170 | printk(KERN_WARNING "Failed to wait MC idle while " |
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171 | "programming pipes. Bad things might happen.\n"); |
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172 | } |
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173 | } |
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174 | |||
175 | int rv515_ga_reset(struct radeon_device *rdev) |
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176 | { |
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177 | uint32_t tmp; |
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178 | bool reinit_cp; |
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179 | int i; |
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180 | |||
181 | reinit_cp = rdev->cp.ready; |
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182 | rdev->cp.ready = false; |
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183 | for (i = 0; i < rdev->usec_timeout; i++) { |
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1179 | serge | 184 | WREG32(CP_CSQ_MODE, 0); |
185 | WREG32(CP_CSQ_CNTL, 0); |
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186 | WREG32(RBBM_SOFT_RESET, 0x32005); |
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187 | (void)RREG32(RBBM_SOFT_RESET); |
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1117 | serge | 188 | udelay(200); |
1179 | serge | 189 | WREG32(RBBM_SOFT_RESET, 0); |
1117 | serge | 190 | /* Wait to prevent race in RBBM_STATUS */ |
191 | mdelay(1); |
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1179 | serge | 192 | tmp = RREG32(RBBM_STATUS); |
1117 | serge | 193 | if (tmp & ((1 << 20) | (1 << 26))) { |
194 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
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195 | /* GA still busy soft reset it */ |
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196 | WREG32(0x429C, 0x200); |
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1179 | serge | 197 | WREG32(VAP_PVS_STATE_FLUSH_REG, 0); |
1117 | serge | 198 | WREG32(0x43E0, 0); |
199 | WREG32(0x43E4, 0); |
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200 | WREG32(0x24AC, 0); |
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201 | } |
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202 | /* Wait to prevent race in RBBM_STATUS */ |
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203 | mdelay(1); |
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1179 | serge | 204 | tmp = RREG32(RBBM_STATUS); |
1117 | serge | 205 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
206 | break; |
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207 | } |
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208 | } |
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209 | for (i = 0; i < rdev->usec_timeout; i++) { |
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1179 | serge | 210 | tmp = RREG32(RBBM_STATUS); |
1117 | serge | 211 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
212 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
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213 | tmp); |
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214 | DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); |
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215 | DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); |
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216 | DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); |
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217 | if (reinit_cp) { |
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218 | return r100_cp_init(rdev, rdev->cp.ring_size); |
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219 | } |
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220 | return 0; |
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221 | } |
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222 | DRM_UDELAY(1); |
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223 | } |
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1179 | serge | 224 | tmp = RREG32(RBBM_STATUS); |
1117 | serge | 225 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
226 | return -1; |
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227 | } |
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228 | |||
229 | int rv515_gpu_reset(struct radeon_device *rdev) |
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230 | { |
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231 | uint32_t status; |
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232 | |||
233 | /* reset order likely matter */ |
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1179 | serge | 234 | status = RREG32(RBBM_STATUS); |
1117 | serge | 235 | /* reset HDP */ |
236 | r100_hdp_reset(rdev); |
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237 | /* reset rb2d */ |
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238 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
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239 | r100_rb2d_reset(rdev); |
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240 | } |
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241 | /* reset GA */ |
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242 | if (status & ((1 << 20) | (1 << 26))) { |
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243 | rv515_ga_reset(rdev); |
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244 | } |
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245 | /* reset CP */ |
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1179 | serge | 246 | status = RREG32(RBBM_STATUS); |
1117 | serge | 247 | if (status & (1 << 16)) { |
248 | r100_cp_reset(rdev); |
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249 | } |
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250 | /* Check if GPU is idle */ |
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1179 | serge | 251 | status = RREG32(RBBM_STATUS); |
1117 | serge | 252 | if (status & (1 << 31)) { |
253 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
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254 | return -1; |
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255 | } |
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256 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
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257 | return 0; |
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258 | } |
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259 | |||
260 | static void rv515_vram_get_type(struct radeon_device *rdev) |
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261 | { |
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262 | uint32_t tmp; |
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263 | |||
264 | rdev->mc.vram_width = 128; |
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265 | rdev->mc.vram_is_ddr = true; |
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1179 | serge | 266 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
1117 | serge | 267 | switch (tmp) { |
268 | case 0: |
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269 | rdev->mc.vram_width = 64; |
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270 | break; |
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271 | case 1: |
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272 | rdev->mc.vram_width = 128; |
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273 | break; |
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274 | default: |
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275 | rdev->mc.vram_width = 128; |
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276 | break; |
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277 | } |
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278 | } |
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279 | |||
1430 | serge | 280 | void rv515_mc_init(struct radeon_device *rdev) |
1117 | serge | 281 | { |
1179 | serge | 282 | fixed20_12 a; |
283 | |||
1117 | serge | 284 | rv515_vram_get_type(rdev); |
1179 | serge | 285 | r100_vram_init_sizes(rdev); |
1430 | serge | 286 | radeon_vram_location(rdev, &rdev->mc, 0); |
287 | if (!(rdev->flags & RADEON_IS_AGP)) |
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288 | radeon_gtt_location(rdev, &rdev->mc); |
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1179 | serge | 289 | /* FIXME: we should enforce default clock in case GPU is not in |
290 | * default setup |
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291 | */ |
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292 | a.full = rfixed_const(100); |
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293 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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294 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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1117 | serge | 295 | } |
296 | |||
297 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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298 | { |
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299 | uint32_t r; |
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300 | |||
1179 | serge | 301 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
302 | r = RREG32(MC_IND_DATA); |
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303 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 304 | return r; |
305 | } |
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306 | |||
307 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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308 | { |
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1179 | serge | 309 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
310 | WREG32(MC_IND_DATA, (v)); |
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311 | WREG32(MC_IND_INDEX, 0); |
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1117 | serge | 312 | } |
313 | |||
314 | #if defined(CONFIG_DEBUG_FS) |
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315 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
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316 | { |
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317 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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318 | struct drm_device *dev = node->minor->dev; |
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319 | struct radeon_device *rdev = dev->dev_private; |
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320 | uint32_t tmp; |
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321 | |||
1179 | serge | 322 | tmp = RREG32(GB_PIPE_SELECT); |
1117 | serge | 323 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
1179 | serge | 324 | tmp = RREG32(SU_REG_DEST); |
1117 | serge | 325 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
1179 | serge | 326 | tmp = RREG32(GB_TILE_CONFIG); |
1117 | serge | 327 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
1179 | serge | 328 | tmp = RREG32(DST_PIPE_CONFIG); |
1117 | serge | 329 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
330 | return 0; |
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331 | } |
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332 | |||
333 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
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334 | { |
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335 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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336 | struct drm_device *dev = node->minor->dev; |
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337 | struct radeon_device *rdev = dev->dev_private; |
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338 | uint32_t tmp; |
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339 | |||
340 | tmp = RREG32(0x2140); |
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341 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
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342 | radeon_gpu_reset(rdev); |
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343 | tmp = RREG32(0x425C); |
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344 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
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345 | return 0; |
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346 | } |
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347 | |||
348 | static struct drm_info_list rv515_pipes_info_list[] = { |
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349 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
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350 | }; |
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351 | |||
352 | static struct drm_info_list rv515_ga_info_list[] = { |
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353 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
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354 | }; |
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355 | #endif |
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356 | |||
357 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
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358 | { |
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359 | #if defined(CONFIG_DEBUG_FS) |
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360 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
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361 | #else |
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362 | return 0; |
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363 | #endif |
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364 | } |
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365 | |||
366 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
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367 | { |
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368 | #if defined(CONFIG_DEBUG_FS) |
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369 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
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370 | #else |
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371 | return 0; |
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372 | #endif |
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373 | } |
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374 | |||
1221 | serge | 375 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
1179 | serge | 376 | { |
1221 | serge | 377 | save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); |
378 | save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); |
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379 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
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380 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
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381 | save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); |
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382 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); |
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1179 | serge | 383 | |
1221 | serge | 384 | /* Stop all video */ |
385 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
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386 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
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387 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
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388 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
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389 | WREG32(R_006080_D1CRTC_CONTROL, 0); |
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390 | WREG32(R_006880_D2CRTC_CONTROL, 0); |
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391 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
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392 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
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1313 | serge | 393 | WREG32(R_000330_D1VGA_CONTROL, 0); |
394 | WREG32(R_000338_D2VGA_CONTROL, 0); |
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1221 | serge | 395 | } |
396 | |||
397 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
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398 | { |
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399 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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400 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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401 | WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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402 | WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
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403 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); |
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404 | /* Unlock host access */ |
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405 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
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406 | mdelay(1); |
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407 | /* Restore video state */ |
||
1313 | serge | 408 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
409 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); |
||
1221 | serge | 410 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
411 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
||
412 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); |
||
413 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); |
||
414 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
||
415 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
||
416 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
||
417 | } |
||
418 | |||
419 | void rv515_mc_program(struct radeon_device *rdev) |
||
420 | { |
||
421 | struct rv515_mc_save save; |
||
422 | |||
423 | /* Stops all mc clients */ |
||
424 | rv515_mc_stop(rdev, &save); |
||
425 | |||
426 | /* Wait for mc idle */ |
||
427 | if (rv515_mc_wait_for_idle(rdev)) |
||
428 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
429 | /* Write VRAM size in case we are limiting it */ |
||
430 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
431 | /* Program MC, should be a 32bits limited address space */ |
||
432 | WREG32_MC(R_000001_MC_FB_LOCATION, |
||
433 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
434 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
435 | WREG32(R_000134_HDP_FB_LOCATION, |
||
436 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
437 | if (rdev->flags & RADEON_IS_AGP) { |
||
438 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
||
439 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
440 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
441 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
442 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
||
443 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
||
444 | } else { |
||
445 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
||
446 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
||
447 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
||
448 | } |
||
449 | |||
450 | rv515_mc_resume(rdev, &save); |
||
451 | } |
||
452 | |||
453 | void rv515_clock_startup(struct radeon_device *rdev) |
||
454 | { |
||
455 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
456 | radeon_atom_set_clock_gating(rdev, 1); |
||
457 | /* We need to force on some of the block */ |
||
458 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
||
459 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
||
460 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
||
461 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
||
462 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
||
463 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
||
464 | } |
||
465 | |||
466 | static int rv515_startup(struct radeon_device *rdev) |
||
467 | { |
||
468 | int r; |
||
469 | |||
470 | rv515_mc_program(rdev); |
||
471 | /* Resume clock */ |
||
472 | rv515_clock_startup(rdev); |
||
473 | /* Initialize GPU configuration (# pipes, ...) */ |
||
474 | rv515_gpu_init(rdev); |
||
475 | /* Initialize GART (initialize after TTM so we can allocate |
||
476 | * memory through TTM but finalize after TTM) */ |
||
477 | if (rdev->flags & RADEON_IS_PCIE) { |
||
478 | r = rv370_pcie_gart_enable(rdev); |
||
479 | if (r) |
||
480 | return r; |
||
481 | } |
||
482 | /* Enable IRQ */ |
||
483 | // rs600_irq_set(rdev); |
||
1403 | serge | 484 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 485 | /* 1M ring buffer */ |
1413 | serge | 486 | r = r100_cp_init(rdev, 1024 * 1024); |
487 | if (r) { |
||
488 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
||
489 | return r; |
||
490 | } |
||
1221 | serge | 491 | // r = r100_wb_init(rdev); |
492 | // if (r) |
||
493 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
||
494 | // r = r100_ib_init(rdev); |
||
495 | // if (r) { |
||
496 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
||
497 | // return r; |
||
498 | // } |
||
499 | return 0; |
||
500 | } |
||
501 | |||
502 | |||
503 | void rv515_set_safe_registers(struct radeon_device *rdev) |
||
504 | { |
||
1179 | serge | 505 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
506 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
||
1221 | serge | 507 | } |
508 | |||
509 | int rv515_init(struct radeon_device *rdev) |
||
510 | { |
||
511 | int r; |
||
512 | |||
513 | /* Initialize scratch registers */ |
||
514 | radeon_scratch_init(rdev); |
||
515 | /* Initialize surface registers */ |
||
516 | radeon_surface_init(rdev); |
||
517 | /* TODO: disable VGA need to use VGA request */ |
||
518 | /* BIOS*/ |
||
519 | if (!radeon_get_bios(rdev)) { |
||
520 | if (ASIC_IS_AVIVO(rdev)) |
||
521 | return -EINVAL; |
||
522 | } |
||
523 | if (rdev->is_atom_bios) { |
||
524 | r = radeon_atombios_init(rdev); |
||
525 | if (r) |
||
526 | return r; |
||
527 | } else { |
||
528 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
529 | return -EINVAL; |
||
530 | } |
||
531 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
532 | if (radeon_gpu_reset(rdev)) { |
||
533 | dev_warn(rdev->dev, |
||
534 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
535 | RREG32(R_000E40_RBBM_STATUS), |
||
536 | RREG32(R_0007C0_CP_STAT)); |
||
537 | } |
||
538 | /* check if cards are posted or not */ |
||
1403 | serge | 539 | if (radeon_boot_test_post_card(rdev) == false) |
540 | return -EINVAL; |
||
1221 | serge | 541 | /* Initialize clocks */ |
542 | radeon_get_clock_info(rdev->ddev); |
||
1268 | serge | 543 | /* Initialize power management */ |
544 | radeon_pm_init(rdev); |
||
1430 | serge | 545 | /* initialize AGP */ |
546 | if (rdev->flags & RADEON_IS_AGP) { |
||
547 | r = radeon_agp_init(rdev); |
||
548 | if (r) { |
||
549 | radeon_agp_disable(rdev); |
||
550 | } |
||
551 | } |
||
552 | /* initialize memory controller */ |
||
553 | rv515_mc_init(rdev); |
||
1221 | serge | 554 | rv515_debugfs(rdev); |
555 | /* Fence driver */ |
||
556 | // r = radeon_fence_driver_init(rdev); |
||
557 | // if (r) |
||
558 | // return r; |
||
559 | // r = radeon_irq_kms_init(rdev); |
||
560 | // if (r) |
||
561 | // return r; |
||
562 | /* Memory manager */ |
||
1403 | serge | 563 | r = radeon_bo_init(rdev); |
1221 | serge | 564 | if (r) |
565 | return r; |
||
566 | r = rv370_pcie_gart_init(rdev); |
||
567 | if (r) |
||
568 | return r; |
||
569 | rv515_set_safe_registers(rdev); |
||
570 | rdev->accel_working = true; |
||
571 | r = rv515_startup(rdev); |
||
572 | if (r) { |
||
573 | /* Somethings want wront with the accel init stop accel */ |
||
574 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
575 | // r100_cp_fini(rdev); |
||
576 | // r100_wb_fini(rdev); |
||
577 | // r100_ib_fini(rdev); |
||
578 | rv370_pcie_gart_fini(rdev); |
||
579 | // radeon_agp_fini(rdev); |
||
580 | rdev->accel_working = false; |
||
581 | } |
||
1179 | serge | 582 | return 0; |
583 | } |
||
584 | |||
585 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
||
586 | { |
||
587 | int index_reg = 0x6578 + crtc->crtc_offset; |
||
588 | int data_reg = 0x657c + crtc->crtc_offset; |
||
589 | |||
590 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
||
591 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
||
592 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
||
593 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
||
594 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
||
595 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
||
596 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
||
597 | WREG32(index_reg, 0x0); |
||
598 | WREG32(data_reg, 0x841880A8); |
||
599 | WREG32(index_reg, 0x1); |
||
600 | WREG32(data_reg, 0x84208680); |
||
601 | WREG32(index_reg, 0x2); |
||
602 | WREG32(data_reg, 0xBFF880B0); |
||
603 | WREG32(index_reg, 0x100); |
||
604 | WREG32(data_reg, 0x83D88088); |
||
605 | WREG32(index_reg, 0x101); |
||
606 | WREG32(data_reg, 0x84608680); |
||
607 | WREG32(index_reg, 0x102); |
||
608 | WREG32(data_reg, 0xBFF080D0); |
||
609 | WREG32(index_reg, 0x200); |
||
610 | WREG32(data_reg, 0x83988068); |
||
611 | WREG32(index_reg, 0x201); |
||
612 | WREG32(data_reg, 0x84A08680); |
||
613 | WREG32(index_reg, 0x202); |
||
614 | WREG32(data_reg, 0xBFF080F8); |
||
615 | WREG32(index_reg, 0x300); |
||
616 | WREG32(data_reg, 0x83588058); |
||
617 | WREG32(index_reg, 0x301); |
||
618 | WREG32(data_reg, 0x84E08660); |
||
619 | WREG32(index_reg, 0x302); |
||
620 | WREG32(data_reg, 0xBFF88120); |
||
621 | WREG32(index_reg, 0x400); |
||
622 | WREG32(data_reg, 0x83188040); |
||
623 | WREG32(index_reg, 0x401); |
||
624 | WREG32(data_reg, 0x85008660); |
||
625 | WREG32(index_reg, 0x402); |
||
626 | WREG32(data_reg, 0xBFF88150); |
||
627 | WREG32(index_reg, 0x500); |
||
628 | WREG32(data_reg, 0x82D88030); |
||
629 | WREG32(index_reg, 0x501); |
||
630 | WREG32(data_reg, 0x85408640); |
||
631 | WREG32(index_reg, 0x502); |
||
632 | WREG32(data_reg, 0xBFF88180); |
||
633 | WREG32(index_reg, 0x600); |
||
634 | WREG32(data_reg, 0x82A08018); |
||
635 | WREG32(index_reg, 0x601); |
||
636 | WREG32(data_reg, 0x85808620); |
||
637 | WREG32(index_reg, 0x602); |
||
638 | WREG32(data_reg, 0xBFF081B8); |
||
639 | WREG32(index_reg, 0x700); |
||
640 | WREG32(data_reg, 0x82608010); |
||
641 | WREG32(index_reg, 0x701); |
||
642 | WREG32(data_reg, 0x85A08600); |
||
643 | WREG32(index_reg, 0x702); |
||
644 | WREG32(data_reg, 0x800081F0); |
||
645 | WREG32(index_reg, 0x800); |
||
646 | WREG32(data_reg, 0x8228BFF8); |
||
647 | WREG32(index_reg, 0x801); |
||
648 | WREG32(data_reg, 0x85E085E0); |
||
649 | WREG32(index_reg, 0x802); |
||
650 | WREG32(data_reg, 0xBFF88228); |
||
651 | WREG32(index_reg, 0x10000); |
||
652 | WREG32(data_reg, 0x82A8BF00); |
||
653 | WREG32(index_reg, 0x10001); |
||
654 | WREG32(data_reg, 0x82A08CC0); |
||
655 | WREG32(index_reg, 0x10002); |
||
656 | WREG32(data_reg, 0x8008BEF8); |
||
657 | WREG32(index_reg, 0x10100); |
||
658 | WREG32(data_reg, 0x81F0BF28); |
||
659 | WREG32(index_reg, 0x10101); |
||
660 | WREG32(data_reg, 0x83608CA0); |
||
661 | WREG32(index_reg, 0x10102); |
||
662 | WREG32(data_reg, 0x8018BED0); |
||
663 | WREG32(index_reg, 0x10200); |
||
664 | WREG32(data_reg, 0x8148BF38); |
||
665 | WREG32(index_reg, 0x10201); |
||
666 | WREG32(data_reg, 0x84408C80); |
||
667 | WREG32(index_reg, 0x10202); |
||
668 | WREG32(data_reg, 0x8008BEB8); |
||
669 | WREG32(index_reg, 0x10300); |
||
670 | WREG32(data_reg, 0x80B0BF78); |
||
671 | WREG32(index_reg, 0x10301); |
||
672 | WREG32(data_reg, 0x85008C20); |
||
673 | WREG32(index_reg, 0x10302); |
||
674 | WREG32(data_reg, 0x8020BEA0); |
||
675 | WREG32(index_reg, 0x10400); |
||
676 | WREG32(data_reg, 0x8028BF90); |
||
677 | WREG32(index_reg, 0x10401); |
||
678 | WREG32(data_reg, 0x85E08BC0); |
||
679 | WREG32(index_reg, 0x10402); |
||
680 | WREG32(data_reg, 0x8018BE90); |
||
681 | WREG32(index_reg, 0x10500); |
||
682 | WREG32(data_reg, 0xBFB8BFB0); |
||
683 | WREG32(index_reg, 0x10501); |
||
684 | WREG32(data_reg, 0x86C08B40); |
||
685 | WREG32(index_reg, 0x10502); |
||
686 | WREG32(data_reg, 0x8010BE90); |
||
687 | WREG32(index_reg, 0x10600); |
||
688 | WREG32(data_reg, 0xBF58BFC8); |
||
689 | WREG32(index_reg, 0x10601); |
||
690 | WREG32(data_reg, 0x87A08AA0); |
||
691 | WREG32(index_reg, 0x10602); |
||
692 | WREG32(data_reg, 0x8010BE98); |
||
693 | WREG32(index_reg, 0x10700); |
||
694 | WREG32(data_reg, 0xBF10BFF0); |
||
695 | WREG32(index_reg, 0x10701); |
||
696 | WREG32(data_reg, 0x886089E0); |
||
697 | WREG32(index_reg, 0x10702); |
||
698 | WREG32(data_reg, 0x8018BEB0); |
||
699 | WREG32(index_reg, 0x10800); |
||
700 | WREG32(data_reg, 0xBED8BFE8); |
||
701 | WREG32(index_reg, 0x10801); |
||
702 | WREG32(data_reg, 0x89408940); |
||
703 | WREG32(index_reg, 0x10802); |
||
704 | WREG32(data_reg, 0xBFE8BED8); |
||
705 | WREG32(index_reg, 0x20000); |
||
706 | WREG32(data_reg, 0x80008000); |
||
707 | WREG32(index_reg, 0x20001); |
||
708 | WREG32(data_reg, 0x90008000); |
||
709 | WREG32(index_reg, 0x20002); |
||
710 | WREG32(data_reg, 0x80008000); |
||
711 | WREG32(index_reg, 0x20003); |
||
712 | WREG32(data_reg, 0x80008000); |
||
713 | WREG32(index_reg, 0x20100); |
||
714 | WREG32(data_reg, 0x80108000); |
||
715 | WREG32(index_reg, 0x20101); |
||
716 | WREG32(data_reg, 0x8FE0BF70); |
||
717 | WREG32(index_reg, 0x20102); |
||
718 | WREG32(data_reg, 0xBFE880C0); |
||
719 | WREG32(index_reg, 0x20103); |
||
720 | WREG32(data_reg, 0x80008000); |
||
721 | WREG32(index_reg, 0x20200); |
||
722 | WREG32(data_reg, 0x8018BFF8); |
||
723 | WREG32(index_reg, 0x20201); |
||
724 | WREG32(data_reg, 0x8F80BF08); |
||
725 | WREG32(index_reg, 0x20202); |
||
726 | WREG32(data_reg, 0xBFD081A0); |
||
727 | WREG32(index_reg, 0x20203); |
||
728 | WREG32(data_reg, 0xBFF88000); |
||
729 | WREG32(index_reg, 0x20300); |
||
730 | WREG32(data_reg, 0x80188000); |
||
731 | WREG32(index_reg, 0x20301); |
||
732 | WREG32(data_reg, 0x8EE0BEC0); |
||
733 | WREG32(index_reg, 0x20302); |
||
734 | WREG32(data_reg, 0xBFB082A0); |
||
735 | WREG32(index_reg, 0x20303); |
||
736 | WREG32(data_reg, 0x80008000); |
||
737 | WREG32(index_reg, 0x20400); |
||
738 | WREG32(data_reg, 0x80188000); |
||
739 | WREG32(index_reg, 0x20401); |
||
740 | WREG32(data_reg, 0x8E00BEA0); |
||
741 | WREG32(index_reg, 0x20402); |
||
742 | WREG32(data_reg, 0xBF8883C0); |
||
743 | WREG32(index_reg, 0x20403); |
||
744 | WREG32(data_reg, 0x80008000); |
||
745 | WREG32(index_reg, 0x20500); |
||
746 | WREG32(data_reg, 0x80188000); |
||
747 | WREG32(index_reg, 0x20501); |
||
748 | WREG32(data_reg, 0x8D00BE90); |
||
749 | WREG32(index_reg, 0x20502); |
||
750 | WREG32(data_reg, 0xBF588500); |
||
751 | WREG32(index_reg, 0x20503); |
||
752 | WREG32(data_reg, 0x80008008); |
||
753 | WREG32(index_reg, 0x20600); |
||
754 | WREG32(data_reg, 0x80188000); |
||
755 | WREG32(index_reg, 0x20601); |
||
756 | WREG32(data_reg, 0x8BC0BE98); |
||
757 | WREG32(index_reg, 0x20602); |
||
758 | WREG32(data_reg, 0xBF308660); |
||
759 | WREG32(index_reg, 0x20603); |
||
760 | WREG32(data_reg, 0x80008008); |
||
761 | WREG32(index_reg, 0x20700); |
||
762 | WREG32(data_reg, 0x80108000); |
||
763 | WREG32(index_reg, 0x20701); |
||
764 | WREG32(data_reg, 0x8A80BEB0); |
||
765 | WREG32(index_reg, 0x20702); |
||
766 | WREG32(data_reg, 0xBF0087C0); |
||
767 | WREG32(index_reg, 0x20703); |
||
768 | WREG32(data_reg, 0x80008008); |
||
769 | WREG32(index_reg, 0x20800); |
||
770 | WREG32(data_reg, 0x80108000); |
||
771 | WREG32(index_reg, 0x20801); |
||
772 | WREG32(data_reg, 0x8920BED0); |
||
773 | WREG32(index_reg, 0x20802); |
||
774 | WREG32(data_reg, 0xBED08920); |
||
775 | WREG32(index_reg, 0x20803); |
||
776 | WREG32(data_reg, 0x80008010); |
||
777 | WREG32(index_reg, 0x30000); |
||
778 | WREG32(data_reg, 0x90008000); |
||
779 | WREG32(index_reg, 0x30001); |
||
780 | WREG32(data_reg, 0x80008000); |
||
781 | WREG32(index_reg, 0x30100); |
||
782 | WREG32(data_reg, 0x8FE0BF90); |
||
783 | WREG32(index_reg, 0x30101); |
||
784 | WREG32(data_reg, 0xBFF880A0); |
||
785 | WREG32(index_reg, 0x30200); |
||
786 | WREG32(data_reg, 0x8F60BF40); |
||
787 | WREG32(index_reg, 0x30201); |
||
788 | WREG32(data_reg, 0xBFE88180); |
||
789 | WREG32(index_reg, 0x30300); |
||
790 | WREG32(data_reg, 0x8EC0BF00); |
||
791 | WREG32(index_reg, 0x30301); |
||
792 | WREG32(data_reg, 0xBFC88280); |
||
793 | WREG32(index_reg, 0x30400); |
||
794 | WREG32(data_reg, 0x8DE0BEE0); |
||
795 | WREG32(index_reg, 0x30401); |
||
796 | WREG32(data_reg, 0xBFA083A0); |
||
797 | WREG32(index_reg, 0x30500); |
||
798 | WREG32(data_reg, 0x8CE0BED0); |
||
799 | WREG32(index_reg, 0x30501); |
||
800 | WREG32(data_reg, 0xBF7884E0); |
||
801 | WREG32(index_reg, 0x30600); |
||
802 | WREG32(data_reg, 0x8BA0BED8); |
||
803 | WREG32(index_reg, 0x30601); |
||
804 | WREG32(data_reg, 0xBF508640); |
||
805 | WREG32(index_reg, 0x30700); |
||
806 | WREG32(data_reg, 0x8A60BEE8); |
||
807 | WREG32(index_reg, 0x30701); |
||
808 | WREG32(data_reg, 0xBF2087A0); |
||
809 | WREG32(index_reg, 0x30800); |
||
810 | WREG32(data_reg, 0x8900BF00); |
||
811 | WREG32(index_reg, 0x30801); |
||
812 | WREG32(data_reg, 0xBF008900); |
||
813 | } |
||
814 | |||
815 | struct rv515_watermark { |
||
816 | u32 lb_request_fifo_depth; |
||
817 | fixed20_12 num_line_pair; |
||
818 | fixed20_12 estimated_width; |
||
819 | fixed20_12 worst_case_latency; |
||
820 | fixed20_12 consumption_rate; |
||
821 | fixed20_12 active_time; |
||
822 | fixed20_12 dbpp; |
||
823 | fixed20_12 priority_mark_max; |
||
824 | fixed20_12 priority_mark; |
||
825 | fixed20_12 sclk; |
||
1117 | serge | 826 | }; |
827 | |||
1179 | serge | 828 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
829 | struct radeon_crtc *crtc, |
||
830 | struct rv515_watermark *wm) |
||
831 | { |
||
832 | struct drm_display_mode *mode = &crtc->base.mode; |
||
833 | fixed20_12 a, b, c; |
||
834 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
||
835 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
||
1117 | serge | 836 | |
1179 | serge | 837 | if (!crtc->base.enabled) { |
838 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
||
839 | wm->lb_request_fifo_depth = 4; |
||
840 | return; |
||
841 | } |
||
1117 | serge | 842 | |
1179 | serge | 843 | if (crtc->vsc.full > rfixed_const(2)) |
844 | wm->num_line_pair.full = rfixed_const(2); |
||
845 | else |
||
846 | wm->num_line_pair.full = rfixed_const(1); |
||
847 | |||
848 | b.full = rfixed_const(mode->crtc_hdisplay); |
||
849 | c.full = rfixed_const(256); |
||
1403 | serge | 850 | a.full = rfixed_div(b, c); |
851 | request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); |
||
852 | request_fifo_depth.full = rfixed_ceil(request_fifo_depth); |
||
1179 | serge | 853 | if (a.full < rfixed_const(4)) { |
854 | wm->lb_request_fifo_depth = 4; |
||
855 | } else { |
||
856 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
||
857 | } |
||
858 | |||
859 | /* Determine consumption rate |
||
860 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
||
861 | * vtaps = number of vertical taps, |
||
862 | * vsc = vertical scaling ratio, defined as source/destination |
||
863 | * hsc = horizontal scaling ration, defined as source/destination |
||
864 | */ |
||
865 | a.full = rfixed_const(mode->clock); |
||
866 | b.full = rfixed_const(1000); |
||
867 | a.full = rfixed_div(a, b); |
||
868 | pclk.full = rfixed_div(b, a); |
||
869 | if (crtc->rmx_type != RMX_OFF) { |
||
870 | b.full = rfixed_const(2); |
||
871 | if (crtc->vsc.full > b.full) |
||
872 | b.full = crtc->vsc.full; |
||
873 | b.full = rfixed_mul(b, crtc->hsc); |
||
874 | c.full = rfixed_const(2); |
||
875 | b.full = rfixed_div(b, c); |
||
876 | consumption_time.full = rfixed_div(pclk, b); |
||
877 | } else { |
||
878 | consumption_time.full = pclk.full; |
||
879 | } |
||
880 | a.full = rfixed_const(1); |
||
881 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
||
882 | |||
883 | |||
884 | /* Determine line time |
||
885 | * LineTime = total time for one line of displayhtotal |
||
886 | * LineTime = total number of horizontal pixels |
||
887 | * pclk = pixel clock period(ns) |
||
888 | */ |
||
889 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
||
890 | line_time.full = rfixed_mul(a, pclk); |
||
891 | |||
892 | /* Determine active time |
||
893 | * ActiveTime = time of active region of display within one line, |
||
894 | * hactive = total number of horizontal active pixels |
||
895 | * htotal = total number of horizontal pixels |
||
896 | */ |
||
897 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
||
898 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
||
899 | wm->active_time.full = rfixed_mul(line_time, b); |
||
900 | wm->active_time.full = rfixed_div(wm->active_time, a); |
||
901 | |||
902 | /* Determine chunk time |
||
903 | * ChunkTime = the time it takes the DCP to send one chunk of data |
||
904 | * to the LB which consists of pipeline delay and inter chunk gap |
||
905 | * sclk = system clock(Mhz) |
||
906 | */ |
||
907 | a.full = rfixed_const(600 * 1000); |
||
908 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); |
||
909 | read_delay_latency.full = rfixed_const(1000); |
||
910 | |||
911 | /* Determine the worst case latency |
||
912 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
||
913 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
||
914 | * to return data |
||
915 | * READ_DELAY_IDLE_MAX = constant of 1us |
||
916 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
||
917 | * which consists of pipeline delay and inter chunk gap |
||
918 | */ |
||
919 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
||
920 | a.full = rfixed_const(3); |
||
921 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
||
922 | wm->worst_case_latency.full += read_delay_latency.full; |
||
923 | } else { |
||
924 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
||
925 | } |
||
926 | |||
927 | /* Determine the tolerable latency |
||
928 | * TolerableLatency = Any given request has only 1 line time |
||
929 | * for the data to be returned |
||
930 | * LBRequestFifoDepth = Number of chunk requests the LB can |
||
931 | * put into the request FIFO for a display |
||
932 | * LineTime = total time for one line of display |
||
933 | * ChunkTime = the time it takes the DCP to send one chunk |
||
934 | * of data to the LB which consists of |
||
935 | * pipeline delay and inter chunk gap |
||
936 | */ |
||
937 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
||
938 | tolerable_latency.full = line_time.full; |
||
939 | } else { |
||
940 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
||
941 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
||
942 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
||
943 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
||
944 | } |
||
945 | /* We assume worst case 32bits (4 bytes) */ |
||
946 | wm->dbpp.full = rfixed_const(2 * 16); |
||
947 | |||
948 | /* Determine the maximum priority mark |
||
949 | * width = viewport width in pixels |
||
950 | */ |
||
951 | a.full = rfixed_const(16); |
||
952 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
||
953 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
||
1403 | serge | 954 | wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); |
1179 | serge | 955 | |
956 | /* Determine estimated width */ |
||
957 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
958 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
||
959 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
1403 | serge | 960 | wm->priority_mark.full = wm->priority_mark_max.full; |
1179 | serge | 961 | } else { |
962 | a.full = rfixed_const(16); |
||
963 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
||
1403 | serge | 964 | wm->priority_mark.full = rfixed_ceil(wm->priority_mark); |
1179 | serge | 965 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
966 | } |
||
967 | } |
||
968 | |||
969 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
||
1117 | serge | 970 | { |
1179 | serge | 971 | struct drm_display_mode *mode0 = NULL; |
972 | struct drm_display_mode *mode1 = NULL; |
||
973 | struct rv515_watermark wm0; |
||
974 | struct rv515_watermark wm1; |
||
975 | u32 tmp; |
||
976 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
||
977 | fixed20_12 a, b; |
||
1117 | serge | 978 | |
1179 | serge | 979 | if (rdev->mode_info.crtcs[0]->base.enabled) |
980 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
981 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
982 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
983 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
984 | |||
985 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
986 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
987 | |||
988 | tmp = wm0.lb_request_fifo_depth; |
||
989 | tmp |= wm1.lb_request_fifo_depth << 16; |
||
990 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
||
991 | |||
992 | if (mode0 && mode1) { |
||
993 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
994 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
995 | else |
||
996 | a.full = wm0.num_line_pair.full; |
||
997 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
998 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
999 | else |
||
1000 | b.full = wm1.num_line_pair.full; |
||
1001 | a.full += b.full; |
||
1002 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
1003 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
1004 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1005 | b.full = rfixed_mul(b, wm0.active_time); |
||
1006 | a.full = rfixed_const(16); |
||
1007 | b.full = rfixed_div(b, a); |
||
1008 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
1009 | wm0.consumption_rate); |
||
1010 | priority_mark02.full = a.full + b.full; |
||
1011 | } else { |
||
1012 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
1013 | wm0.consumption_rate); |
||
1014 | b.full = rfixed_const(16 * 1000); |
||
1015 | priority_mark02.full = rfixed_div(a, b); |
||
1016 | } |
||
1017 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
1018 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1019 | b.full = rfixed_mul(b, wm1.active_time); |
||
1020 | a.full = rfixed_const(16); |
||
1021 | b.full = rfixed_div(b, a); |
||
1022 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
1023 | wm1.consumption_rate); |
||
1024 | priority_mark12.full = a.full + b.full; |
||
1025 | } else { |
||
1026 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
1027 | wm1.consumption_rate); |
||
1028 | b.full = rfixed_const(16 * 1000); |
||
1029 | priority_mark12.full = rfixed_div(a, b); |
||
1030 | } |
||
1031 | if (wm0.priority_mark.full > priority_mark02.full) |
||
1032 | priority_mark02.full = wm0.priority_mark.full; |
||
1033 | if (rfixed_trunc(priority_mark02) < 0) |
||
1034 | priority_mark02.full = 0; |
||
1035 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
1036 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1037 | if (wm1.priority_mark.full > priority_mark12.full) |
||
1038 | priority_mark12.full = wm1.priority_mark.full; |
||
1039 | if (rfixed_trunc(priority_mark12) < 0) |
||
1040 | priority_mark12.full = 0; |
||
1041 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
1042 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1043 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
1044 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
1045 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
1046 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
1047 | } else if (mode0) { |
||
1048 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
1049 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
||
1050 | else |
||
1051 | a.full = wm0.num_line_pair.full; |
||
1052 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
1053 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
1054 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1055 | b.full = rfixed_mul(b, wm0.active_time); |
||
1056 | a.full = rfixed_const(16); |
||
1057 | b.full = rfixed_div(b, a); |
||
1058 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
1059 | wm0.consumption_rate); |
||
1060 | priority_mark02.full = a.full + b.full; |
||
1061 | } else { |
||
1062 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
1063 | wm0.consumption_rate); |
||
1064 | b.full = rfixed_const(16); |
||
1065 | priority_mark02.full = rfixed_div(a, b); |
||
1066 | } |
||
1067 | if (wm0.priority_mark.full > priority_mark02.full) |
||
1068 | priority_mark02.full = wm0.priority_mark.full; |
||
1069 | if (rfixed_trunc(priority_mark02) < 0) |
||
1070 | priority_mark02.full = 0; |
||
1071 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
1072 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1073 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
||
1074 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
1075 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
1076 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
1077 | } else { |
||
1078 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
1079 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
||
1080 | else |
||
1081 | a.full = wm1.num_line_pair.full; |
||
1082 | fill_rate.full = rfixed_div(wm1.sclk, a); |
||
1083 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
1084 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1085 | b.full = rfixed_mul(b, wm1.active_time); |
||
1086 | a.full = rfixed_const(16); |
||
1087 | b.full = rfixed_div(b, a); |
||
1088 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
1089 | wm1.consumption_rate); |
||
1090 | priority_mark12.full = a.full + b.full; |
||
1091 | } else { |
||
1092 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
1093 | wm1.consumption_rate); |
||
1094 | b.full = rfixed_const(16 * 1000); |
||
1095 | priority_mark12.full = rfixed_div(a, b); |
||
1096 | } |
||
1097 | if (wm1.priority_mark.full > priority_mark12.full) |
||
1098 | priority_mark12.full = wm1.priority_mark.full; |
||
1099 | if (rfixed_trunc(priority_mark12) < 0) |
||
1100 | priority_mark12.full = 0; |
||
1101 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
1102 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1103 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
||
1104 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
||
1105 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
1106 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
1107 | } |
||
1117 | serge | 1108 | } |
1179 | serge | 1109 | |
1110 | void rv515_bandwidth_update(struct radeon_device *rdev) |
||
1111 | { |
||
1112 | uint32_t tmp; |
||
1113 | struct drm_display_mode *mode0 = NULL; |
||
1114 | struct drm_display_mode *mode1 = NULL; |
||
1115 | |||
1116 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
1117 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
1118 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
1119 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
1120 | /* |
||
1121 | * Set display0/1 priority up in the memory controller for |
||
1122 | * modes if the user specifies HIGH for displaypriority |
||
1123 | * option. |
||
1124 | */ |
||
1125 | if (rdev->disp_priority == 2) { |
||
1126 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
||
1127 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
||
1128 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
||
1129 | if (mode1) |
||
1130 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
||
1131 | if (mode0) |
||
1132 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
||
1133 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
||
1134 | } |
||
1135 | rv515_bandwidth_avivo_update(rdev); |
||
1136 | }><>><>>>>>><>>><>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |