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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
1179 serge 28
#include 
1125 serge 29
#include "drmP.h"
1179 serge 30
#include "rv515d.h"
1117 serge 31
#include "radeon.h"
1221 serge 32
#include "atom.h"
1179 serge 33
#include "rv515_reg_safe.h"
1117 serge 34
 
1221 serge 35
/* This files gather functions specifics to: rv515 */
1117 serge 36
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37
int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38
void rv515_gpu_init(struct radeon_device *rdev);
39
int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40
 
1221 serge 41
void rv515_debugfs(struct radeon_device *rdev)
1117 serge 42
{
1129 serge 43
	if (r100_debugfs_rbbm_init(rdev)) {
44
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
45
	}
46
	if (rv515_debugfs_pipes_info_init(rdev)) {
47
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
48
	}
49
	if (rv515_debugfs_ga_info_init(rdev)) {
50
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
51
	}
1117 serge 52
}
53
 
54
void rv515_ring_start(struct radeon_device *rdev)
55
{
56
	int r;
57
 
1179 serge 58
    ENTER();
1117 serge 59
 
60
	r = radeon_ring_lock(rdev, 64);
61
	if (r) {
62
		return;
63
	}
1179 serge 64
	radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
1117 serge 65
	radeon_ring_write(rdev,
1179 serge 66
			  ISYNC_ANY2D_IDLE3D |
67
			  ISYNC_ANY3D_IDLE2D |
68
			  ISYNC_WAIT_IDLEGUI |
69
			  ISYNC_CPSCRATCH_IDLEGUI);
70
	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71
	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
1117 serge 72
	radeon_ring_write(rdev, PACKET0(0x170C, 0));
73
	radeon_ring_write(rdev, 1 << 31);
1179 serge 74
	radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
1117 serge 75
	radeon_ring_write(rdev, 0);
1179 serge 76
	radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
1117 serge 77
	radeon_ring_write(rdev, 0);
78
	radeon_ring_write(rdev, PACKET0(0x42C8, 0));
79
	radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
1179 serge 80
	radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
1117 serge 81
	radeon_ring_write(rdev, 0);
1179 serge 82
	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83
	radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
84
	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85
	radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
86
	radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87
	radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88
	radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
1117 serge 89
	radeon_ring_write(rdev, 0);
1179 serge 90
	radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91
	radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
92
	radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93
	radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
94
	radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
1117 serge 95
	radeon_ring_write(rdev,
1179 serge 96
			  ((6 << MS_X0_SHIFT) |
97
			   (6 << MS_Y0_SHIFT) |
98
			   (6 << MS_X1_SHIFT) |
99
			   (6 << MS_Y1_SHIFT) |
100
			   (6 << MS_X2_SHIFT) |
101
			   (6 << MS_Y2_SHIFT) |
102
			   (6 << MSBD0_Y_SHIFT) |
103
			   (6 << MSBD0_X_SHIFT)));
104
	radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
1117 serge 105
	radeon_ring_write(rdev,
1179 serge 106
			  ((6 << MS_X3_SHIFT) |
107
			   (6 << MS_Y3_SHIFT) |
108
			   (6 << MS_X4_SHIFT) |
109
			   (6 << MS_Y4_SHIFT) |
110
			   (6 << MS_X5_SHIFT) |
111
			   (6 << MS_Y5_SHIFT) |
112
			   (6 << MSBD1_SHIFT)));
113
	radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114
	radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115
	radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116
	radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117
	radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118
	radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
1117 serge 119
	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120
	radeon_ring_write(rdev, 0);
121
	radeon_ring_unlock_commit(rdev);
1119 serge 122
 
1179 serge 123
    LEAVE();
1119 serge 124
 
1117 serge 125
}
126
 
127
int rv515_mc_wait_for_idle(struct radeon_device *rdev)
128
{
129
	unsigned i;
130
	uint32_t tmp;
131
 
132
	for (i = 0; i < rdev->usec_timeout; i++) {
133
		/* read MC_STATUS */
1179 serge 134
		tmp = RREG32_MC(MC_STATUS);
135
		if (tmp & MC_STATUS_IDLE) {
1117 serge 136
			return 0;
137
		}
138
		DRM_UDELAY(1);
139
	}
140
	return -1;
141
}
142
 
1221 serge 143
void rv515_vga_render_disable(struct radeon_device *rdev)
144
{
145
	WREG32(R_000300_VGA_RENDER_CONTROL,
146
		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
147
}
148
 
1117 serge 149
void rv515_gpu_init(struct radeon_device *rdev)
150
{
151
	unsigned pipe_select_current, gb_pipe_select, tmp;
152
 
153
	r100_hdp_reset(rdev);
154
	r100_rb2d_reset(rdev);
155
 
156
	if (r100_gui_wait_for_idle(rdev)) {
157
		printk(KERN_WARNING "Failed to wait GUI idle while "
158
		       "reseting GPU. Bad things might happen.\n");
159
	}
160
 
1221 serge 161
	rv515_vga_render_disable(rdev);
1117 serge 162
 
163
	r420_pipes_init(rdev);
164
	gb_pipe_select = RREG32(0x402C);
165
	tmp = RREG32(0x170C);
166
	pipe_select_current = (tmp >> 2) & 3;
167
	tmp = (1 << pipe_select_current) |
168
	      (((gb_pipe_select >> 8) & 0xF) << 4);
169
	WREG32_PLL(0x000D, tmp);
170
	if (r100_gui_wait_for_idle(rdev)) {
171
		printk(KERN_WARNING "Failed to wait GUI idle while "
172
		       "reseting GPU. Bad things might happen.\n");
173
	}
174
	if (rv515_mc_wait_for_idle(rdev)) {
175
		printk(KERN_WARNING "Failed to wait MC idle while "
176
		       "programming pipes. Bad things might happen.\n");
177
	}
178
}
179
 
180
int rv515_ga_reset(struct radeon_device *rdev)
181
{
182
	uint32_t tmp;
183
	bool reinit_cp;
184
	int i;
185
 
1179 serge 186
    ENTER();
1117 serge 187
 
188
	reinit_cp = rdev->cp.ready;
189
	rdev->cp.ready = false;
190
	for (i = 0; i < rdev->usec_timeout; i++) {
1179 serge 191
		WREG32(CP_CSQ_MODE, 0);
192
		WREG32(CP_CSQ_CNTL, 0);
193
		WREG32(RBBM_SOFT_RESET, 0x32005);
194
		(void)RREG32(RBBM_SOFT_RESET);
1117 serge 195
		udelay(200);
1179 serge 196
		WREG32(RBBM_SOFT_RESET, 0);
1117 serge 197
		/* Wait to prevent race in RBBM_STATUS */
198
		mdelay(1);
1179 serge 199
		tmp = RREG32(RBBM_STATUS);
1117 serge 200
		if (tmp & ((1 << 20) | (1 << 26))) {
201
			DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
202
			/* GA still busy soft reset it */
203
			WREG32(0x429C, 0x200);
1179 serge 204
			WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
1117 serge 205
			WREG32(0x43E0, 0);
206
			WREG32(0x43E4, 0);
207
			WREG32(0x24AC, 0);
208
		}
209
		/* Wait to prevent race in RBBM_STATUS */
210
		mdelay(1);
1179 serge 211
		tmp = RREG32(RBBM_STATUS);
1117 serge 212
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
213
			break;
214
		}
215
	}
216
	for (i = 0; i < rdev->usec_timeout; i++) {
1179 serge 217
		tmp = RREG32(RBBM_STATUS);
1117 serge 218
		if (!(tmp & ((1 << 20) | (1 << 26)))) {
219
			DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
220
				 tmp);
221
			DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
222
			DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
223
			DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
224
			if (reinit_cp) {
225
				return r100_cp_init(rdev, rdev->cp.ring_size);
226
			}
227
			return 0;
228
		}
229
		DRM_UDELAY(1);
230
	}
1179 serge 231
	tmp = RREG32(RBBM_STATUS);
1117 serge 232
	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
233
	return -1;
234
}
235
 
236
int rv515_gpu_reset(struct radeon_device *rdev)
237
{
238
	uint32_t status;
239
 
1179 serge 240
    ENTER();
1117 serge 241
 
242
	/* reset order likely matter */
1179 serge 243
	status = RREG32(RBBM_STATUS);
1117 serge 244
	/* reset HDP */
245
	r100_hdp_reset(rdev);
246
	/* reset rb2d */
247
	if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
248
		r100_rb2d_reset(rdev);
249
	}
250
	/* reset GA */
251
	if (status & ((1 << 20) | (1 << 26))) {
252
		rv515_ga_reset(rdev);
253
	}
254
	/* reset CP */
1179 serge 255
	status = RREG32(RBBM_STATUS);
1117 serge 256
	if (status & (1 << 16)) {
257
		r100_cp_reset(rdev);
258
	}
259
	/* Check if GPU is idle */
1179 serge 260
	status = RREG32(RBBM_STATUS);
1117 serge 261
	if (status & (1 << 31)) {
262
		DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
263
		return -1;
264
	}
265
	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
266
	return 0;
267
}
268
 
269
static void rv515_vram_get_type(struct radeon_device *rdev)
270
{
271
	uint32_t tmp;
272
 
273
	rdev->mc.vram_width = 128;
274
	rdev->mc.vram_is_ddr = true;
1179 serge 275
	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
1117 serge 276
	switch (tmp) {
277
	case 0:
278
		rdev->mc.vram_width = 64;
279
		break;
280
	case 1:
281
		rdev->mc.vram_width = 128;
282
		break;
283
	default:
284
		rdev->mc.vram_width = 128;
285
		break;
286
	}
287
}
288
 
289
void rv515_vram_info(struct radeon_device *rdev)
290
{
1179 serge 291
	fixed20_12 a;
292
 
1117 serge 293
	rv515_vram_get_type(rdev);
294
 
1179 serge 295
	r100_vram_init_sizes(rdev);
296
	/* FIXME: we should enforce default clock in case GPU is not in
297
	 * default setup
298
	 */
299
	a.full = rfixed_const(100);
300
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
301
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
1117 serge 302
}
303
 
304
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
305
{
306
	uint32_t r;
307
 
1179 serge 308
	WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
309
	r = RREG32(MC_IND_DATA);
310
	WREG32(MC_IND_INDEX, 0);
1117 serge 311
	return r;
312
}
313
 
314
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
315
{
1179 serge 316
	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
317
	WREG32(MC_IND_DATA, (v));
318
	WREG32(MC_IND_INDEX, 0);
1117 serge 319
}
320
 
321
#if defined(CONFIG_DEBUG_FS)
322
static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
323
{
324
	struct drm_info_node *node = (struct drm_info_node *) m->private;
325
	struct drm_device *dev = node->minor->dev;
326
	struct radeon_device *rdev = dev->dev_private;
327
	uint32_t tmp;
328
 
1179 serge 329
	tmp = RREG32(GB_PIPE_SELECT);
1117 serge 330
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
1179 serge 331
	tmp = RREG32(SU_REG_DEST);
1117 serge 332
	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
1179 serge 333
	tmp = RREG32(GB_TILE_CONFIG);
1117 serge 334
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
1179 serge 335
	tmp = RREG32(DST_PIPE_CONFIG);
1117 serge 336
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
337
	return 0;
338
}
339
 
340
static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
341
{
342
	struct drm_info_node *node = (struct drm_info_node *) m->private;
343
	struct drm_device *dev = node->minor->dev;
344
	struct radeon_device *rdev = dev->dev_private;
345
	uint32_t tmp;
346
 
347
	tmp = RREG32(0x2140);
348
	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
349
	radeon_gpu_reset(rdev);
350
	tmp = RREG32(0x425C);
351
	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
352
	return 0;
353
}
354
 
355
static struct drm_info_list rv515_pipes_info_list[] = {
356
	{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
357
};
358
 
359
static struct drm_info_list rv515_ga_info_list[] = {
360
	{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
361
};
362
#endif
363
 
364
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
365
{
366
#if defined(CONFIG_DEBUG_FS)
367
	return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
368
#else
369
	return 0;
370
#endif
371
}
372
 
373
int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
374
{
375
#if defined(CONFIG_DEBUG_FS)
376
	return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
377
#else
378
	return 0;
379
#endif
380
}
381
 
1221 serge 382
void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
1179 serge 383
{
1221 serge 384
	save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
385
	save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
386
	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
387
	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
388
	save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
389
	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
1179 serge 390
 
1221 serge 391
	/* Stop all video */
392
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
393
	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
394
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
395
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
396
	WREG32(R_006080_D1CRTC_CONTROL, 0);
397
	WREG32(R_006880_D2CRTC_CONTROL, 0);
398
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
399
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
1313 serge 400
	WREG32(R_000330_D1VGA_CONTROL, 0);
401
	WREG32(R_000338_D2VGA_CONTROL, 0);
1221 serge 402
}
403
 
404
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
405
{
406
	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
407
	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
408
	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
409
	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
410
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
411
	/* Unlock host access */
412
	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
413
	mdelay(1);
414
	/* Restore video state */
1313 serge 415
	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
416
	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
1221 serge 417
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
418
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
419
	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
420
	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
421
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
422
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
423
	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
424
}
425
 
426
void rv515_mc_program(struct radeon_device *rdev)
427
{
428
	struct rv515_mc_save save;
429
 
430
	/* Stops all mc clients */
431
	rv515_mc_stop(rdev, &save);
432
 
433
	/* Wait for mc idle */
434
	if (rv515_mc_wait_for_idle(rdev))
435
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
436
	/* Write VRAM size in case we are limiting it */
437
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
438
	/* Program MC, should be a 32bits limited address space */
439
	WREG32_MC(R_000001_MC_FB_LOCATION,
440
			S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
441
			S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
442
	WREG32(R_000134_HDP_FB_LOCATION,
443
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
444
	if (rdev->flags & RADEON_IS_AGP) {
445
		WREG32_MC(R_000002_MC_AGP_LOCATION,
446
			S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
447
			S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
448
		WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
449
		WREG32_MC(R_000004_MC_AGP_BASE_2,
450
			S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
451
	} else {
452
		WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
453
		WREG32_MC(R_000003_MC_AGP_BASE, 0);
454
		WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
455
	}
456
 
457
	rv515_mc_resume(rdev, &save);
458
}
459
 
460
void rv515_clock_startup(struct radeon_device *rdev)
461
{
462
	if (radeon_dynclks != -1 && radeon_dynclks)
463
		radeon_atom_set_clock_gating(rdev, 1);
464
	/* We need to force on some of the block */
465
	WREG32_PLL(R_00000F_CP_DYN_CNTL,
466
		RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
467
	WREG32_PLL(R_000011_E2_DYN_CNTL,
468
		RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
469
	WREG32_PLL(R_000013_IDCT_DYN_CNTL,
470
		RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
471
}
472
 
473
static int rv515_startup(struct radeon_device *rdev)
474
{
475
	int r;
476
 
477
	rv515_mc_program(rdev);
478
	/* Resume clock */
479
	rv515_clock_startup(rdev);
480
	/* Initialize GPU configuration (# pipes, ...) */
481
	rv515_gpu_init(rdev);
482
	/* Initialize GART (initialize after TTM so we can allocate
483
	 * memory through TTM but finalize after TTM) */
484
	if (rdev->flags & RADEON_IS_PCIE) {
485
		r = rv370_pcie_gart_enable(rdev);
486
		if (r)
487
			return r;
488
	}
489
	/* Enable IRQ */
490
//	rdev->irq.sw_int = true;
491
//	rs600_irq_set(rdev);
1403 serge 492
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221 serge 493
	/* 1M ring buffer */
494
//	r = r100_cp_init(rdev, 1024 * 1024);
495
//	if (r) {
496
//		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
497
//		return r;
498
//	}
499
//	r = r100_wb_init(rdev);
500
//	if (r)
501
//		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
502
//	r = r100_ib_init(rdev);
503
//	if (r) {
504
//		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
505
//		return r;
506
//	}
507
	return 0;
508
}
509
 
510
 
511
void rv515_set_safe_registers(struct radeon_device *rdev)
512
{
1179 serge 513
	rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
514
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
1221 serge 515
}
516
 
517
int rv515_init(struct radeon_device *rdev)
518
{
519
	int r;
520
 
521
	/* Initialize scratch registers */
522
	radeon_scratch_init(rdev);
523
	/* Initialize surface registers */
524
	radeon_surface_init(rdev);
525
	/* TODO: disable VGA need to use VGA request */
526
	/* BIOS*/
527
	if (!radeon_get_bios(rdev)) {
528
		if (ASIC_IS_AVIVO(rdev))
529
			return -EINVAL;
530
	}
531
	if (rdev->is_atom_bios) {
532
		r = radeon_atombios_init(rdev);
533
		if (r)
534
			return r;
535
	} else {
536
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
537
		return -EINVAL;
538
	}
539
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
540
	if (radeon_gpu_reset(rdev)) {
541
		dev_warn(rdev->dev,
542
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
543
			RREG32(R_000E40_RBBM_STATUS),
544
			RREG32(R_0007C0_CP_STAT));
545
	}
546
	/* check if cards are posted or not */
1403 serge 547
	if (radeon_boot_test_post_card(rdev) == false)
548
		return -EINVAL;
1221 serge 549
	/* Initialize clocks */
550
	radeon_get_clock_info(rdev->ddev);
1268 serge 551
	/* Initialize power management */
552
	radeon_pm_init(rdev);
1221 serge 553
	/* Get vram informations */
554
	rv515_vram_info(rdev);
555
	/* Initialize memory controller (also test AGP) */
556
	r = r420_mc_init(rdev);
1246 serge 557
    dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221 serge 558
	if (r)
559
		return r;
560
	rv515_debugfs(rdev);
561
	/* Fence driver */
562
//   r = radeon_fence_driver_init(rdev);
563
//   if (r)
564
//       return r;
565
//	r = radeon_irq_kms_init(rdev);
566
//	if (r)
567
//		return r;
568
	/* Memory manager */
1403 serge 569
	r = radeon_bo_init(rdev);
1221 serge 570
	if (r)
571
		return r;
572
	r = rv370_pcie_gart_init(rdev);
573
	if (r)
574
		return r;
575
	rv515_set_safe_registers(rdev);
576
	rdev->accel_working = true;
577
	r = rv515_startup(rdev);
578
	if (r) {
579
		/* Somethings want wront with the accel init stop accel */
580
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
581
//		rv515_suspend(rdev);
582
//		r100_cp_fini(rdev);
583
//		r100_wb_fini(rdev);
584
//		r100_ib_fini(rdev);
585
		rv370_pcie_gart_fini(rdev);
586
//		radeon_agp_fini(rdev);
587
//		radeon_irq_kms_fini(rdev);
588
		rdev->accel_working = false;
589
	}
1179 serge 590
	return 0;
591
}
592
 
593
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
594
{
595
	int index_reg = 0x6578 + crtc->crtc_offset;
596
	int data_reg = 0x657c + crtc->crtc_offset;
597
 
598
	WREG32(0x659C + crtc->crtc_offset, 0x0);
599
	WREG32(0x6594 + crtc->crtc_offset, 0x705);
600
	WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
601
	WREG32(0x65D8 + crtc->crtc_offset, 0x0);
602
	WREG32(0x65B0 + crtc->crtc_offset, 0x0);
603
	WREG32(0x65C0 + crtc->crtc_offset, 0x0);
604
	WREG32(0x65D4 + crtc->crtc_offset, 0x0);
605
	WREG32(index_reg, 0x0);
606
	WREG32(data_reg, 0x841880A8);
607
	WREG32(index_reg, 0x1);
608
	WREG32(data_reg, 0x84208680);
609
	WREG32(index_reg, 0x2);
610
	WREG32(data_reg, 0xBFF880B0);
611
	WREG32(index_reg, 0x100);
612
	WREG32(data_reg, 0x83D88088);
613
	WREG32(index_reg, 0x101);
614
	WREG32(data_reg, 0x84608680);
615
	WREG32(index_reg, 0x102);
616
	WREG32(data_reg, 0xBFF080D0);
617
	WREG32(index_reg, 0x200);
618
	WREG32(data_reg, 0x83988068);
619
	WREG32(index_reg, 0x201);
620
	WREG32(data_reg, 0x84A08680);
621
	WREG32(index_reg, 0x202);
622
	WREG32(data_reg, 0xBFF080F8);
623
	WREG32(index_reg, 0x300);
624
	WREG32(data_reg, 0x83588058);
625
	WREG32(index_reg, 0x301);
626
	WREG32(data_reg, 0x84E08660);
627
	WREG32(index_reg, 0x302);
628
	WREG32(data_reg, 0xBFF88120);
629
	WREG32(index_reg, 0x400);
630
	WREG32(data_reg, 0x83188040);
631
	WREG32(index_reg, 0x401);
632
	WREG32(data_reg, 0x85008660);
633
	WREG32(index_reg, 0x402);
634
	WREG32(data_reg, 0xBFF88150);
635
	WREG32(index_reg, 0x500);
636
	WREG32(data_reg, 0x82D88030);
637
	WREG32(index_reg, 0x501);
638
	WREG32(data_reg, 0x85408640);
639
	WREG32(index_reg, 0x502);
640
	WREG32(data_reg, 0xBFF88180);
641
	WREG32(index_reg, 0x600);
642
	WREG32(data_reg, 0x82A08018);
643
	WREG32(index_reg, 0x601);
644
	WREG32(data_reg, 0x85808620);
645
	WREG32(index_reg, 0x602);
646
	WREG32(data_reg, 0xBFF081B8);
647
	WREG32(index_reg, 0x700);
648
	WREG32(data_reg, 0x82608010);
649
	WREG32(index_reg, 0x701);
650
	WREG32(data_reg, 0x85A08600);
651
	WREG32(index_reg, 0x702);
652
	WREG32(data_reg, 0x800081F0);
653
	WREG32(index_reg, 0x800);
654
	WREG32(data_reg, 0x8228BFF8);
655
	WREG32(index_reg, 0x801);
656
	WREG32(data_reg, 0x85E085E0);
657
	WREG32(index_reg, 0x802);
658
	WREG32(data_reg, 0xBFF88228);
659
	WREG32(index_reg, 0x10000);
660
	WREG32(data_reg, 0x82A8BF00);
661
	WREG32(index_reg, 0x10001);
662
	WREG32(data_reg, 0x82A08CC0);
663
	WREG32(index_reg, 0x10002);
664
	WREG32(data_reg, 0x8008BEF8);
665
	WREG32(index_reg, 0x10100);
666
	WREG32(data_reg, 0x81F0BF28);
667
	WREG32(index_reg, 0x10101);
668
	WREG32(data_reg, 0x83608CA0);
669
	WREG32(index_reg, 0x10102);
670
	WREG32(data_reg, 0x8018BED0);
671
	WREG32(index_reg, 0x10200);
672
	WREG32(data_reg, 0x8148BF38);
673
	WREG32(index_reg, 0x10201);
674
	WREG32(data_reg, 0x84408C80);
675
	WREG32(index_reg, 0x10202);
676
	WREG32(data_reg, 0x8008BEB8);
677
	WREG32(index_reg, 0x10300);
678
	WREG32(data_reg, 0x80B0BF78);
679
	WREG32(index_reg, 0x10301);
680
	WREG32(data_reg, 0x85008C20);
681
	WREG32(index_reg, 0x10302);
682
	WREG32(data_reg, 0x8020BEA0);
683
	WREG32(index_reg, 0x10400);
684
	WREG32(data_reg, 0x8028BF90);
685
	WREG32(index_reg, 0x10401);
686
	WREG32(data_reg, 0x85E08BC0);
687
	WREG32(index_reg, 0x10402);
688
	WREG32(data_reg, 0x8018BE90);
689
	WREG32(index_reg, 0x10500);
690
	WREG32(data_reg, 0xBFB8BFB0);
691
	WREG32(index_reg, 0x10501);
692
	WREG32(data_reg, 0x86C08B40);
693
	WREG32(index_reg, 0x10502);
694
	WREG32(data_reg, 0x8010BE90);
695
	WREG32(index_reg, 0x10600);
696
	WREG32(data_reg, 0xBF58BFC8);
697
	WREG32(index_reg, 0x10601);
698
	WREG32(data_reg, 0x87A08AA0);
699
	WREG32(index_reg, 0x10602);
700
	WREG32(data_reg, 0x8010BE98);
701
	WREG32(index_reg, 0x10700);
702
	WREG32(data_reg, 0xBF10BFF0);
703
	WREG32(index_reg, 0x10701);
704
	WREG32(data_reg, 0x886089E0);
705
	WREG32(index_reg, 0x10702);
706
	WREG32(data_reg, 0x8018BEB0);
707
	WREG32(index_reg, 0x10800);
708
	WREG32(data_reg, 0xBED8BFE8);
709
	WREG32(index_reg, 0x10801);
710
	WREG32(data_reg, 0x89408940);
711
	WREG32(index_reg, 0x10802);
712
	WREG32(data_reg, 0xBFE8BED8);
713
	WREG32(index_reg, 0x20000);
714
	WREG32(data_reg, 0x80008000);
715
	WREG32(index_reg, 0x20001);
716
	WREG32(data_reg, 0x90008000);
717
	WREG32(index_reg, 0x20002);
718
	WREG32(data_reg, 0x80008000);
719
	WREG32(index_reg, 0x20003);
720
	WREG32(data_reg, 0x80008000);
721
	WREG32(index_reg, 0x20100);
722
	WREG32(data_reg, 0x80108000);
723
	WREG32(index_reg, 0x20101);
724
	WREG32(data_reg, 0x8FE0BF70);
725
	WREG32(index_reg, 0x20102);
726
	WREG32(data_reg, 0xBFE880C0);
727
	WREG32(index_reg, 0x20103);
728
	WREG32(data_reg, 0x80008000);
729
	WREG32(index_reg, 0x20200);
730
	WREG32(data_reg, 0x8018BFF8);
731
	WREG32(index_reg, 0x20201);
732
	WREG32(data_reg, 0x8F80BF08);
733
	WREG32(index_reg, 0x20202);
734
	WREG32(data_reg, 0xBFD081A0);
735
	WREG32(index_reg, 0x20203);
736
	WREG32(data_reg, 0xBFF88000);
737
	WREG32(index_reg, 0x20300);
738
	WREG32(data_reg, 0x80188000);
739
	WREG32(index_reg, 0x20301);
740
	WREG32(data_reg, 0x8EE0BEC0);
741
	WREG32(index_reg, 0x20302);
742
	WREG32(data_reg, 0xBFB082A0);
743
	WREG32(index_reg, 0x20303);
744
	WREG32(data_reg, 0x80008000);
745
	WREG32(index_reg, 0x20400);
746
	WREG32(data_reg, 0x80188000);
747
	WREG32(index_reg, 0x20401);
748
	WREG32(data_reg, 0x8E00BEA0);
749
	WREG32(index_reg, 0x20402);
750
	WREG32(data_reg, 0xBF8883C0);
751
	WREG32(index_reg, 0x20403);
752
	WREG32(data_reg, 0x80008000);
753
	WREG32(index_reg, 0x20500);
754
	WREG32(data_reg, 0x80188000);
755
	WREG32(index_reg, 0x20501);
756
	WREG32(data_reg, 0x8D00BE90);
757
	WREG32(index_reg, 0x20502);
758
	WREG32(data_reg, 0xBF588500);
759
	WREG32(index_reg, 0x20503);
760
	WREG32(data_reg, 0x80008008);
761
	WREG32(index_reg, 0x20600);
762
	WREG32(data_reg, 0x80188000);
763
	WREG32(index_reg, 0x20601);
764
	WREG32(data_reg, 0x8BC0BE98);
765
	WREG32(index_reg, 0x20602);
766
	WREG32(data_reg, 0xBF308660);
767
	WREG32(index_reg, 0x20603);
768
	WREG32(data_reg, 0x80008008);
769
	WREG32(index_reg, 0x20700);
770
	WREG32(data_reg, 0x80108000);
771
	WREG32(index_reg, 0x20701);
772
	WREG32(data_reg, 0x8A80BEB0);
773
	WREG32(index_reg, 0x20702);
774
	WREG32(data_reg, 0xBF0087C0);
775
	WREG32(index_reg, 0x20703);
776
	WREG32(data_reg, 0x80008008);
777
	WREG32(index_reg, 0x20800);
778
	WREG32(data_reg, 0x80108000);
779
	WREG32(index_reg, 0x20801);
780
	WREG32(data_reg, 0x8920BED0);
781
	WREG32(index_reg, 0x20802);
782
	WREG32(data_reg, 0xBED08920);
783
	WREG32(index_reg, 0x20803);
784
	WREG32(data_reg, 0x80008010);
785
	WREG32(index_reg, 0x30000);
786
	WREG32(data_reg, 0x90008000);
787
	WREG32(index_reg, 0x30001);
788
	WREG32(data_reg, 0x80008000);
789
	WREG32(index_reg, 0x30100);
790
	WREG32(data_reg, 0x8FE0BF90);
791
	WREG32(index_reg, 0x30101);
792
	WREG32(data_reg, 0xBFF880A0);
793
	WREG32(index_reg, 0x30200);
794
	WREG32(data_reg, 0x8F60BF40);
795
	WREG32(index_reg, 0x30201);
796
	WREG32(data_reg, 0xBFE88180);
797
	WREG32(index_reg, 0x30300);
798
	WREG32(data_reg, 0x8EC0BF00);
799
	WREG32(index_reg, 0x30301);
800
	WREG32(data_reg, 0xBFC88280);
801
	WREG32(index_reg, 0x30400);
802
	WREG32(data_reg, 0x8DE0BEE0);
803
	WREG32(index_reg, 0x30401);
804
	WREG32(data_reg, 0xBFA083A0);
805
	WREG32(index_reg, 0x30500);
806
	WREG32(data_reg, 0x8CE0BED0);
807
	WREG32(index_reg, 0x30501);
808
	WREG32(data_reg, 0xBF7884E0);
809
	WREG32(index_reg, 0x30600);
810
	WREG32(data_reg, 0x8BA0BED8);
811
	WREG32(index_reg, 0x30601);
812
	WREG32(data_reg, 0xBF508640);
813
	WREG32(index_reg, 0x30700);
814
	WREG32(data_reg, 0x8A60BEE8);
815
	WREG32(index_reg, 0x30701);
816
	WREG32(data_reg, 0xBF2087A0);
817
	WREG32(index_reg, 0x30800);
818
	WREG32(data_reg, 0x8900BF00);
819
	WREG32(index_reg, 0x30801);
820
	WREG32(data_reg, 0xBF008900);
821
}
822
 
823
struct rv515_watermark {
824
	u32        lb_request_fifo_depth;
825
	fixed20_12 num_line_pair;
826
	fixed20_12 estimated_width;
827
	fixed20_12 worst_case_latency;
828
	fixed20_12 consumption_rate;
829
	fixed20_12 active_time;
830
	fixed20_12 dbpp;
831
	fixed20_12 priority_mark_max;
832
	fixed20_12 priority_mark;
833
	fixed20_12 sclk;
1117 serge 834
};
835
 
1179 serge 836
void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
837
				  struct radeon_crtc *crtc,
838
				  struct rv515_watermark *wm)
839
{
840
	struct drm_display_mode *mode = &crtc->base.mode;
841
	fixed20_12 a, b, c;
842
	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
843
	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
1117 serge 844
 
1179 serge 845
	if (!crtc->base.enabled) {
846
		/* FIXME: wouldn't it better to set priority mark to maximum */
847
		wm->lb_request_fifo_depth = 4;
848
		return;
849
	}
1117 serge 850
 
1179 serge 851
	if (crtc->vsc.full > rfixed_const(2))
852
		wm->num_line_pair.full = rfixed_const(2);
853
	else
854
		wm->num_line_pair.full = rfixed_const(1);
855
 
856
	b.full = rfixed_const(mode->crtc_hdisplay);
857
	c.full = rfixed_const(256);
1403 serge 858
	a.full = rfixed_div(b, c);
859
	request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
860
	request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
1179 serge 861
	if (a.full < rfixed_const(4)) {
862
		wm->lb_request_fifo_depth = 4;
863
	} else {
864
		wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
865
	}
866
 
867
	/* Determine consumption rate
868
	 *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
869
	 *  vtaps = number of vertical taps,
870
	 *  vsc = vertical scaling ratio, defined as source/destination
871
	 *  hsc = horizontal scaling ration, defined as source/destination
872
	 */
873
	a.full = rfixed_const(mode->clock);
874
	b.full = rfixed_const(1000);
875
	a.full = rfixed_div(a, b);
876
	pclk.full = rfixed_div(b, a);
877
	if (crtc->rmx_type != RMX_OFF) {
878
		b.full = rfixed_const(2);
879
		if (crtc->vsc.full > b.full)
880
			b.full = crtc->vsc.full;
881
		b.full = rfixed_mul(b, crtc->hsc);
882
		c.full = rfixed_const(2);
883
		b.full = rfixed_div(b, c);
884
		consumption_time.full = rfixed_div(pclk, b);
885
	} else {
886
		consumption_time.full = pclk.full;
887
	}
888
	a.full = rfixed_const(1);
889
	wm->consumption_rate.full = rfixed_div(a, consumption_time);
890
 
891
 
892
	/* Determine line time
893
	 *  LineTime = total time for one line of displayhtotal
894
	 *  LineTime = total number of horizontal pixels
895
	 *  pclk = pixel clock period(ns)
896
	 */
897
	a.full = rfixed_const(crtc->base.mode.crtc_htotal);
898
	line_time.full = rfixed_mul(a, pclk);
899
 
900
	/* Determine active time
901
	 *  ActiveTime = time of active region of display within one line,
902
	 *  hactive = total number of horizontal active pixels
903
	 *  htotal = total number of horizontal pixels
904
	 */
905
	a.full = rfixed_const(crtc->base.mode.crtc_htotal);
906
	b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
907
	wm->active_time.full = rfixed_mul(line_time, b);
908
	wm->active_time.full = rfixed_div(wm->active_time, a);
909
 
910
	/* Determine chunk time
911
	 * ChunkTime = the time it takes the DCP to send one chunk of data
912
	 * to the LB which consists of pipeline delay and inter chunk gap
913
	 * sclk = system clock(Mhz)
914
	 */
915
	a.full = rfixed_const(600 * 1000);
916
	chunk_time.full = rfixed_div(a, rdev->pm.sclk);
917
	read_delay_latency.full = rfixed_const(1000);
918
 
919
	/* Determine the worst case latency
920
	 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
921
	 * WorstCaseLatency = worst case time from urgent to when the MC starts
922
	 *                    to return data
923
	 * READ_DELAY_IDLE_MAX = constant of 1us
924
	 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
925
	 *             which consists of pipeline delay and inter chunk gap
926
	 */
927
	if (rfixed_trunc(wm->num_line_pair) > 1) {
928
		a.full = rfixed_const(3);
929
		wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
930
		wm->worst_case_latency.full += read_delay_latency.full;
931
	} else {
932
		wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
933
	}
934
 
935
	/* Determine the tolerable latency
936
	 * TolerableLatency = Any given request has only 1 line time
937
	 *                    for the data to be returned
938
	 * LBRequestFifoDepth = Number of chunk requests the LB can
939
	 *                      put into the request FIFO for a display
940
	 *  LineTime = total time for one line of display
941
	 *  ChunkTime = the time it takes the DCP to send one chunk
942
	 *              of data to the LB which consists of
943
	 *  pipeline delay and inter chunk gap
944
	 */
945
	if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
946
		tolerable_latency.full = line_time.full;
947
	} else {
948
		tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
949
		tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
950
		tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
951
		tolerable_latency.full = line_time.full - tolerable_latency.full;
952
	}
953
	/* We assume worst case 32bits (4 bytes) */
954
	wm->dbpp.full = rfixed_const(2 * 16);
955
 
956
	/* Determine the maximum priority mark
957
	 *  width = viewport width in pixels
958
	 */
959
	a.full = rfixed_const(16);
960
	wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
961
	wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
1403 serge 962
	wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
1179 serge 963
 
964
	/* Determine estimated width */
965
	estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
966
	estimated_width.full = rfixed_div(estimated_width, consumption_time);
967
	if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1403 serge 968
		wm->priority_mark.full = wm->priority_mark_max.full;
1179 serge 969
	} else {
970
		a.full = rfixed_const(16);
971
		wm->priority_mark.full = rfixed_div(estimated_width, a);
1403 serge 972
		wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
1179 serge 973
		wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
974
	}
975
}
976
 
977
void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1117 serge 978
{
1179 serge 979
	struct drm_display_mode *mode0 = NULL;
980
	struct drm_display_mode *mode1 = NULL;
981
	struct rv515_watermark wm0;
982
	struct rv515_watermark wm1;
983
	u32 tmp;
984
	fixed20_12 priority_mark02, priority_mark12, fill_rate;
985
	fixed20_12 a, b;
1117 serge 986
 
1179 serge 987
	if (rdev->mode_info.crtcs[0]->base.enabled)
988
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
989
	if (rdev->mode_info.crtcs[1]->base.enabled)
990
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
991
	rs690_line_buffer_adjust(rdev, mode0, mode1);
992
 
993
	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
994
	rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
995
 
996
	tmp = wm0.lb_request_fifo_depth;
997
	tmp |= wm1.lb_request_fifo_depth << 16;
998
	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
999
 
1000
	if (mode0 && mode1) {
1001
		if (rfixed_trunc(wm0.dbpp) > 64)
1002
			a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1003
		else
1004
			a.full = wm0.num_line_pair.full;
1005
		if (rfixed_trunc(wm1.dbpp) > 64)
1006
			b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1007
		else
1008
			b.full = wm1.num_line_pair.full;
1009
		a.full += b.full;
1010
		fill_rate.full = rfixed_div(wm0.sclk, a);
1011
		if (wm0.consumption_rate.full > fill_rate.full) {
1012
			b.full = wm0.consumption_rate.full - fill_rate.full;
1013
			b.full = rfixed_mul(b, wm0.active_time);
1014
			a.full = rfixed_const(16);
1015
			b.full = rfixed_div(b, a);
1016
			a.full = rfixed_mul(wm0.worst_case_latency,
1017
						wm0.consumption_rate);
1018
			priority_mark02.full = a.full + b.full;
1019
		} else {
1020
			a.full = rfixed_mul(wm0.worst_case_latency,
1021
						wm0.consumption_rate);
1022
			b.full = rfixed_const(16 * 1000);
1023
			priority_mark02.full = rfixed_div(a, b);
1024
		}
1025
		if (wm1.consumption_rate.full > fill_rate.full) {
1026
			b.full = wm1.consumption_rate.full - fill_rate.full;
1027
			b.full = rfixed_mul(b, wm1.active_time);
1028
			a.full = rfixed_const(16);
1029
			b.full = rfixed_div(b, a);
1030
			a.full = rfixed_mul(wm1.worst_case_latency,
1031
						wm1.consumption_rate);
1032
			priority_mark12.full = a.full + b.full;
1033
		} else {
1034
			a.full = rfixed_mul(wm1.worst_case_latency,
1035
						wm1.consumption_rate);
1036
			b.full = rfixed_const(16 * 1000);
1037
			priority_mark12.full = rfixed_div(a, b);
1038
		}
1039
		if (wm0.priority_mark.full > priority_mark02.full)
1040
			priority_mark02.full = wm0.priority_mark.full;
1041
		if (rfixed_trunc(priority_mark02) < 0)
1042
			priority_mark02.full = 0;
1043
		if (wm0.priority_mark_max.full > priority_mark02.full)
1044
			priority_mark02.full = wm0.priority_mark_max.full;
1045
		if (wm1.priority_mark.full > priority_mark12.full)
1046
			priority_mark12.full = wm1.priority_mark.full;
1047
		if (rfixed_trunc(priority_mark12) < 0)
1048
			priority_mark12.full = 0;
1049
		if (wm1.priority_mark_max.full > priority_mark12.full)
1050
			priority_mark12.full = wm1.priority_mark_max.full;
1051
		WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1052
		WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1053
		WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1054
		WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1055
	} else if (mode0) {
1056
		if (rfixed_trunc(wm0.dbpp) > 64)
1057
			a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1058
		else
1059
			a.full = wm0.num_line_pair.full;
1060
		fill_rate.full = rfixed_div(wm0.sclk, a);
1061
		if (wm0.consumption_rate.full > fill_rate.full) {
1062
			b.full = wm0.consumption_rate.full - fill_rate.full;
1063
			b.full = rfixed_mul(b, wm0.active_time);
1064
			a.full = rfixed_const(16);
1065
			b.full = rfixed_div(b, a);
1066
			a.full = rfixed_mul(wm0.worst_case_latency,
1067
						wm0.consumption_rate);
1068
			priority_mark02.full = a.full + b.full;
1069
		} else {
1070
			a.full = rfixed_mul(wm0.worst_case_latency,
1071
						wm0.consumption_rate);
1072
			b.full = rfixed_const(16);
1073
			priority_mark02.full = rfixed_div(a, b);
1074
		}
1075
		if (wm0.priority_mark.full > priority_mark02.full)
1076
			priority_mark02.full = wm0.priority_mark.full;
1077
		if (rfixed_trunc(priority_mark02) < 0)
1078
			priority_mark02.full = 0;
1079
		if (wm0.priority_mark_max.full > priority_mark02.full)
1080
			priority_mark02.full = wm0.priority_mark_max.full;
1081
		WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1082
		WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1083
		WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1084
		WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1085
	} else {
1086
		if (rfixed_trunc(wm1.dbpp) > 64)
1087
			a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1088
		else
1089
			a.full = wm1.num_line_pair.full;
1090
		fill_rate.full = rfixed_div(wm1.sclk, a);
1091
		if (wm1.consumption_rate.full > fill_rate.full) {
1092
			b.full = wm1.consumption_rate.full - fill_rate.full;
1093
			b.full = rfixed_mul(b, wm1.active_time);
1094
			a.full = rfixed_const(16);
1095
			b.full = rfixed_div(b, a);
1096
			a.full = rfixed_mul(wm1.worst_case_latency,
1097
						wm1.consumption_rate);
1098
			priority_mark12.full = a.full + b.full;
1099
		} else {
1100
			a.full = rfixed_mul(wm1.worst_case_latency,
1101
						wm1.consumption_rate);
1102
			b.full = rfixed_const(16 * 1000);
1103
			priority_mark12.full = rfixed_div(a, b);
1104
		}
1105
		if (wm1.priority_mark.full > priority_mark12.full)
1106
			priority_mark12.full = wm1.priority_mark.full;
1107
		if (rfixed_trunc(priority_mark12) < 0)
1108
			priority_mark12.full = 0;
1109
		if (wm1.priority_mark_max.full > priority_mark12.full)
1110
			priority_mark12.full = wm1.priority_mark_max.full;
1111
		WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1112
		WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1113
		WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1114
		WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1115
	}
1117 serge 1116
}
1179 serge 1117
 
1118
void rv515_bandwidth_update(struct radeon_device *rdev)
1119
{
1120
	uint32_t tmp;
1121
	struct drm_display_mode *mode0 = NULL;
1122
	struct drm_display_mode *mode1 = NULL;
1123
 
1124
	if (rdev->mode_info.crtcs[0]->base.enabled)
1125
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1126
	if (rdev->mode_info.crtcs[1]->base.enabled)
1127
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1128
	/*
1129
	 * Set display0/1 priority up in the memory controller for
1130
	 * modes if the user specifies HIGH for displaypriority
1131
	 * option.
1132
	 */
1133
	if (rdev->disp_priority == 2) {
1134
		tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1135
		tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1136
		tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1137
		if (mode1)
1138
			tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1139
		if (mode0)
1140
			tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1141
		WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1142
	}
1143
	rv515_bandwidth_avivo_update(rdev);
1144
}