WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/rs780_dpm.c

Rev	Author	Line No.	Line
5078	serge	1	/*
		2	* Copyright 2011 Advanced Micro Devices, Inc.
		3	*
		4	* Permission is hereby granted, free of charge, to any person obtaining a
		5	* copy of this software and associated documentation files (the "Software"),
		6	* to deal in the Software without restriction, including without limitation
		7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		8	* and/or sell copies of the Software, and to permit persons to whom the
		9	* Software is furnished to do so, subject to the following conditions:
		10	*
		11	* The above copyright notice and this permission notice shall be included in
		12	* all copies or substantial portions of the Software.
		13	*
		14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		20	* OTHER DEALINGS IN THE SOFTWARE.
		21	*
		22	* Authors: Alex Deucher
		23	*/
		24
		25	#include "drmP.h"
		26	#include "radeon.h"
		27	#include "rs780d.h"
		28	#include "r600_dpm.h"
		29	#include "rs780_dpm.h"
		30	#include "atom.h"
		31	#include
		32
		33	static struct igp_ps rs780_get_ps(struct radeon_ps rps)
		34	{
		35	struct igp_ps *ps = rps->ps_priv;
		36
		37	return ps;
		38	}
		39
		40	static struct igp_power_info rs780_get_pi(struct radeon_device rdev)
		41	{
		42	struct igp_power_info *pi = rdev->pm.dpm.priv;
		43
		44	return pi;
		45	}
		46
		47	static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
		48	{
		49	struct igp_power_info *pi = rs780_get_pi(rdev);
		50	struct radeon_mode_info *minfo = &rdev->mode_info;
		51	struct drm_crtc *crtc;
		52	struct radeon_crtc *radeon_crtc;
		53	int i;
		54
		55	/* defaults */
		56	pi->crtc_id = 0;
		57	pi->refresh_rate = 60;
		58
		59	for (i = 0; i < rdev->num_crtc; i++) {
		60	crtc = (struct drm_crtc *)minfo->crtcs[i];
		61	if (crtc && crtc->enabled) {
		62	radeon_crtc = to_radeon_crtc(crtc);
		63	pi->crtc_id = radeon_crtc->crtc_id;
		64	if (crtc->mode.htotal && crtc->mode.vtotal)
		65	pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
		66	break;
		67	}
		68	}
		69	}
		70
		71	static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
		72
		73	static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
		74	struct radeon_ps *boot_ps)
		75	{
		76	struct atom_clock_dividers dividers;
		77	struct igp_ps *default_state = rs780_get_ps(boot_ps);
		78	int i, ret;
		79
		80	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		81	default_state->sclk_low, false, ÷rs);
		82	if (ret)
		83	return ret;
		84
		85	r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
		86	r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
		87	r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
		88
		89	if (dividers.enable_post_div)
		90	r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
		91	else
		92	r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
		93
		94	r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
		95	r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
		96
		97	r600_engine_clock_entry_enable(rdev, 0, true);
		98	for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
		99	r600_engine_clock_entry_enable(rdev, i, false);
		100
		101	r600_enable_mclk_control(rdev, false);
		102	r600_voltage_control_enable_pins(rdev, 0);
		103
		104	return 0;
		105	}
		106
		107	static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
		108	struct radeon_ps *boot_ps)
		109	{
		110	int ret = 0;
		111	int i;
		112
		113	r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
		114
		115	r600_set_at(rdev, 0, 0, 0, 0);
		116
		117	r600_set_git(rdev, R600_GICST_DFLT);
		118
		119	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
		120	r600_set_tc(rdev, i, 0, 0);
		121
		122	r600_select_td(rdev, R600_TD_DFLT);
		123	r600_set_vrc(rdev, 0);
		124
		125	r600_set_tpu(rdev, R600_TPU_DFLT);
		126	r600_set_tpc(rdev, R600_TPC_DFLT);
		127
		128	r600_set_sstu(rdev, R600_SSTU_DFLT);
		129	r600_set_sst(rdev, R600_SST_DFLT);
		130
		131	r600_set_fctu(rdev, R600_FCTU_DFLT);
		132	r600_set_fct(rdev, R600_FCT_DFLT);
		133
		134	r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
		135	r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
		136	r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
		137	r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
		138	r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
		139
		140	r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
		141	r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
		142	r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
		143
		144	ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
		145
		146	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
		147	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
		148	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
		149
		150	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
		151	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
		152	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
		153
		154	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
		155	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
		156	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
		157
		158	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
		159	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
		160	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
		161
		162	r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
		163	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
		164	r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
		165	r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
		166
		167	r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
		168
		169	r600_set_vrc(rdev, RS780_CGFTV_DFLT);
		170
		171	return ret;
		172	}
		173
		174	static void rs780_start_dpm(struct radeon_device *rdev)
		175	{
		176	r600_enable_sclk_control(rdev, false);
		177	r600_enable_mclk_control(rdev, false);
		178
		179	r600_dynamicpm_enable(rdev, true);
		180
		181	radeon_wait_for_vblank(rdev, 0);
		182	radeon_wait_for_vblank(rdev, 1);
		183
		184	r600_enable_spll_bypass(rdev, true);
		185	r600_wait_for_spll_change(rdev);
		186	r600_enable_spll_bypass(rdev, false);
		187	r600_wait_for_spll_change(rdev);
		188
		189	r600_enable_spll_bypass(rdev, true);
		190	r600_wait_for_spll_change(rdev);
		191	r600_enable_spll_bypass(rdev, false);
		192	r600_wait_for_spll_change(rdev);
		193
		194	r600_enable_sclk_control(rdev, true);
		195	}
		196
		197
		198	static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
		199	{
		200	WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
		201	~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
		202
		203	WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
		204	RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
		205	~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
		206	}
		207
		208	static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
		209	{
		210	u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
		211
		212	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
		213	~STARTING_FEEDBACK_DIV_MASK);
		214
		215	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
		216	~FORCED_FEEDBACK_DIV_MASK);
		217
		218	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
		219	}
		220
		221	static void rs780_voltage_scaling_init(struct radeon_device *rdev)
		222	{
		223	struct igp_power_info *pi = rs780_get_pi(rdev);
		224	struct drm_device *dev = rdev->ddev;
		225	u32 fv_throt_pwm_fb_div_range[3];
		226	u32 fv_throt_pwm_range[4];
		227
		228	if (dev->pdev->device == 0x9614) {
		229	fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
		230	fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
		231	fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
		232	} else if ((dev->pdev->device == 0x9714) \|\|
		233	(dev->pdev->device == 0x9715)) {
		234	fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
		235	fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
		236	fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
		237	} else {
		238	fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
		239	fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
		240	fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
		241	}
		242
		243	if (pi->pwm_voltage_control) {
		244	fv_throt_pwm_range[0] = pi->min_voltage;
		245	fv_throt_pwm_range[1] = pi->min_voltage;
		246	fv_throt_pwm_range[2] = pi->max_voltage;
		247	fv_throt_pwm_range[3] = pi->max_voltage;
		248	} else {
		249	fv_throt_pwm_range[0] = pi->invert_pwm_required ?
		250	RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
		251	fv_throt_pwm_range[1] = pi->invert_pwm_required ?
		252	RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
		253	fv_throt_pwm_range[2] = pi->invert_pwm_required ?
		254	RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
		255	fv_throt_pwm_range[3] = pi->invert_pwm_required ?
		256	RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
		257	}
		258
		259	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		260	STARTING_PWM_HIGHTIME(pi->max_voltage),
		261	~STARTING_PWM_HIGHTIME_MASK);
		262
		263	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		264	NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
		265	~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
		266
		267	WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
		268	~FORCE_STARTING_PWM_HIGHTIME);
		269
		270	if (pi->invert_pwm_required)
		271	WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
		272	else
		273	WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
		274
		275	rs780_voltage_scaling_enable(rdev, true);
		276
		277	WREG32(FVTHROT_PWM_CTRL_REG1,
		278	(MIN_PWM_HIGHTIME(pi->min_voltage) \|
		279	MAX_PWM_HIGHTIME(pi->max_voltage)));
		280
		281	WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
		282	WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
		283	WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
		284	WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
		285
		286	WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
		287	RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
		288	~RANGE0_PWM_FEEDBACK_DIV_MASK);
		289
		290	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
		291	(RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) \|
		292	RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
		293
		294	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
		295	(RANGE0_PWM(fv_throt_pwm_range[1]) \|
		296	RANGE1_PWM(fv_throt_pwm_range[2])));
		297	WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
		298	(RANGE2_PWM(fv_throt_pwm_range[1]) \|
		299	RANGE3_PWM(fv_throt_pwm_range[2])));
		300	}
		301
		302	static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
		303	{
		304	if (enable)
		305	WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT \| ENABLE_FV_UPDATE,
		306	~(ENABLE_FV_THROT \| ENABLE_FV_UPDATE));
		307	else
		308	WREG32_P(FVTHROT_CNTRL_REG, 0,
		309	~(ENABLE_FV_THROT \| ENABLE_FV_UPDATE));
		310	}
		311
		312	static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
		313	{
		314	if (enable)
		315	WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
		316	else
		317	WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
		318	}
		319
		320	static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
		321	{
		322	WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
		323	WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
		324	WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
		325	WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
		326	WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
		327
		328	WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
		329	WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
		330	WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
		331	WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
		332	WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
		333	}
		334
		335	static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
		336	{
		337	WREG32_P(FVTHROT_FBDIV_REG2,
		338	FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
		339	~FB_DIV_TIMER_VAL_MASK);
		340
		341	WREG32_P(FVTHROT_CNTRL_REG,
		342	REFRESH_RATE_DIVISOR(0) \| MINIMUM_CIP(0xf),
		343	~(REFRESH_RATE_DIVISOR_MASK \| MINIMUM_CIP_MASK));
		344	}
		345
		346	static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
		347	{
		348	WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL \| TREND_SEL_MODE));
		349	}
		350
		351	static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
		352	{
		353	WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
		354	WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
		355	WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
		356	WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
		357
		358	WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
		359	}
		360
		361	static void rs780_program_at(struct radeon_device *rdev)
		362	{
		363	struct igp_power_info *pi = rs780_get_pi(rdev);
		364
		365	WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
		366	WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
		367	WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
		368	WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
		369	WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
		370	}
		371
		372	static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
		373	{
		374	WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
		375	}
		376
		377	static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
		378	{
		379	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
		380
		381	if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
		382	(current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
		383	return;
		384
		385	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
		386
		387	udelay(1);
		388
		389	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		390	STARTING_PWM_HIGHTIME(voltage),
		391	~STARTING_PWM_HIGHTIME_MASK);
		392
		393	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		394	FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
		395
		396	WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
		397	~RANGE_PWM_FEEDBACK_DIV_EN);
		398
		399	udelay(1);
		400
		401	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
		402	}
		403
		404	static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
		405	{
		406	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
		407
		408	if (current_state->sclk_low == current_state->sclk_high)
		409	return;
		410
		411	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
		412
		413	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
		414	~FORCED_FEEDBACK_DIV_MASK);
		415	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
		416	~STARTING_FEEDBACK_DIV_MASK);
		417	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
		418
		419	udelay(100);
		420
		421	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
		422	}
		423
		424	static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
		425	struct radeon_ps *new_ps,
		426	struct radeon_ps *old_ps)
		427	{
		428	struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
		429	struct igp_ps *new_state = rs780_get_ps(new_ps);
		430	struct igp_ps *old_state = rs780_get_ps(old_ps);
		431	int ret;
		432
		433	if ((new_state->sclk_high == old_state->sclk_high) &&
		434	(new_state->sclk_low == old_state->sclk_low))
		435	return 0;
		436
		437	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		438	new_state->sclk_low, false, &min_dividers);
		439	if (ret)
		440	return ret;
		441
		442	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		443	new_state->sclk_high, false, &max_dividers);
		444	if (ret)
		445	return ret;
		446
		447	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		448	old_state->sclk_high, false, ¤t_max_dividers);
		449	if (ret)
		450	return ret;
		451
		452	if ((min_dividers.ref_div != max_dividers.ref_div) \|\|
		453	(min_dividers.post_div != max_dividers.post_div) \|\|
		454	(max_dividers.ref_div != current_max_dividers.ref_div) \|\|
		455	(max_dividers.post_div != current_max_dividers.post_div))
		456	return -EINVAL;
		457
		458	rs780_force_fbdiv(rdev, max_dividers.fb_div);
		459
		460	if (max_dividers.fb_div > min_dividers.fb_div) {
		461	WREG32_P(FVTHROT_FBDIV_REG0,
		462	MIN_FEEDBACK_DIV(min_dividers.fb_div) \|
		463	MAX_FEEDBACK_DIV(max_dividers.fb_div),
		464	~(MIN_FEEDBACK_DIV_MASK \| MAX_FEEDBACK_DIV_MASK));
		465
		466	WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
		467	}
		468
		469	return 0;
		470	}
		471
		472	static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
		473	struct radeon_ps *new_ps,
		474	struct radeon_ps *old_ps)
		475	{
		476	struct igp_ps *new_state = rs780_get_ps(new_ps);
		477	struct igp_ps *old_state = rs780_get_ps(old_ps);
		478	struct igp_power_info *pi = rs780_get_pi(rdev);
		479
		480	if ((new_state->sclk_high == old_state->sclk_high) &&
		481	(new_state->sclk_low == old_state->sclk_low))
		482	return;
		483
		484	if (pi->crtc_id == 0)
		485	WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
		486	else
		487	WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
		488
		489	}
		490
		491	static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
		492	struct radeon_ps *new_ps,
		493	struct radeon_ps *old_ps)
		494	{
		495	struct igp_ps *new_state = rs780_get_ps(new_ps);
		496	struct igp_ps *old_state = rs780_get_ps(old_ps);
		497
		498	if ((new_state->sclk_high == old_state->sclk_high) &&
		499	(new_state->sclk_low == old_state->sclk_low))
		500	return;
		501
		502	if (new_state->sclk_high == new_state->sclk_low)
		503	return;
		504
		505	rs780_clk_scaling_enable(rdev, true);
		506	}
		507
		508	static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
		509	enum rs780_vddc_level vddc)
		510	{
		511	struct igp_power_info *pi = rs780_get_pi(rdev);
		512
		513	if (vddc == RS780_VDDC_LEVEL_HIGH)
		514	return pi->max_voltage;
		515	else if (vddc == RS780_VDDC_LEVEL_LOW)
		516	return pi->min_voltage;
		517	else
		518	return pi->max_voltage;
		519	}
		520
		521	static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
		522	struct radeon_ps *new_ps)
		523	{
		524	struct igp_ps *new_state = rs780_get_ps(new_ps);
		525	struct igp_power_info *pi = rs780_get_pi(rdev);
		526	enum rs780_vddc_level vddc_high, vddc_low;
		527
		528	udelay(100);
		529
		530	if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
		531	(new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
		532	return;
		533
		534	vddc_high = rs780_get_voltage_for_vddc_level(rdev,
		535	new_state->max_voltage);
		536	vddc_low = rs780_get_voltage_for_vddc_level(rdev,
		537	new_state->min_voltage);
		538
		539	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
		540
		541	udelay(1);
		542	if (vddc_high > vddc_low) {
		543	WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
		544	RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
		545
		546	WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
		547	} else if (vddc_high == vddc_low) {
		548	if (pi->max_voltage != vddc_high) {
		549	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		550	STARTING_PWM_HIGHTIME(vddc_high),
		551	~STARTING_PWM_HIGHTIME_MASK);
		552
		553	WREG32_P(FVTHROT_PWM_CTRL_REG0,
		554	FORCE_STARTING_PWM_HIGHTIME,
		555	~FORCE_STARTING_PWM_HIGHTIME);
		556	}
		557	}
		558
		559	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
		560	}
		561
		562	static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
		563	struct radeon_ps *new_ps,
		564	struct radeon_ps *old_ps)
		565	{
		566	struct igp_ps *new_state = rs780_get_ps(new_ps);
		567	struct igp_ps *current_state = rs780_get_ps(old_ps);
		568
		569	if ((new_ps->vclk == old_ps->vclk) &&
		570	(new_ps->dclk == old_ps->dclk))
		571	return;
		572
		573	if (new_state->sclk_high >= current_state->sclk_high)
		574	return;
		575
		576	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
		577	}
		578
		579	static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
		580	struct radeon_ps *new_ps,
		581	struct radeon_ps *old_ps)
		582	{
		583	struct igp_ps *new_state = rs780_get_ps(new_ps);
		584	struct igp_ps *current_state = rs780_get_ps(old_ps);
		585
		586	if ((new_ps->vclk == old_ps->vclk) &&
		587	(new_ps->dclk == old_ps->dclk))
		588	return;
		589
		590	if (new_state->sclk_high < current_state->sclk_high)
		591	return;
		592
		593	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
		594	}
		595
		596	int rs780_dpm_enable(struct radeon_device *rdev)
		597	{
		598	struct igp_power_info *pi = rs780_get_pi(rdev);
		599	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
		600	int ret;
		601
		602	rs780_get_pm_mode_parameters(rdev);
		603	rs780_disable_vbios_powersaving(rdev);
		604
		605	if (r600_dynamicpm_enabled(rdev))
		606	return -EINVAL;
		607	ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
		608	if (ret)
		609	return ret;
		610	rs780_start_dpm(rdev);
		611
		612	rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
		613	rs780_preset_starting_fbdiv(rdev);
		614	if (pi->voltage_control)
		615	rs780_voltage_scaling_init(rdev);
		616	rs780_clk_scaling_enable(rdev, true);
		617	rs780_set_engine_clock_sc(rdev);
		618	rs780_set_engine_clock_wfc(rdev);
		619	rs780_program_at(rdev);
		620	rs780_set_engine_clock_tdc(rdev);
		621	rs780_set_engine_clock_ssc(rdev);
		622
		623	if (pi->gfx_clock_gating)
		624	r600_gfx_clockgating_enable(rdev, true);
		625
		626	return 0;
		627	}
		628
		629	void rs780_dpm_disable(struct radeon_device *rdev)
		630	{
		631	struct igp_power_info *pi = rs780_get_pi(rdev);
		632
		633	r600_dynamicpm_enable(rdev, false);
		634
		635	rs780_clk_scaling_enable(rdev, false);
		636	rs780_voltage_scaling_enable(rdev, false);
		637
		638	if (pi->gfx_clock_gating)
		639	r600_gfx_clockgating_enable(rdev, false);
		640
		641	if (rdev->irq.installed &&
		642	(rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
		643	rdev->irq.dpm_thermal = false;
		644	radeon_irq_set(rdev);
		645	}
		646	}
		647
		648	int rs780_dpm_set_power_state(struct radeon_device *rdev)
		649	{
		650	struct igp_power_info *pi = rs780_get_pi(rdev);
		651	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
		652	struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
		653	int ret;
		654
		655	rs780_get_pm_mode_parameters(rdev);
		656
		657	rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
		658
		659	if (pi->voltage_control) {
		660	rs780_force_voltage(rdev, pi->max_voltage);
		661	mdelay(5);
		662	}
		663
		664	ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
		665	if (ret)
		666	return ret;
		667	rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
		668
		669	rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
		670
		671	if (pi->voltage_control)
		672	rs780_enable_voltage_scaling(rdev, new_ps);
		673
		674	rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
		675
		676	return 0;
		677	}
		678
		679	void rs780_dpm_setup_asic(struct radeon_device *rdev)
		680	{
		681
		682	}
		683
		684	void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
		685	{
		686	rs780_get_pm_mode_parameters(rdev);
		687	rs780_program_at(rdev);
		688	}
		689
		690	union igp_info {
		691	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		692	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
		693	};
		694
		695	union power_info {
		696	struct _ATOM_POWERPLAY_INFO info;
		697	struct _ATOM_POWERPLAY_INFO_V2 info_2;
		698	struct _ATOM_POWERPLAY_INFO_V3 info_3;
		699	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
		700	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
		701	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
		702	};
		703
		704	union pplib_clock_info {
		705	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
		706	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
		707	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
		708	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
		709	};
		710
		711	union pplib_power_state {
		712	struct _ATOM_PPLIB_STATE v1;
		713	struct _ATOM_PPLIB_STATE_V2 v2;
		714	};
		715
		716	static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
		717	struct radeon_ps *rps,
		718	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
		719	u8 table_rev)
		720	{
		721	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
		722	rps->class = le16_to_cpu(non_clock_info->usClassification);
		723	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
		724
		725	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
		726	rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
		727	rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
		728	} else {
		729	rps->vclk = 0;
		730	rps->dclk = 0;
		731	}
		732
		733	if (r600_is_uvd_state(rps->class, rps->class2)) {
		734	if ((rps->vclk == 0) \|\| (rps->dclk == 0)) {
		735	rps->vclk = RS780_DEFAULT_VCLK_FREQ;
		736	rps->dclk = RS780_DEFAULT_DCLK_FREQ;
		737	}
		738	}
		739
		740	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
		741	rdev->pm.dpm.boot_ps = rps;
		742	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
		743	rdev->pm.dpm.uvd_ps = rps;
		744	}
		745
		746	static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
		747	struct radeon_ps *rps,
		748	union pplib_clock_info *clock_info)
		749	{
		750	struct igp_ps *ps = rs780_get_ps(rps);
		751	u32 sclk;
		752
		753	sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
		754	sclk \|= clock_info->rs780.ucLowEngineClockHigh << 16;
		755	ps->sclk_low = sclk;
		756	sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
		757	sclk \|= clock_info->rs780.ucHighEngineClockHigh << 16;
		758	ps->sclk_high = sclk;
		759	switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
		760	case ATOM_PPLIB_RS780_VOLTAGE_NONE:
		761	default:
		762	ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
		763	ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
		764	break;
		765	case ATOM_PPLIB_RS780_VOLTAGE_LOW:
		766	ps->min_voltage = RS780_VDDC_LEVEL_LOW;
		767	ps->max_voltage = RS780_VDDC_LEVEL_LOW;
		768	break;
		769	case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
		770	ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
		771	ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
		772	break;
		773	case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
		774	ps->min_voltage = RS780_VDDC_LEVEL_LOW;
		775	ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
		776	break;
		777	}
		778	ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
		779
		780	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
		781	ps->sclk_low = rdev->clock.default_sclk;
		782	ps->sclk_high = rdev->clock.default_sclk;
		783	ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
		784	ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
		785	}
		786	}
		787
		788	static int rs780_parse_power_table(struct radeon_device *rdev)
		789	{
		790	struct radeon_mode_info *mode_info = &rdev->mode_info;
		791	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		792	union pplib_power_state *power_state;
		793	int i;
		794	union pplib_clock_info *clock_info;
		795	union power_info *power_info;
		796	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		797	u16 data_offset;
		798	u8 frev, crev;
		799	struct igp_ps *ps;
		800
		801	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		802	&frev, &crev, &data_offset))
		803	return -EINVAL;
		804	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		805
		806	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
		807	power_info->pplib.ucNumStates, GFP_KERNEL);
		808	if (!rdev->pm.dpm.ps)
		809	return -ENOMEM;
		810
		811	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
		812	power_state = (union pplib_power_state *)
		813	(mode_info->atom_context->bios + data_offset +
		814	le16_to_cpu(power_info->pplib.usStateArrayOffset) +
		815	i * power_info->pplib.ucStateEntrySize);
		816	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		817	(mode_info->atom_context->bios + data_offset +
		818	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
		819	(power_state->v1.ucNonClockStateIndex *
		820	power_info->pplib.ucNonClockSize));
		821	if (power_info->pplib.ucStateEntrySize - 1) {
		822	clock_info = (union pplib_clock_info *)
		823	(mode_info->atom_context->bios + data_offset +
		824	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
		825	(power_state->v1.ucClockStateIndices[0] *
		826	power_info->pplib.ucClockInfoSize));
		827	ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
		828	if (ps == NULL) {
		829	kfree(rdev->pm.dpm.ps);
		830	return -ENOMEM;
		831	}
		832	rdev->pm.dpm.ps[i].ps_priv = ps;
		833	rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
		834	non_clock_info,
		835	power_info->pplib.ucNonClockSize);
		836	rs780_parse_pplib_clock_info(rdev,
		837	&rdev->pm.dpm.ps[i],
		838	clock_info);
		839	}
		840	}
		841	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
		842	return 0;
		843	}
		844
		845	int rs780_dpm_init(struct radeon_device *rdev)
		846	{
		847	struct igp_power_info *pi;
		848	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		849	union igp_info *info;
		850	u16 data_offset;
		851	u8 frev, crev;
		852	int ret;
		853
		854	pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
		855	if (pi == NULL)
		856	return -ENOMEM;
		857	rdev->pm.dpm.priv = pi;
		858
		859	ret = r600_get_platform_caps(rdev);
		860	if (ret)
		861	return ret;
		862
		863	ret = rs780_parse_power_table(rdev);
		864	if (ret)
		865	return ret;
		866
		867	pi->voltage_control = false;
		868	pi->gfx_clock_gating = true;
		869
		870	if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
		871	&frev, &crev, &data_offset)) {
		872	info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
		873
		874	/* Get various system informations from bios */
		875	switch (crev) {
		876	case 1:
		877	pi->num_of_cycles_in_period =
		878	info->info.ucNumberOfCyclesInPeriod;
		879	pi->num_of_cycles_in_period \|=
		880	info->info.ucNumberOfCyclesInPeriodHi << 8;
		881	pi->invert_pwm_required =
		882	(pi->num_of_cycles_in_period & 0x8000) ? true : false;
		883	pi->boot_voltage = info->info.ucStartingPWM_HighTime;
		884	pi->max_voltage = info->info.ucMaxNBVoltage;
		885	pi->max_voltage \|= info->info.ucMaxNBVoltageHigh << 8;
		886	pi->min_voltage = info->info.ucMinNBVoltage;
		887	pi->min_voltage \|= info->info.ucMinNBVoltageHigh << 8;
		888	pi->inter_voltage_low =
		889	le16_to_cpu(info->info.usInterNBVoltageLow);
		890	pi->inter_voltage_high =
		891	le16_to_cpu(info->info.usInterNBVoltageHigh);
		892	pi->voltage_control = true;
		893	pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
		894	break;
		895	case 2:
		896	pi->num_of_cycles_in_period =
		897	le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
		898	pi->invert_pwm_required =
		899	(pi->num_of_cycles_in_period & 0x8000) ? true : false;
		900	pi->boot_voltage =
		901	le16_to_cpu(info->info_2.usBootUpNBVoltage);
		902	pi->max_voltage =
		903	le16_to_cpu(info->info_2.usMaxNBVoltage);
		904	pi->min_voltage =
		905	le16_to_cpu(info->info_2.usMinNBVoltage);
		906	pi->system_config =
		907	le32_to_cpu(info->info_2.ulSystemConfig);
		908	pi->pwm_voltage_control =
		909	(pi->system_config & 0x4) ? true : false;
		910	pi->voltage_control = true;
		911	pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
		912	break;
		913	default:
		914	DRM_ERROR("No integrated system info for your GPU\n");
		915	return -EINVAL;
		916	}
		917	if (pi->min_voltage > pi->max_voltage)
		918	pi->voltage_control = false;
		919	if (pi->pwm_voltage_control) {
		920	if ((pi->num_of_cycles_in_period == 0) \|\|
		921	(pi->max_voltage == 0) \|\|
		922	(pi->min_voltage == 0))
		923	pi->voltage_control = false;
		924	} else {
		925	if ((pi->num_of_cycles_in_period == 0) \|\|
		926	(pi->max_voltage == 0))
		927	pi->voltage_control = false;
		928	}
		929
		930	return 0;
		931	}
		932	radeon_dpm_fini(rdev);
		933	return -EINVAL;
		934	}
		935
		936	void rs780_dpm_print_power_state(struct radeon_device *rdev,
		937	struct radeon_ps *rps)
		938	{
		939	struct igp_ps *ps = rs780_get_ps(rps);
		940
		941	r600_dpm_print_class_info(rps->class, rps->class2);
		942	r600_dpm_print_cap_info(rps->caps);
		943	printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
		944	printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
		945	ps->sclk_low, ps->min_voltage);
		946	printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
		947	ps->sclk_high, ps->max_voltage);
		948	r600_dpm_print_ps_status(rdev, rps);
		949	}
		950
		951	void rs780_dpm_fini(struct radeon_device *rdev)
		952	{
		953	int i;
		954
		955	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
		956	kfree(rdev->pm.dpm.ps[i].ps_priv);
		957	}
		958	kfree(rdev->pm.dpm.ps);
		959	kfree(rdev->pm.dpm.priv);
		960	}
		961
		962	u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
		963	{
		964	struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
		965
		966	if (low)
		967	return requested_state->sclk_low;
		968	else
		969	return requested_state->sclk_high;
		970	}
		971
		972	u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
		973	{
		974	struct igp_power_info *pi = rs780_get_pi(rdev);
		975
		976	return pi->bootup_uma_clk;
		977	}
		978
		979	void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
		980	struct seq_file *m)
		981	{
		982	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
		983	struct igp_ps *ps = rs780_get_ps(rps);
		984	u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
		985	u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
		986	u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
		987	u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
		988	((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
		989	u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
		990	(post_div * ref_div);
		991
		992	seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
		993
		994	/* guess based on the current sclk */
		995	if (sclk < (ps->sclk_low + 500))
		996	seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n",
		997	ps->sclk_low, ps->min_voltage);
		998	else
		999	seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
		1000	ps->sclk_high, ps->max_voltage);
		1001	}
		1002
		1003	int rs780_dpm_force_performance_level(struct radeon_device *rdev,
		1004	enum radeon_dpm_forced_level level)
		1005	{
		1006	struct igp_power_info *pi = rs780_get_pi(rdev);
		1007	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
		1008	struct igp_ps *ps = rs780_get_ps(rps);
		1009	struct atom_clock_dividers dividers;
		1010	int ret;
		1011
		1012	rs780_clk_scaling_enable(rdev, false);
		1013	rs780_voltage_scaling_enable(rdev, false);
		1014
		1015	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
		1016	if (pi->voltage_control)
		1017	rs780_force_voltage(rdev, pi->max_voltage);
		1018
		1019	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		1020	ps->sclk_high, false, ÷rs);
		1021	if (ret)
		1022	return ret;
		1023
		1024	rs780_force_fbdiv(rdev, dividers.fb_div);
		1025	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
		1026	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		1027	ps->sclk_low, false, ÷rs);
		1028	if (ret)
		1029	return ret;
		1030
		1031	rs780_force_fbdiv(rdev, dividers.fb_div);
		1032
		1033	if (pi->voltage_control)
		1034	rs780_force_voltage(rdev, pi->min_voltage);
		1035	} else {
		1036	if (pi->voltage_control)
		1037	rs780_force_voltage(rdev, pi->max_voltage);
		1038
		1039	if (ps->sclk_high != ps->sclk_low) {
		1040	WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
		1041	rs780_clk_scaling_enable(rdev, true);
		1042	}
		1043
		1044	if (pi->voltage_control) {
		1045	rs780_voltage_scaling_enable(rdev, true);
		1046	rs780_enable_voltage_scaling(rdev, rps);
		1047	}
		1048	}
		1049
		1050	rdev->pm.dpm.forced_level = level;
		1051
		1052	return 0;
		1053	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs780_dpm.c – Rev 5078