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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include "drmP.h" |
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29 | #include "radeon.h" |
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1963 | serge | 30 | #include "radeon_asic.h" |
1179 | serge | 31 | #include "atom.h" |
1221 | serge | 32 | #include "rs690d.h" |
1128 | serge | 33 | |
1221 | serge | 34 | static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
1128 | serge | 35 | { |
36 | unsigned i; |
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37 | uint32_t tmp; |
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38 | |||
39 | for (i = 0; i < rdev->usec_timeout; i++) { |
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40 | /* read MC_STATUS */ |
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1221 | serge | 41 | tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); |
42 | if (G_000090_MC_SYSTEM_IDLE(tmp)) |
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1128 | serge | 43 | return 0; |
1221 | serge | 44 | udelay(1); |
1128 | serge | 45 | } |
46 | return -1; |
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47 | } |
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48 | |||
1221 | serge | 49 | static void rs690_gpu_init(struct radeon_device *rdev) |
1128 | serge | 50 | { |
51 | /* FIXME: is this correct ? */ |
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52 | r420_pipes_init(rdev); |
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53 | if (rs690_mc_wait_for_idle(rdev)) { |
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54 | printk(KERN_WARNING "Failed to wait MC idle while " |
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55 | "programming pipes. Bad things might happen.\n"); |
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56 | } |
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57 | } |
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58 | |||
1963 | serge | 59 | union igp_info { |
60 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
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61 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; |
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62 | }; |
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63 | |||
1179 | serge | 64 | void rs690_pm_info(struct radeon_device *rdev) |
65 | { |
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66 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
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1963 | serge | 67 | union igp_info *info; |
1179 | serge | 68 | uint16_t data_offset; |
69 | uint8_t frev, crev; |
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70 | fixed20_12 tmp; |
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71 | |||
1963 | serge | 72 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
73 | &frev, &crev, &data_offset)) { |
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74 | info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); |
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75 | |||
1179 | serge | 76 | /* Get various system informations from bios */ |
77 | switch (crev) { |
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78 | case 1: |
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1963 | serge | 79 | tmp.full = dfixed_const(100); |
80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); |
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81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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82 | if (le16_to_cpu(info->info.usK8MemoryClock)) |
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83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); |
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84 | else if (rdev->clock.default_mclk) { |
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85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
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86 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
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87 | } else |
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88 | rdev->pm.igp_system_mclk.full = dfixed_const(400); |
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89 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); |
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90 | rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); |
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1179 | serge | 91 | break; |
92 | case 2: |
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1963 | serge | 93 | tmp.full = dfixed_const(100); |
94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); |
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95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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96 | if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) |
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97 | rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); |
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98 | else if (rdev->clock.default_mclk) |
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99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
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100 | else |
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101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); |
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102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
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103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); |
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104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
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105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); |
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1179 | serge | 106 | break; |
107 | default: |
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108 | /* We assume the slower possible clock ie worst case */ |
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1963 | serge | 109 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
110 | rdev->pm.igp_system_mclk.full = dfixed_const(200); |
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111 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); |
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112 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
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1179 | serge | 113 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
114 | break; |
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115 | } |
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1963 | serge | 116 | } else { |
117 | /* We assume the slower possible clock ie worst case */ |
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118 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
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119 | rdev->pm.igp_system_mclk.full = dfixed_const(200); |
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120 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); |
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121 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
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122 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
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123 | } |
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1179 | serge | 124 | /* Compute various bandwidth */ |
125 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
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1963 | serge | 126 | tmp.full = dfixed_const(4); |
127 | rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); |
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1179 | serge | 128 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
129 | * = ht_clk * ht_width / 5 |
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130 | */ |
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1963 | serge | 131 | tmp.full = dfixed_const(5); |
132 | rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, |
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1179 | serge | 133 | rdev->pm.igp_ht_link_width); |
1963 | serge | 134 | rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); |
1179 | serge | 135 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
136 | /* HT link is a limiting factor */ |
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137 | rdev->pm.max_bandwidth.full = tmp.full; |
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138 | } |
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139 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
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140 | * = (sideport_clk * 14) / 10 |
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141 | */ |
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1963 | serge | 142 | tmp.full = dfixed_const(14); |
143 | rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); |
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144 | tmp.full = dfixed_const(10); |
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145 | rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); |
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1179 | serge | 146 | } |
147 | |||
1430 | serge | 148 | void rs690_mc_init(struct radeon_device *rdev) |
1128 | serge | 149 | { |
1430 | serge | 150 | u64 base; |
1128 | serge | 151 | |
152 | rs400_gart_adjust_size(rdev); |
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153 | rdev->mc.vram_is_ddr = true; |
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154 | rdev->mc.vram_width = 128; |
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1179 | serge | 155 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
156 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
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1963 | serge | 157 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
158 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
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1430 | serge | 159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
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161 | base = G_000100_MC_FB_START(base) << 16; |
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1963 | serge | 162 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
1179 | serge | 163 | rs690_pm_info(rdev); |
1430 | serge | 164 | radeon_vram_location(rdev, &rdev->mc, base); |
1963 | serge | 165 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
1430 | serge | 166 | radeon_gtt_location(rdev, &rdev->mc); |
1963 | serge | 167 | radeon_update_bandwidth_info(rdev); |
1403 | serge | 168 | } |
169 | |||
1179 | serge | 170 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
171 | struct drm_display_mode *mode1, |
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172 | struct drm_display_mode *mode2) |
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173 | { |
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174 | u32 tmp; |
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1128 | serge | 175 | |
1179 | serge | 176 | /* |
177 | * Line Buffer Setup |
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178 | * There is a single line buffer shared by both display controllers. |
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1221 | serge | 179 | * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
1179 | serge | 180 | * the display controllers. The paritioning can either be done |
181 | * manually or via one of four preset allocations specified in bits 1:0: |
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182 | * 0 - line buffer is divided in half and shared between crtc |
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183 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 |
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184 | * 2 - D1 gets the whole buffer |
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185 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 |
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1221 | serge | 186 | * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual |
1179 | serge | 187 | * allocation mode. In manual allocation mode, D1 always starts at 0, |
188 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. |
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189 | */ |
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1221 | serge | 190 | tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; |
191 | tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; |
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1179 | serge | 192 | /* auto */ |
193 | if (mode1 && mode2) { |
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194 | if (mode1->hdisplay > mode2->hdisplay) { |
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195 | if (mode1->hdisplay > 2560) |
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1221 | serge | 196 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
1179 | serge | 197 | else |
1221 | serge | 198 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 199 | } else if (mode2->hdisplay > mode1->hdisplay) { |
200 | if (mode2->hdisplay > 2560) |
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1221 | serge | 201 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
1179 | serge | 202 | else |
1221 | serge | 203 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 204 | } else |
1221 | serge | 205 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 206 | } else if (mode1) { |
1221 | serge | 207 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; |
1179 | serge | 208 | } else if (mode2) { |
1221 | serge | 209 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
1179 | serge | 210 | } |
1221 | serge | 211 | WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); |
1179 | serge | 212 | } |
213 | |||
214 | struct rs690_watermark { |
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215 | u32 lb_request_fifo_depth; |
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216 | fixed20_12 num_line_pair; |
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217 | fixed20_12 estimated_width; |
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218 | fixed20_12 worst_case_latency; |
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219 | fixed20_12 consumption_rate; |
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220 | fixed20_12 active_time; |
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221 | fixed20_12 dbpp; |
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222 | fixed20_12 priority_mark_max; |
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223 | fixed20_12 priority_mark; |
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224 | fixed20_12 sclk; |
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225 | }; |
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226 | |||
227 | void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, |
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228 | struct radeon_crtc *crtc, |
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229 | struct rs690_watermark *wm) |
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230 | { |
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231 | struct drm_display_mode *mode = &crtc->base.mode; |
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232 | fixed20_12 a, b, c; |
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233 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
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234 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
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235 | |||
236 | if (!crtc->base.enabled) { |
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237 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
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238 | wm->lb_request_fifo_depth = 4; |
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239 | return; |
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240 | } |
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241 | |||
1963 | serge | 242 | if (crtc->vsc.full > dfixed_const(2)) |
243 | wm->num_line_pair.full = dfixed_const(2); |
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1179 | serge | 244 | else |
1963 | serge | 245 | wm->num_line_pair.full = dfixed_const(1); |
1179 | serge | 246 | |
1963 | serge | 247 | b.full = dfixed_const(mode->crtc_hdisplay); |
248 | c.full = dfixed_const(256); |
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249 | a.full = dfixed_div(b, c); |
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250 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
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251 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
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252 | if (a.full < dfixed_const(4)) { |
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1179 | serge | 253 | wm->lb_request_fifo_depth = 4; |
254 | } else { |
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1963 | serge | 255 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
1179 | serge | 256 | } |
257 | |||
258 | /* Determine consumption rate |
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259 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
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260 | * vtaps = number of vertical taps, |
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261 | * vsc = vertical scaling ratio, defined as source/destination |
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262 | * hsc = horizontal scaling ration, defined as source/destination |
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263 | */ |
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1963 | serge | 264 | a.full = dfixed_const(mode->clock); |
265 | b.full = dfixed_const(1000); |
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266 | a.full = dfixed_div(a, b); |
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267 | pclk.full = dfixed_div(b, a); |
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1179 | serge | 268 | if (crtc->rmx_type != RMX_OFF) { |
1963 | serge | 269 | b.full = dfixed_const(2); |
1179 | serge | 270 | if (crtc->vsc.full > b.full) |
271 | b.full = crtc->vsc.full; |
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1963 | serge | 272 | b.full = dfixed_mul(b, crtc->hsc); |
273 | c.full = dfixed_const(2); |
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274 | b.full = dfixed_div(b, c); |
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275 | consumption_time.full = dfixed_div(pclk, b); |
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1179 | serge | 276 | } else { |
277 | consumption_time.full = pclk.full; |
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278 | } |
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1963 | serge | 279 | a.full = dfixed_const(1); |
280 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
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1179 | serge | 281 | |
282 | |||
283 | /* Determine line time |
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284 | * LineTime = total time for one line of displayhtotal |
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285 | * LineTime = total number of horizontal pixels |
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286 | * pclk = pixel clock period(ns) |
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287 | */ |
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1963 | serge | 288 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
289 | line_time.full = dfixed_mul(a, pclk); |
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1179 | serge | 290 | |
291 | /* Determine active time |
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292 | * ActiveTime = time of active region of display within one line, |
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293 | * hactive = total number of horizontal active pixels |
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294 | * htotal = total number of horizontal pixels |
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295 | */ |
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1963 | serge | 296 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
297 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
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298 | wm->active_time.full = dfixed_mul(line_time, b); |
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299 | wm->active_time.full = dfixed_div(wm->active_time, a); |
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1179 | serge | 300 | |
301 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
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302 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
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1963 | serge | 303 | if (rdev->mc.igp_sideport_enabled) { |
1179 | serge | 304 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
305 | rdev->pm.sideport_bandwidth.full) |
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306 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
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1963 | serge | 307 | read_delay_latency.full = dfixed_const(370 * 800 * 1000); |
308 | read_delay_latency.full = dfixed_div(read_delay_latency, |
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1179 | serge | 309 | rdev->pm.igp_sideport_mclk); |
310 | } else { |
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311 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
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312 | rdev->pm.k8_bandwidth.full) |
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313 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; |
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314 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
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315 | rdev->pm.ht_bandwidth.full) |
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316 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
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1963 | serge | 317 | read_delay_latency.full = dfixed_const(5000); |
1179 | serge | 318 | } |
319 | |||
320 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
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1963 | serge | 321 | a.full = dfixed_const(16); |
322 | rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); |
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323 | a.full = dfixed_const(1000); |
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324 | rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); |
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1179 | serge | 325 | /* Determine chunk time |
326 | * ChunkTime = the time it takes the DCP to send one chunk of data |
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327 | * to the LB which consists of pipeline delay and inter chunk gap |
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328 | * sclk = system clock(ns) |
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329 | */ |
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1963 | serge | 330 | a.full = dfixed_const(256 * 13); |
331 | chunk_time.full = dfixed_mul(rdev->pm.sclk, a); |
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332 | a.full = dfixed_const(10); |
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333 | chunk_time.full = dfixed_div(chunk_time, a); |
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1179 | serge | 334 | |
335 | /* Determine the worst case latency |
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336 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
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337 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
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338 | * to return data |
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339 | * READ_DELAY_IDLE_MAX = constant of 1us |
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340 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
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341 | * which consists of pipeline delay and inter chunk gap |
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342 | */ |
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1963 | serge | 343 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
344 | a.full = dfixed_const(3); |
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345 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
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1179 | serge | 346 | wm->worst_case_latency.full += read_delay_latency.full; |
347 | } else { |
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1963 | serge | 348 | a.full = dfixed_const(2); |
349 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
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1179 | serge | 350 | wm->worst_case_latency.full += read_delay_latency.full; |
351 | } |
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352 | |||
353 | /* Determine the tolerable latency |
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354 | * TolerableLatency = Any given request has only 1 line time |
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355 | * for the data to be returned |
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356 | * LBRequestFifoDepth = Number of chunk requests the LB can |
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357 | * put into the request FIFO for a display |
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358 | * LineTime = total time for one line of display |
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359 | * ChunkTime = the time it takes the DCP to send one chunk |
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360 | * of data to the LB which consists of |
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361 | * pipeline delay and inter chunk gap |
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362 | */ |
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1963 | serge | 363 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
1179 | serge | 364 | tolerable_latency.full = line_time.full; |
365 | } else { |
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1963 | serge | 366 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
1179 | serge | 367 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
1963 | serge | 368 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
1179 | serge | 369 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
370 | } |
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371 | /* We assume worst case 32bits (4 bytes) */ |
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1963 | serge | 372 | wm->dbpp.full = dfixed_const(4 * 8); |
1179 | serge | 373 | |
374 | /* Determine the maximum priority mark |
||
375 | * width = viewport width in pixels |
||
376 | */ |
||
1963 | serge | 377 | a.full = dfixed_const(16); |
378 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
||
379 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
||
380 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
||
1179 | serge | 381 | |
382 | /* Determine estimated width */ |
||
383 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
||
1963 | serge | 384 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
385 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
||
386 | wm->priority_mark.full = dfixed_const(10); |
||
1179 | serge | 387 | } else { |
1963 | serge | 388 | a.full = dfixed_const(16); |
389 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
||
390 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
||
1179 | serge | 391 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
392 | } |
||
393 | } |
||
394 | |||
395 | void rs690_bandwidth_update(struct radeon_device *rdev) |
||
396 | { |
||
397 | struct drm_display_mode *mode0 = NULL; |
||
398 | struct drm_display_mode *mode1 = NULL; |
||
399 | struct rs690_watermark wm0; |
||
400 | struct rs690_watermark wm1; |
||
401 | u32 tmp; |
||
1963 | serge | 402 | u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); |
403 | u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); |
||
1179 | serge | 404 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
405 | fixed20_12 a, b; |
||
406 | |||
1963 | serge | 407 | radeon_update_display_priority(rdev); |
408 | |||
1179 | serge | 409 | if (rdev->mode_info.crtcs[0]->base.enabled) |
410 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
411 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
412 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
413 | /* |
||
414 | * Set display0/1 priority up in the memory controller for |
||
415 | * modes if the user specifies HIGH for displaypriority |
||
416 | * option. |
||
417 | */ |
||
1963 | serge | 418 | if ((rdev->disp_priority == 2) && |
419 | ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { |
||
1221 | serge | 420 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
421 | tmp &= C_000104_MC_DISP0R_INIT_LAT; |
||
422 | tmp &= C_000104_MC_DISP1R_INIT_LAT; |
||
423 | if (mode0) |
||
424 | tmp |= S_000104_MC_DISP0R_INIT_LAT(1); |
||
1179 | serge | 425 | if (mode1) |
1221 | serge | 426 | tmp |= S_000104_MC_DISP1R_INIT_LAT(1); |
427 | WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); |
||
1179 | serge | 428 | } |
429 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
430 | |||
431 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) |
||
1221 | serge | 432 | WREG32(R_006C9C_DCP_CONTROL, 0); |
1179 | serge | 433 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
1221 | serge | 434 | WREG32(R_006C9C_DCP_CONTROL, 2); |
1179 | serge | 435 | |
436 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
437 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
438 | |||
439 | tmp = (wm0.lb_request_fifo_depth - 1); |
||
440 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
||
1221 | serge | 441 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
1179 | serge | 442 | |
443 | if (mode0 && mode1) { |
||
1963 | serge | 444 | if (dfixed_trunc(wm0.dbpp) > 64) |
445 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 446 | else |
447 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 448 | if (dfixed_trunc(wm1.dbpp) > 64) |
449 | b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 450 | else |
451 | b.full = wm1.num_line_pair.full; |
||
452 | a.full += b.full; |
||
1963 | serge | 453 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 454 | if (wm0.consumption_rate.full > fill_rate.full) { |
455 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 456 | b.full = dfixed_mul(b, wm0.active_time); |
457 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 458 | wm0.consumption_rate); |
459 | a.full = a.full + b.full; |
||
1963 | serge | 460 | b.full = dfixed_const(16 * 1000); |
461 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 462 | } else { |
1963 | serge | 463 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 464 | wm0.consumption_rate); |
1963 | serge | 465 | b.full = dfixed_const(16 * 1000); |
466 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 467 | } |
468 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
469 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 470 | b.full = dfixed_mul(b, wm1.active_time); |
471 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 472 | wm1.consumption_rate); |
473 | a.full = a.full + b.full; |
||
1963 | serge | 474 | b.full = dfixed_const(16 * 1000); |
475 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 476 | } else { |
1963 | serge | 477 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 478 | wm1.consumption_rate); |
1963 | serge | 479 | b.full = dfixed_const(16 * 1000); |
480 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 481 | } |
482 | if (wm0.priority_mark.full > priority_mark02.full) |
||
483 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 484 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 485 | priority_mark02.full = 0; |
486 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
487 | priority_mark02.full = wm0.priority_mark_max.full; |
||
488 | if (wm1.priority_mark.full > priority_mark12.full) |
||
489 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 490 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 491 | priority_mark12.full = 0; |
492 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
493 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 494 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
495 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
||
496 | if (rdev->disp_priority == 2) { |
||
497 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
||
498 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
||
499 | } |
||
1179 | serge | 500 | } else if (mode0) { |
1963 | serge | 501 | if (dfixed_trunc(wm0.dbpp) > 64) |
502 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
1179 | serge | 503 | else |
504 | a.full = wm0.num_line_pair.full; |
||
1963 | serge | 505 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1179 | serge | 506 | if (wm0.consumption_rate.full > fill_rate.full) { |
507 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 508 | b.full = dfixed_mul(b, wm0.active_time); |
509 | a.full = dfixed_mul(wm0.worst_case_latency, |
||
1179 | serge | 510 | wm0.consumption_rate); |
511 | a.full = a.full + b.full; |
||
1963 | serge | 512 | b.full = dfixed_const(16 * 1000); |
513 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 514 | } else { |
1963 | serge | 515 | a.full = dfixed_mul(wm0.worst_case_latency, |
1179 | serge | 516 | wm0.consumption_rate); |
1963 | serge | 517 | b.full = dfixed_const(16 * 1000); |
518 | priority_mark02.full = dfixed_div(a, b); |
||
1179 | serge | 519 | } |
520 | if (wm0.priority_mark.full > priority_mark02.full) |
||
521 | priority_mark02.full = wm0.priority_mark.full; |
||
1963 | serge | 522 | if (dfixed_trunc(priority_mark02) < 0) |
1179 | serge | 523 | priority_mark02.full = 0; |
524 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
525 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1963 | serge | 526 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
527 | if (rdev->disp_priority == 2) |
||
528 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
||
529 | } else if (mode1) { |
||
530 | if (dfixed_trunc(wm1.dbpp) > 64) |
||
531 | a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
1179 | serge | 532 | else |
533 | a.full = wm1.num_line_pair.full; |
||
1963 | serge | 534 | fill_rate.full = dfixed_div(wm1.sclk, a); |
1179 | serge | 535 | if (wm1.consumption_rate.full > fill_rate.full) { |
536 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
1963 | serge | 537 | b.full = dfixed_mul(b, wm1.active_time); |
538 | a.full = dfixed_mul(wm1.worst_case_latency, |
||
1179 | serge | 539 | wm1.consumption_rate); |
540 | a.full = a.full + b.full; |
||
1963 | serge | 541 | b.full = dfixed_const(16 * 1000); |
542 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 543 | } else { |
1963 | serge | 544 | a.full = dfixed_mul(wm1.worst_case_latency, |
1179 | serge | 545 | wm1.consumption_rate); |
1963 | serge | 546 | b.full = dfixed_const(16 * 1000); |
547 | priority_mark12.full = dfixed_div(a, b); |
||
1179 | serge | 548 | } |
549 | if (wm1.priority_mark.full > priority_mark12.full) |
||
550 | priority_mark12.full = wm1.priority_mark.full; |
||
1963 | serge | 551 | if (dfixed_trunc(priority_mark12) < 0) |
1179 | serge | 552 | priority_mark12.full = 0; |
553 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
554 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1963 | serge | 555 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
556 | if (rdev->disp_priority == 2) |
||
557 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
||
1179 | serge | 558 | } |
1963 | serge | 559 | |
560 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
561 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
562 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
563 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
1179 | serge | 564 | } |
565 | |||
1128 | serge | 566 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
567 | { |
||
568 | uint32_t r; |
||
569 | |||
1221 | serge | 570 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); |
571 | r = RREG32(R_00007C_MC_DATA); |
||
572 | WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); |
||
1128 | serge | 573 | return r; |
574 | } |
||
575 | |||
576 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
577 | { |
||
1221 | serge | 578 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | |
579 | S_000078_MC_IND_WR_EN(1)); |
||
580 | WREG32(R_00007C_MC_DATA, v); |
||
581 | WREG32(R_000078_MC_INDEX, 0x7F); |
||
1128 | serge | 582 | } |
1221 | serge | 583 | |
584 | void rs690_mc_program(struct radeon_device *rdev) |
||
585 | { |
||
586 | struct rv515_mc_save save; |
||
587 | |||
588 | /* Stops all mc clients */ |
||
589 | rv515_mc_stop(rdev, &save); |
||
590 | |||
591 | /* Wait for mc idle */ |
||
592 | if (rs690_mc_wait_for_idle(rdev)) |
||
593 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
594 | /* Program MC, should be a 32bits limited address space */ |
||
595 | WREG32_MC(R_000100_MCCFG_FB_LOCATION, |
||
596 | S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
597 | S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
598 | WREG32(R_000134_HDP_FB_LOCATION, |
||
599 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
600 | |||
601 | rv515_mc_resume(rdev, &save); |
||
602 | } |
||
603 | |||
604 | static int rs690_startup(struct radeon_device *rdev) |
||
605 | { |
||
606 | int r; |
||
607 | |||
608 | rs690_mc_program(rdev); |
||
609 | /* Resume clock */ |
||
610 | rv515_clock_startup(rdev); |
||
611 | /* Initialize GPU configuration (# pipes, ...) */ |
||
612 | rs690_gpu_init(rdev); |
||
613 | /* Initialize GART (initialize after TTM so we can allocate |
||
614 | * memory through TTM but finalize after TTM) */ |
||
615 | r = rs400_gart_enable(rdev); |
||
616 | if (r) |
||
617 | return r; |
||
2005 | serge | 618 | |
619 | /* allocate wb buffer */ |
||
620 | r = radeon_wb_init(rdev); |
||
621 | if (r) |
||
622 | return r; |
||
623 | |||
1221 | serge | 624 | /* Enable IRQ */ |
2005 | serge | 625 | rs600_irq_set(rdev); |
1403 | serge | 626 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 627 | /* 1M ring buffer */ |
1413 | serge | 628 | r = r100_cp_init(rdev, 1024 * 1024); |
629 | if (r) { |
||
1963 | serge | 630 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 631 | return r; |
632 | } |
||
2005 | serge | 633 | r = r100_ib_init(rdev); |
634 | if (r) { |
||
635 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
||
636 | return r; |
||
637 | } |
||
1221 | serge | 638 | return 0; |
639 | } |
||
640 | |||
641 | |||
642 | |||
643 | |||
644 | int rs690_init(struct radeon_device *rdev) |
||
645 | { |
||
646 | int r; |
||
647 | |||
648 | /* Disable VGA */ |
||
649 | rv515_vga_render_disable(rdev); |
||
650 | /* Initialize scratch registers */ |
||
651 | radeon_scratch_init(rdev); |
||
652 | /* Initialize surface registers */ |
||
653 | radeon_surface_init(rdev); |
||
1963 | serge | 654 | /* restore some register to sane defaults */ |
655 | r100_restore_sanity(rdev); |
||
1221 | serge | 656 | /* TODO: disable VGA need to use VGA request */ |
657 | /* BIOS*/ |
||
658 | if (!radeon_get_bios(rdev)) { |
||
659 | if (ASIC_IS_AVIVO(rdev)) |
||
660 | return -EINVAL; |
||
661 | } |
||
662 | if (rdev->is_atom_bios) { |
||
663 | r = radeon_atombios_init(rdev); |
||
664 | if (r) |
||
665 | return r; |
||
666 | } else { |
||
667 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
668 | return -EINVAL; |
||
669 | } |
||
670 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 671 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 672 | dev_warn(rdev->dev, |
673 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
674 | RREG32(R_000E40_RBBM_STATUS), |
||
675 | RREG32(R_0007C0_CP_STAT)); |
||
676 | } |
||
677 | /* check if cards are posted or not */ |
||
1403 | serge | 678 | if (radeon_boot_test_post_card(rdev) == false) |
679 | return -EINVAL; |
||
680 | |||
1221 | serge | 681 | /* Initialize clocks */ |
682 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 683 | /* initialize memory controller */ |
684 | rs690_mc_init(rdev); |
||
1221 | serge | 685 | rv515_debugfs(rdev); |
686 | /* Fence driver */ |
||
2005 | serge | 687 | r = radeon_fence_driver_init(rdev); |
688 | if (r) |
||
689 | return r; |
||
690 | r = radeon_irq_kms_init(rdev); |
||
691 | if (r) |
||
692 | return r; |
||
1221 | serge | 693 | /* Memory manager */ |
1403 | serge | 694 | r = radeon_bo_init(rdev); |
1221 | serge | 695 | if (r) |
696 | return r; |
||
697 | r = rs400_gart_init(rdev); |
||
698 | if (r) |
||
699 | return r; |
||
700 | rs600_set_safe_registers(rdev); |
||
701 | rdev->accel_working = true; |
||
702 | r = rs690_startup(rdev); |
||
703 | if (r) { |
||
704 | /* Somethings want wront with the accel init stop accel */ |
||
705 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
706 | // r100_cp_fini(rdev); |
||
707 | // r100_wb_fini(rdev); |
||
708 | // r100_ib_fini(rdev); |
||
709 | rs400_gart_fini(rdev); |
||
710 | // radeon_irq_kms_fini(rdev); |
||
711 | rdev->accel_working = false; |
||
712 | } |
||
713 | return 0; |
||
714 | }>>>>><>>><>>> |