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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include "drmP.h" |
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29 | #include "radeon.h" |
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1179 | serge | 30 | #include "atom.h" |
1221 | serge | 31 | #include "rs690d.h" |
1128 | serge | 32 | |
1221 | serge | 33 | static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
1128 | serge | 34 | { |
35 | unsigned i; |
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36 | uint32_t tmp; |
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37 | |||
38 | for (i = 0; i < rdev->usec_timeout; i++) { |
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39 | /* read MC_STATUS */ |
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1221 | serge | 40 | tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); |
41 | if (G_000090_MC_SYSTEM_IDLE(tmp)) |
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1128 | serge | 42 | return 0; |
1221 | serge | 43 | udelay(1); |
1128 | serge | 44 | } |
45 | return -1; |
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46 | } |
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47 | |||
1221 | serge | 48 | static void rs690_gpu_init(struct radeon_device *rdev) |
1128 | serge | 49 | { |
50 | /* FIXME: HDP same place on rs690 ? */ |
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51 | r100_hdp_reset(rdev); |
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52 | /* FIXME: is this correct ? */ |
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53 | r420_pipes_init(rdev); |
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54 | if (rs690_mc_wait_for_idle(rdev)) { |
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55 | printk(KERN_WARNING "Failed to wait MC idle while " |
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56 | "programming pipes. Bad things might happen.\n"); |
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57 | } |
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58 | } |
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59 | |||
1179 | serge | 60 | void rs690_pm_info(struct radeon_device *rdev) |
61 | { |
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62 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
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63 | struct _ATOM_INTEGRATED_SYSTEM_INFO *info; |
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64 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2; |
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65 | void *ptr; |
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66 | uint16_t data_offset; |
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67 | uint8_t frev, crev; |
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68 | fixed20_12 tmp; |
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69 | |||
70 | atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
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71 | &frev, &crev, &data_offset); |
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72 | ptr = rdev->mode_info.atom_context->bios + data_offset; |
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73 | info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; |
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74 | info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; |
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75 | /* Get various system informations from bios */ |
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76 | switch (crev) { |
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77 | case 1: |
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78 | tmp.full = rfixed_const(100); |
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79 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); |
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80 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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81 | rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); |
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82 | rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); |
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83 | rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); |
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84 | break; |
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85 | case 2: |
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86 | tmp.full = rfixed_const(100); |
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87 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); |
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88 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
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89 | rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); |
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90 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
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91 | rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); |
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92 | rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
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93 | rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); |
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94 | break; |
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95 | default: |
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96 | tmp.full = rfixed_const(100); |
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97 | /* We assume the slower possible clock ie worst case */ |
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98 | /* DDR 333Mhz */ |
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99 | rdev->pm.igp_sideport_mclk.full = rfixed_const(333); |
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100 | /* FIXME: system clock ? */ |
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101 | rdev->pm.igp_system_mclk.full = rfixed_const(100); |
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102 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
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103 | rdev->pm.igp_ht_link_clk.full = rfixed_const(200); |
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104 | rdev->pm.igp_ht_link_width.full = rfixed_const(8); |
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105 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
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106 | break; |
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107 | } |
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108 | /* Compute various bandwidth */ |
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109 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
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110 | tmp.full = rfixed_const(4); |
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111 | rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); |
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112 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
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113 | * = ht_clk * ht_width / 5 |
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114 | */ |
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115 | tmp.full = rfixed_const(5); |
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116 | rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, |
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117 | rdev->pm.igp_ht_link_width); |
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118 | rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); |
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119 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
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120 | /* HT link is a limiting factor */ |
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121 | rdev->pm.max_bandwidth.full = tmp.full; |
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122 | } |
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123 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
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124 | * = (sideport_clk * 14) / 10 |
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125 | */ |
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126 | tmp.full = rfixed_const(14); |
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127 | rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); |
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128 | tmp.full = rfixed_const(10); |
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129 | rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); |
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130 | } |
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131 | |||
1128 | serge | 132 | void rs690_vram_info(struct radeon_device *rdev) |
133 | { |
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134 | uint32_t tmp; |
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1179 | serge | 135 | fixed20_12 a; |
1128 | serge | 136 | |
137 | rs400_gart_adjust_size(rdev); |
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138 | /* DDR for all card after R300 & IGP */ |
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139 | rdev->mc.vram_is_ddr = true; |
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140 | /* FIXME: is this correct for RS690/RS740 ? */ |
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141 | tmp = RREG32(RADEON_MEM_CNTL); |
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142 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
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143 | rdev->mc.vram_width = 128; |
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144 | } else { |
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145 | rdev->mc.vram_width = 64; |
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146 | } |
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1179 | serge | 147 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
148 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
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1128 | serge | 149 | |
150 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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151 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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1179 | serge | 152 | rs690_pm_info(rdev); |
153 | /* FIXME: we should enforce default clock in case GPU is not in |
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154 | * default setup |
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155 | */ |
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156 | a.full = rfixed_const(100); |
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157 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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158 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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159 | a.full = rfixed_const(16); |
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160 | /* core_bandwidth = sclk(Mhz) * 16 */ |
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161 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); |
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1128 | serge | 162 | } |
163 | |||
1179 | serge | 164 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
165 | struct drm_display_mode *mode1, |
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166 | struct drm_display_mode *mode2) |
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167 | { |
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168 | u32 tmp; |
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1128 | serge | 169 | |
1179 | serge | 170 | /* |
171 | * Line Buffer Setup |
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172 | * There is a single line buffer shared by both display controllers. |
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1221 | serge | 173 | * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
1179 | serge | 174 | * the display controllers. The paritioning can either be done |
175 | * manually or via one of four preset allocations specified in bits 1:0: |
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176 | * 0 - line buffer is divided in half and shared between crtc |
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177 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 |
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178 | * 2 - D1 gets the whole buffer |
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179 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 |
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1221 | serge | 180 | * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual |
1179 | serge | 181 | * allocation mode. In manual allocation mode, D1 always starts at 0, |
182 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. |
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183 | */ |
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1221 | serge | 184 | tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; |
185 | tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; |
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1179 | serge | 186 | /* auto */ |
187 | if (mode1 && mode2) { |
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188 | if (mode1->hdisplay > mode2->hdisplay) { |
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189 | if (mode1->hdisplay > 2560) |
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1221 | serge | 190 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
1179 | serge | 191 | else |
1221 | serge | 192 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 193 | } else if (mode2->hdisplay > mode1->hdisplay) { |
194 | if (mode2->hdisplay > 2560) |
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1221 | serge | 195 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
1179 | serge | 196 | else |
1221 | serge | 197 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 198 | } else |
1221 | serge | 199 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
1179 | serge | 200 | } else if (mode1) { |
1221 | serge | 201 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; |
1179 | serge | 202 | } else if (mode2) { |
1221 | serge | 203 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
1179 | serge | 204 | } |
1221 | serge | 205 | WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); |
1179 | serge | 206 | } |
207 | |||
208 | struct rs690_watermark { |
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209 | u32 lb_request_fifo_depth; |
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210 | fixed20_12 num_line_pair; |
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211 | fixed20_12 estimated_width; |
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212 | fixed20_12 worst_case_latency; |
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213 | fixed20_12 consumption_rate; |
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214 | fixed20_12 active_time; |
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215 | fixed20_12 dbpp; |
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216 | fixed20_12 priority_mark_max; |
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217 | fixed20_12 priority_mark; |
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218 | fixed20_12 sclk; |
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219 | }; |
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220 | |||
221 | void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, |
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222 | struct radeon_crtc *crtc, |
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223 | struct rs690_watermark *wm) |
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224 | { |
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225 | struct drm_display_mode *mode = &crtc->base.mode; |
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226 | fixed20_12 a, b, c; |
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227 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
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228 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
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229 | /* FIXME: detect IGP with sideport memory, i don't think there is any |
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230 | * such product available |
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231 | */ |
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232 | bool sideport = false; |
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233 | |||
234 | if (!crtc->base.enabled) { |
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235 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
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236 | wm->lb_request_fifo_depth = 4; |
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237 | return; |
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238 | } |
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239 | |||
240 | if (crtc->vsc.full > rfixed_const(2)) |
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241 | wm->num_line_pair.full = rfixed_const(2); |
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242 | else |
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243 | wm->num_line_pair.full = rfixed_const(1); |
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244 | |||
245 | b.full = rfixed_const(mode->crtc_hdisplay); |
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246 | c.full = rfixed_const(256); |
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247 | a.full = rfixed_mul(wm->num_line_pair, b); |
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248 | request_fifo_depth.full = rfixed_div(a, c); |
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249 | if (a.full < rfixed_const(4)) { |
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250 | wm->lb_request_fifo_depth = 4; |
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251 | } else { |
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252 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
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253 | } |
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254 | |||
255 | /* Determine consumption rate |
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256 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
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257 | * vtaps = number of vertical taps, |
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258 | * vsc = vertical scaling ratio, defined as source/destination |
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259 | * hsc = horizontal scaling ration, defined as source/destination |
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260 | */ |
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261 | a.full = rfixed_const(mode->clock); |
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262 | b.full = rfixed_const(1000); |
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263 | a.full = rfixed_div(a, b); |
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264 | pclk.full = rfixed_div(b, a); |
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265 | if (crtc->rmx_type != RMX_OFF) { |
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266 | b.full = rfixed_const(2); |
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267 | if (crtc->vsc.full > b.full) |
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268 | b.full = crtc->vsc.full; |
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269 | b.full = rfixed_mul(b, crtc->hsc); |
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270 | c.full = rfixed_const(2); |
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271 | b.full = rfixed_div(b, c); |
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272 | consumption_time.full = rfixed_div(pclk, b); |
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273 | } else { |
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274 | consumption_time.full = pclk.full; |
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275 | } |
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276 | a.full = rfixed_const(1); |
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277 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
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278 | |||
279 | |||
280 | /* Determine line time |
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281 | * LineTime = total time for one line of displayhtotal |
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282 | * LineTime = total number of horizontal pixels |
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283 | * pclk = pixel clock period(ns) |
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284 | */ |
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285 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
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286 | line_time.full = rfixed_mul(a, pclk); |
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287 | |||
288 | /* Determine active time |
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289 | * ActiveTime = time of active region of display within one line, |
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290 | * hactive = total number of horizontal active pixels |
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291 | * htotal = total number of horizontal pixels |
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292 | */ |
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293 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
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294 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
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295 | wm->active_time.full = rfixed_mul(line_time, b); |
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296 | wm->active_time.full = rfixed_div(wm->active_time, a); |
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297 | |||
298 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
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299 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
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300 | if (sideport) { |
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301 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
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302 | rdev->pm.sideport_bandwidth.full) |
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303 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
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304 | read_delay_latency.full = rfixed_const(370 * 800 * 1000); |
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305 | read_delay_latency.full = rfixed_div(read_delay_latency, |
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306 | rdev->pm.igp_sideport_mclk); |
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307 | } else { |
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308 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
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309 | rdev->pm.k8_bandwidth.full) |
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310 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; |
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311 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
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312 | rdev->pm.ht_bandwidth.full) |
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313 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
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314 | read_delay_latency.full = rfixed_const(5000); |
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315 | } |
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316 | |||
317 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
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318 | a.full = rfixed_const(16); |
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319 | rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); |
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320 | a.full = rfixed_const(1000); |
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321 | rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); |
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322 | /* Determine chunk time |
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323 | * ChunkTime = the time it takes the DCP to send one chunk of data |
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324 | * to the LB which consists of pipeline delay and inter chunk gap |
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325 | * sclk = system clock(ns) |
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326 | */ |
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327 | a.full = rfixed_const(256 * 13); |
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328 | chunk_time.full = rfixed_mul(rdev->pm.sclk, a); |
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329 | a.full = rfixed_const(10); |
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330 | chunk_time.full = rfixed_div(chunk_time, a); |
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331 | |||
332 | /* Determine the worst case latency |
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333 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
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334 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
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335 | * to return data |
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336 | * READ_DELAY_IDLE_MAX = constant of 1us |
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337 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
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338 | * which consists of pipeline delay and inter chunk gap |
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339 | */ |
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340 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
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341 | a.full = rfixed_const(3); |
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342 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
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343 | wm->worst_case_latency.full += read_delay_latency.full; |
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344 | } else { |
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345 | a.full = rfixed_const(2); |
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346 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
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347 | wm->worst_case_latency.full += read_delay_latency.full; |
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348 | } |
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349 | |||
350 | /* Determine the tolerable latency |
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351 | * TolerableLatency = Any given request has only 1 line time |
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352 | * for the data to be returned |
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353 | * LBRequestFifoDepth = Number of chunk requests the LB can |
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354 | * put into the request FIFO for a display |
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355 | * LineTime = total time for one line of display |
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356 | * ChunkTime = the time it takes the DCP to send one chunk |
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357 | * of data to the LB which consists of |
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358 | * pipeline delay and inter chunk gap |
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359 | */ |
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360 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
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361 | tolerable_latency.full = line_time.full; |
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362 | } else { |
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363 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
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364 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
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365 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
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366 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
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367 | } |
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368 | /* We assume worst case 32bits (4 bytes) */ |
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369 | wm->dbpp.full = rfixed_const(4 * 8); |
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370 | |||
371 | /* Determine the maximum priority mark |
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372 | * width = viewport width in pixels |
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373 | */ |
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374 | a.full = rfixed_const(16); |
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375 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
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376 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
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377 | |||
378 | /* Determine estimated width */ |
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379 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
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380 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
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381 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
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382 | wm->priority_mark.full = rfixed_const(10); |
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383 | } else { |
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384 | a.full = rfixed_const(16); |
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385 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
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386 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
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387 | } |
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388 | } |
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389 | |||
390 | void rs690_bandwidth_update(struct radeon_device *rdev) |
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391 | { |
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392 | struct drm_display_mode *mode0 = NULL; |
||
393 | struct drm_display_mode *mode1 = NULL; |
||
394 | struct rs690_watermark wm0; |
||
395 | struct rs690_watermark wm1; |
||
396 | u32 tmp; |
||
397 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
||
398 | fixed20_12 a, b; |
||
399 | |||
400 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
401 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
402 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
403 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
404 | /* |
||
405 | * Set display0/1 priority up in the memory controller for |
||
406 | * modes if the user specifies HIGH for displaypriority |
||
407 | * option. |
||
408 | */ |
||
409 | if (rdev->disp_priority == 2) { |
||
1221 | serge | 410 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
411 | tmp &= C_000104_MC_DISP0R_INIT_LAT; |
||
412 | tmp &= C_000104_MC_DISP1R_INIT_LAT; |
||
413 | if (mode0) |
||
414 | tmp |= S_000104_MC_DISP0R_INIT_LAT(1); |
||
1179 | serge | 415 | if (mode1) |
1221 | serge | 416 | tmp |= S_000104_MC_DISP1R_INIT_LAT(1); |
417 | WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); |
||
1179 | serge | 418 | } |
419 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
420 | |||
421 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) |
||
1221 | serge | 422 | WREG32(R_006C9C_DCP_CONTROL, 0); |
1179 | serge | 423 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
1221 | serge | 424 | WREG32(R_006C9C_DCP_CONTROL, 2); |
1179 | serge | 425 | |
426 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
||
427 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
||
428 | |||
429 | tmp = (wm0.lb_request_fifo_depth - 1); |
||
430 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
||
1221 | serge | 431 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
1179 | serge | 432 | |
433 | if (mode0 && mode1) { |
||
434 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
435 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
436 | else |
||
437 | a.full = wm0.num_line_pair.full; |
||
438 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
439 | b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
440 | else |
||
441 | b.full = wm1.num_line_pair.full; |
||
442 | a.full += b.full; |
||
443 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
444 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
445 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
446 | b.full = rfixed_mul(b, wm0.active_time); |
||
447 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
448 | wm0.consumption_rate); |
||
449 | a.full = a.full + b.full; |
||
450 | b.full = rfixed_const(16 * 1000); |
||
451 | priority_mark02.full = rfixed_div(a, b); |
||
452 | } else { |
||
453 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
454 | wm0.consumption_rate); |
||
455 | b.full = rfixed_const(16 * 1000); |
||
456 | priority_mark02.full = rfixed_div(a, b); |
||
457 | } |
||
458 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
459 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
460 | b.full = rfixed_mul(b, wm1.active_time); |
||
461 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
462 | wm1.consumption_rate); |
||
463 | a.full = a.full + b.full; |
||
464 | b.full = rfixed_const(16 * 1000); |
||
465 | priority_mark12.full = rfixed_div(a, b); |
||
466 | } else { |
||
467 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
468 | wm1.consumption_rate); |
||
469 | b.full = rfixed_const(16 * 1000); |
||
470 | priority_mark12.full = rfixed_div(a, b); |
||
471 | } |
||
472 | if (wm0.priority_mark.full > priority_mark02.full) |
||
473 | priority_mark02.full = wm0.priority_mark.full; |
||
474 | if (rfixed_trunc(priority_mark02) < 0) |
||
475 | priority_mark02.full = 0; |
||
476 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
477 | priority_mark02.full = wm0.priority_mark_max.full; |
||
478 | if (wm1.priority_mark.full > priority_mark12.full) |
||
479 | priority_mark12.full = wm1.priority_mark.full; |
||
480 | if (rfixed_trunc(priority_mark12) < 0) |
||
481 | priority_mark12.full = 0; |
||
482 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
483 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1221 | serge | 484 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
485 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
486 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
487 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
1179 | serge | 488 | } else if (mode0) { |
489 | if (rfixed_trunc(wm0.dbpp) > 64) |
||
490 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
||
491 | else |
||
492 | a.full = wm0.num_line_pair.full; |
||
493 | fill_rate.full = rfixed_div(wm0.sclk, a); |
||
494 | if (wm0.consumption_rate.full > fill_rate.full) { |
||
495 | b.full = wm0.consumption_rate.full - fill_rate.full; |
||
496 | b.full = rfixed_mul(b, wm0.active_time); |
||
497 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
498 | wm0.consumption_rate); |
||
499 | a.full = a.full + b.full; |
||
500 | b.full = rfixed_const(16 * 1000); |
||
501 | priority_mark02.full = rfixed_div(a, b); |
||
502 | } else { |
||
503 | a.full = rfixed_mul(wm0.worst_case_latency, |
||
504 | wm0.consumption_rate); |
||
505 | b.full = rfixed_const(16 * 1000); |
||
506 | priority_mark02.full = rfixed_div(a, b); |
||
507 | } |
||
508 | if (wm0.priority_mark.full > priority_mark02.full) |
||
509 | priority_mark02.full = wm0.priority_mark.full; |
||
510 | if (rfixed_trunc(priority_mark02) < 0) |
||
511 | priority_mark02.full = 0; |
||
512 | if (wm0.priority_mark_max.full > priority_mark02.full) |
||
513 | priority_mark02.full = wm0.priority_mark_max.full; |
||
1221 | serge | 514 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
515 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
||
516 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, |
||
517 | S_006D48_D2MODE_PRIORITY_A_OFF(1)); |
||
518 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, |
||
519 | S_006D4C_D2MODE_PRIORITY_B_OFF(1)); |
||
1179 | serge | 520 | } else { |
521 | if (rfixed_trunc(wm1.dbpp) > 64) |
||
522 | a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
||
523 | else |
||
524 | a.full = wm1.num_line_pair.full; |
||
525 | fill_rate.full = rfixed_div(wm1.sclk, a); |
||
526 | if (wm1.consumption_rate.full > fill_rate.full) { |
||
527 | b.full = wm1.consumption_rate.full - fill_rate.full; |
||
528 | b.full = rfixed_mul(b, wm1.active_time); |
||
529 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
530 | wm1.consumption_rate); |
||
531 | a.full = a.full + b.full; |
||
532 | b.full = rfixed_const(16 * 1000); |
||
533 | priority_mark12.full = rfixed_div(a, b); |
||
534 | } else { |
||
535 | a.full = rfixed_mul(wm1.worst_case_latency, |
||
536 | wm1.consumption_rate); |
||
537 | b.full = rfixed_const(16 * 1000); |
||
538 | priority_mark12.full = rfixed_div(a, b); |
||
539 | } |
||
540 | if (wm1.priority_mark.full > priority_mark12.full) |
||
541 | priority_mark12.full = wm1.priority_mark.full; |
||
542 | if (rfixed_trunc(priority_mark12) < 0) |
||
543 | priority_mark12.full = 0; |
||
544 | if (wm1.priority_mark_max.full > priority_mark12.full) |
||
545 | priority_mark12.full = wm1.priority_mark_max.full; |
||
1221 | serge | 546 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, |
547 | S_006548_D1MODE_PRIORITY_A_OFF(1)); |
||
548 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, |
||
549 | S_00654C_D1MODE_PRIORITY_B_OFF(1)); |
||
550 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
||
551 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
||
1179 | serge | 552 | } |
553 | } |
||
554 | |||
1128 | serge | 555 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
556 | { |
||
557 | uint32_t r; |
||
558 | |||
1221 | serge | 559 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); |
560 | r = RREG32(R_00007C_MC_DATA); |
||
561 | WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); |
||
1128 | serge | 562 | return r; |
563 | } |
||
564 | |||
565 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
566 | { |
||
1221 | serge | 567 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | |
568 | S_000078_MC_IND_WR_EN(1)); |
||
569 | WREG32(R_00007C_MC_DATA, v); |
||
570 | WREG32(R_000078_MC_INDEX, 0x7F); |
||
1128 | serge | 571 | } |
1221 | serge | 572 | |
573 | void rs690_mc_program(struct radeon_device *rdev) |
||
574 | { |
||
575 | struct rv515_mc_save save; |
||
576 | |||
577 | /* Stops all mc clients */ |
||
578 | rv515_mc_stop(rdev, &save); |
||
579 | |||
580 | /* Wait for mc idle */ |
||
581 | if (rs690_mc_wait_for_idle(rdev)) |
||
582 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
583 | /* Program MC, should be a 32bits limited address space */ |
||
584 | WREG32_MC(R_000100_MCCFG_FB_LOCATION, |
||
585 | S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
586 | S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
587 | WREG32(R_000134_HDP_FB_LOCATION, |
||
588 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
589 | |||
590 | rv515_mc_resume(rdev, &save); |
||
591 | } |
||
592 | |||
593 | static int rs690_startup(struct radeon_device *rdev) |
||
594 | { |
||
595 | int r; |
||
596 | |||
597 | rs690_mc_program(rdev); |
||
598 | /* Resume clock */ |
||
599 | rv515_clock_startup(rdev); |
||
600 | /* Initialize GPU configuration (# pipes, ...) */ |
||
601 | rs690_gpu_init(rdev); |
||
602 | /* Initialize GART (initialize after TTM so we can allocate |
||
603 | * memory through TTM but finalize after TTM) */ |
||
604 | r = rs400_gart_enable(rdev); |
||
605 | if (r) |
||
606 | return r; |
||
607 | /* Enable IRQ */ |
||
608 | // rdev->irq.sw_int = true; |
||
609 | // rs600_irq_set(rdev); |
||
610 | /* 1M ring buffer */ |
||
611 | // r = r100_cp_init(rdev, 1024 * 1024); |
||
612 | // if (r) { |
||
613 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
||
614 | // return r; |
||
615 | // } |
||
616 | // r = r100_wb_init(rdev); |
||
617 | // if (r) |
||
618 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
||
619 | // r = r100_ib_init(rdev); |
||
620 | // if (r) { |
||
621 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
||
622 | // return r; |
||
623 | // } |
||
624 | return 0; |
||
625 | } |
||
626 | |||
627 | |||
628 | |||
629 | |||
630 | int rs690_init(struct radeon_device *rdev) |
||
631 | { |
||
632 | int r; |
||
633 | |||
634 | /* Disable VGA */ |
||
635 | rv515_vga_render_disable(rdev); |
||
636 | /* Initialize scratch registers */ |
||
637 | radeon_scratch_init(rdev); |
||
638 | /* Initialize surface registers */ |
||
639 | radeon_surface_init(rdev); |
||
640 | /* TODO: disable VGA need to use VGA request */ |
||
641 | /* BIOS*/ |
||
642 | if (!radeon_get_bios(rdev)) { |
||
643 | if (ASIC_IS_AVIVO(rdev)) |
||
644 | return -EINVAL; |
||
645 | } |
||
646 | if (rdev->is_atom_bios) { |
||
647 | r = radeon_atombios_init(rdev); |
||
648 | if (r) |
||
649 | return r; |
||
650 | } else { |
||
651 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
||
652 | return -EINVAL; |
||
653 | } |
||
654 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
655 | if (radeon_gpu_reset(rdev)) { |
||
656 | dev_warn(rdev->dev, |
||
657 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
658 | RREG32(R_000E40_RBBM_STATUS), |
||
659 | RREG32(R_0007C0_CP_STAT)); |
||
660 | } |
||
661 | /* check if cards are posted or not */ |
||
662 | if (!radeon_card_posted(rdev) && rdev->bios) { |
||
663 | DRM_INFO("GPU not posted. posting now...\n"); |
||
664 | atom_asic_init(rdev->mode_info.atom_context); |
||
665 | } |
||
666 | /* Initialize clocks */ |
||
667 | radeon_get_clock_info(rdev->ddev); |
||
668 | /* Get vram informations */ |
||
669 | rs690_vram_info(rdev); |
||
670 | /* Initialize memory controller (also test AGP) */ |
||
671 | r = r420_mc_init(rdev); |
||
672 | if (r) |
||
673 | return r; |
||
674 | rv515_debugfs(rdev); |
||
675 | /* Fence driver */ |
||
676 | // r = radeon_fence_driver_init(rdev); |
||
677 | // if (r) |
||
678 | // return r; |
||
679 | // r = radeon_irq_kms_init(rdev); |
||
680 | // if (r) |
||
681 | // return r; |
||
682 | /* Memory manager */ |
||
683 | r = radeon_object_init(rdev); |
||
684 | if (r) |
||
685 | return r; |
||
686 | r = rs400_gart_init(rdev); |
||
687 | if (r) |
||
688 | return r; |
||
689 | rs600_set_safe_registers(rdev); |
||
690 | rdev->accel_working = true; |
||
691 | r = rs690_startup(rdev); |
||
692 | if (r) { |
||
693 | /* Somethings want wront with the accel init stop accel */ |
||
694 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
695 | // rs690_suspend(rdev); |
||
696 | // r100_cp_fini(rdev); |
||
697 | // r100_wb_fini(rdev); |
||
698 | // r100_ib_fini(rdev); |
||
699 | rs400_gart_fini(rdev); |
||
700 | // radeon_irq_kms_fini(rdev); |
||
701 | rdev->accel_working = false; |
||
702 | } |
||
703 | return 0; |
||
704 | }>>>>><>>>> |