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1221 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RS600D_H__ |
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29 | #define __RS600D_H__ |
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30 | |||
31 | /* Registers */ |
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32 | #define R_000040_GEN_INT_CNTL 0x000040 |
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1321 | serge | 33 | #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) |
34 | #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) |
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35 | #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF |
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36 | #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) |
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37 | #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) |
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38 | #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF |
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1221 | serge | 39 | #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) |
40 | #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) |
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41 | #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF |
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42 | #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) |
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43 | #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) |
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44 | #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF |
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45 | #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) |
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46 | #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) |
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47 | #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF |
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48 | #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) |
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49 | #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) |
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50 | #define C_000040_I2C_INT_EN 0xFFFDFFFF |
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51 | #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) |
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52 | #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) |
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53 | #define C_000040_GUI_IDLE 0xFFF7FFFF |
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54 | #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) |
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55 | #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) |
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56 | #define C_000040_VIPH_INT_EN 0xFEFFFFFF |
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57 | #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) |
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58 | #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) |
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59 | #define C_000040_SW_INT_EN 0xFDFFFFFF |
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60 | #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) |
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61 | #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) |
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62 | #define C_000040_GEYSERVILLE 0xF7FFFFFF |
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63 | #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) |
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64 | #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) |
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65 | #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF |
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66 | #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) |
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67 | #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) |
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68 | #define C_000040_DVI_I2C_INT 0xDFFFFFFF |
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69 | #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) |
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70 | #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) |
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71 | #define C_000040_GUIDMA 0xBFFFFFFF |
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72 | #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) |
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73 | #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) |
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74 | #define C_000040_VIDDMA 0x7FFFFFFF |
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75 | #define R_000044_GEN_INT_STATUS 0x000044 |
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76 | #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0) |
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77 | #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1) |
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78 | #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE |
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79 | #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1) |
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80 | #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1) |
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81 | #define C_000044_VGA_INT_STAT 0xFFFFFFFD |
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82 | #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) |
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83 | #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) |
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84 | #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF |
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85 | #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) |
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86 | #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) |
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87 | #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF |
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88 | #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) |
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89 | #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) |
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90 | #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF |
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91 | #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) |
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92 | #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) |
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93 | #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF |
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94 | #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) |
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95 | #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) |
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96 | #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF |
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97 | #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16) |
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98 | #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1) |
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99 | #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF |
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100 | #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) |
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101 | #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) |
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102 | #define C_000044_I2C_INT 0xFFFDFFFF |
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103 | #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18) |
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104 | #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1) |
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105 | #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF |
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106 | #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) |
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107 | #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) |
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108 | #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF |
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109 | #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20) |
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110 | #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1) |
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111 | #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF |
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112 | #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21) |
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113 | #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1) |
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114 | #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF |
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115 | #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22) |
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116 | #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1) |
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117 | #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF |
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118 | #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23) |
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119 | #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1) |
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120 | #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF |
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121 | #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) |
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122 | #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) |
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123 | #define C_000044_VIPH_INT 0xFEFFFFFF |
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124 | #define S_000044_SW_INT(x) (((x) & 0x1) << 25) |
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125 | #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) |
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126 | #define C_000044_SW_INT 0xFDFFFFFF |
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127 | #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) |
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128 | #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) |
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129 | #define C_000044_SW_INT_SET 0xFBFFFFFF |
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130 | #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27) |
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131 | #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1) |
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132 | #define C_000044_IDCT_INT_STAT 0xF7FFFFFF |
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133 | #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) |
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134 | #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) |
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135 | #define C_000044_GUIDMA_STAT 0xBFFFFFFF |
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136 | #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) |
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137 | #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) |
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138 | #define C_000044_VIDDMA_STAT 0x7FFFFFFF |
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139 | #define R_00004C_BUS_CNTL 0x00004C |
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140 | #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) |
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141 | #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) |
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142 | #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF |
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143 | #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) |
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144 | #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) |
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145 | #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF |
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146 | #define R_000070_MC_IND_INDEX 0x000070 |
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147 | #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) |
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148 | #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) |
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149 | #define C_000070_MC_IND_ADDR 0xFFFF0000 |
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150 | #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) |
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151 | #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) |
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152 | #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF |
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153 | #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) |
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154 | #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) |
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155 | #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF |
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156 | #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) |
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157 | #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) |
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158 | #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF |
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159 | #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) |
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160 | #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) |
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161 | #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF |
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162 | #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) |
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163 | #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) |
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164 | #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF |
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165 | #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) |
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166 | #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) |
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167 | #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF |
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168 | #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) |
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169 | #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) |
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170 | #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF |
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171 | #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) |
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172 | #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) |
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173 | #define C_000070_MC_IND_WR_EN 0xFF7FFFFF |
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174 | #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) |
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175 | #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) |
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176 | #define C_000070_MC_IND_RD_INV 0xFEFFFFFF |
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177 | #define R_000074_MC_IND_DATA 0x000074 |
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178 | #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) |
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179 | #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) |
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180 | #define C_000074_MC_IND_DATA 0x00000000 |
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181 | #define R_000134_HDP_FB_LOCATION 0x000134 |
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182 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) |
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183 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) |
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184 | #define C_000134_HDP_FB_START 0xFFFF0000 |
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185 | #define R_0007C0_CP_STAT 0x0007C0 |
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186 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
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187 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
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188 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
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189 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
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190 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
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191 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
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192 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
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193 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
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194 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
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195 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
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196 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
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197 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
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198 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
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199 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
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200 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
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201 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
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202 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
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203 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
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204 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
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205 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
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206 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
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207 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
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208 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
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209 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
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210 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
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211 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
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212 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
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213 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) |
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214 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) |
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215 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF |
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216 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) |
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217 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) |
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218 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF |
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219 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
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220 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
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221 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
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222 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
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223 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
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224 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
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225 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
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226 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
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227 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
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228 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
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229 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
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230 | #define C_0007C0_CP_BUSY 0x7FFFFFFF |
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231 | #define R_000E40_RBBM_STATUS 0x000E40 |
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232 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
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233 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
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234 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
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235 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
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236 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) |
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237 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF |
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238 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) |
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239 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) |
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240 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF |
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241 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) |
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242 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) |
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243 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF |
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244 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) |
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245 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) |
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246 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF |
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247 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) |
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248 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) |
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249 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF |
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250 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) |
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251 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) |
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252 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF |
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253 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) |
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254 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) |
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255 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF |
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256 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) |
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257 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) |
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258 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF |
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259 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) |
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260 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) |
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261 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF |
||
262 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) |
||
263 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) |
||
264 | #define C_000E40_E2_BUSY 0xFFFDFFFF |
||
265 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) |
||
266 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) |
||
267 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF |
||
268 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) |
||
269 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) |
||
270 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF |
||
271 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) |
||
272 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) |
||
273 | #define C_000E40_VAP_BUSY 0xFFEFFFFF |
||
274 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) |
||
275 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) |
||
276 | #define C_000E40_RE_BUSY 0xFFDFFFFF |
||
277 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) |
||
278 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) |
||
279 | #define C_000E40_TAM_BUSY 0xFFBFFFFF |
||
280 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) |
||
281 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) |
||
282 | #define C_000E40_TDM_BUSY 0xFF7FFFFF |
||
283 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) |
||
284 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) |
||
285 | #define C_000E40_PB_BUSY 0xFEFFFFFF |
||
286 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) |
||
287 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) |
||
288 | #define C_000E40_TIM_BUSY 0xFDFFFFFF |
||
289 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) |
||
290 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) |
||
291 | #define C_000E40_GA_BUSY 0xFBFFFFFF |
||
292 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) |
||
293 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) |
||
294 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF |
||
295 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
||
296 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
||
297 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
||
298 | #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 |
||
299 | #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) |
||
300 | #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) |
||
301 | #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 |
||
302 | #define R_006534_D1MODE_VBLANK_STATUS 0x006534 |
||
303 | #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) |
||
304 | #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) |
||
305 | #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE |
||
306 | #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) |
||
307 | #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) |
||
308 | #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF |
||
309 | #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) |
||
310 | #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) |
||
311 | #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF |
||
312 | #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) |
||
313 | #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) |
||
314 | #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF |
||
315 | #define R_006540_DxMODE_INT_MASK 0x006540 |
||
316 | #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) |
||
317 | #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) |
||
318 | #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE |
||
319 | #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) |
||
320 | #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) |
||
321 | #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF |
||
322 | #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) |
||
323 | #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) |
||
324 | #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF |
||
325 | #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) |
||
326 | #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) |
||
327 | #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF |
||
328 | #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) |
||
329 | #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) |
||
330 | #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF |
||
331 | #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) |
||
332 | #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) |
||
333 | #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF |
||
334 | #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 |
||
335 | #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) |
||
336 | #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) |
||
337 | #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 |
||
338 | #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 |
||
339 | #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) |
||
340 | #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) |
||
341 | #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE |
||
342 | #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) |
||
343 | #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) |
||
344 | #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF |
||
345 | #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) |
||
346 | #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) |
||
347 | #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF |
||
348 | #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) |
||
349 | #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) |
||
350 | #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF |
||
351 | #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC |
||
352 | #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) |
||
353 | #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) |
||
354 | #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF |
||
355 | #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) |
||
356 | #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) |
||
357 | #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF |
||
1321 | serge | 358 | #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) |
359 | #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) |
||
360 | #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF |
||
361 | #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) |
||
362 | #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) |
||
363 | #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF |
||
364 | #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) |
||
365 | #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) |
||
366 | #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF |
||
367 | #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) |
||
368 | #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) |
||
369 | #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF |
||
370 | #define R_007828_DACA_AUTODETECT_CONTROL 0x007828 |
||
371 | #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) |
||
372 | #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) |
||
373 | #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC |
||
374 | #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) |
||
375 | #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) |
||
376 | #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF |
||
377 | #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) |
||
378 | #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) |
||
379 | #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF |
||
380 | #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 |
||
381 | #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) |
||
382 | #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE |
||
383 | #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) |
||
384 | #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) |
||
385 | #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF |
||
386 | #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 |
||
387 | #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) |
||
388 | #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) |
||
389 | #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC |
||
390 | #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) |
||
391 | #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) |
||
392 | #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF |
||
393 | #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) |
||
394 | #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) |
||
395 | #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF |
||
396 | #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 |
||
397 | #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) |
||
398 | #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE |
||
399 | #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) |
||
400 | #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) |
||
401 | #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF |
||
402 | #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 |
||
403 | #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) |
||
404 | #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) |
||
405 | #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE |
||
406 | #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 |
||
407 | #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) |
||
408 | #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) |
||
409 | #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE |
||
410 | #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) |
||
411 | #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) |
||
412 | #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD |
||
413 | #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 |
||
414 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) |
||
415 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE |
||
416 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) |
||
417 | #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) |
||
418 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF |
||
419 | #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) |
||
420 | #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) |
||
421 | #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF |
||
422 | #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 |
||
423 | #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) |
||
424 | #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) |
||
425 | #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE |
||
426 | #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 |
||
427 | #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) |
||
428 | #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) |
||
429 | #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE |
||
430 | #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) |
||
431 | #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) |
||
432 | #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD |
||
433 | #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 |
||
434 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) |
||
435 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE |
||
436 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) |
||
437 | #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) |
||
438 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF |
||
439 | #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) |
||
440 | #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) |
||
441 | #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF |
||
1221 | serge | 442 | |
443 | /* MC registers */ |
||
444 | #define R_000000_MC_STATUS 0x000000 |
||
445 | #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) |
||
446 | #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) |
||
447 | #define C_000000_MC_IDLE 0xFFFFFFFE |
||
448 | #define R_000004_MC_FB_LOCATION 0x000004 |
||
449 | #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
||
450 | #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
||
451 | #define C_000004_MC_FB_START 0xFFFF0000 |
||
452 | #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
||
453 | #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
||
454 | #define C_000004_MC_FB_TOP 0x0000FFFF |
||
455 | #define R_000005_MC_AGP_LOCATION 0x000005 |
||
456 | #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
||
457 | #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
||
458 | #define C_000005_MC_AGP_START 0xFFFF0000 |
||
459 | #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
||
460 | #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
||
461 | #define C_000005_MC_AGP_TOP 0x0000FFFF |
||
462 | #define R_000006_AGP_BASE 0x000006 |
||
463 | #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
||
464 | #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
||
465 | #define C_000006_AGP_BASE_ADDR 0x00000000 |
||
466 | #define R_000007_AGP_BASE_2 0x000007 |
||
467 | #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) |
||
468 | #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) |
||
469 | #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 |
||
470 | #define R_000009_MC_CNTL1 0x000009 |
||
471 | #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) |
||
472 | #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) |
||
473 | #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF |
||
474 | /* FIXME don't know the various field size need feedback from AMD */ |
||
475 | #define R_000100_MC_PT0_CNTL 0x000100 |
||
476 | #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) |
||
477 | #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) |
||
478 | #define C_000100_ENABLE_PT 0xFFFFFFFE |
||
479 | #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) |
||
480 | #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) |
||
481 | #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF |
||
482 | #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) |
||
483 | #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) |
||
484 | #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF |
||
485 | #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) |
||
486 | #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) |
||
487 | #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF |
||
488 | #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) |
||
489 | #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) |
||
490 | #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF |
||
491 | #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 |
||
492 | #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) |
||
493 | #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) |
||
494 | #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE |
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495 | #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) |
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496 | #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) |
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497 | #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 |
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498 | #define V_000102_PAGE_TABLE_FLAT 0 |
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499 | /* R600 documentation suggest that this should be a number of pages */ |
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500 | #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 |
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501 | #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 |
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502 | #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C |
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503 | #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C |
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504 | #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C |
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505 | #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C |
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506 | #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C |
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507 | #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) |
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508 | #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) |
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509 | #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE |
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510 | #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) |
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511 | #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) |
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512 | #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD |
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513 | #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) |
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514 | #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) |
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515 | #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF |
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516 | #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 |
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517 | #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 |
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518 | #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 |
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519 | #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 |
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520 | #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) |
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521 | #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) |
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522 | #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF |
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523 | #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 |
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524 | #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 |
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525 | #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) |
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526 | #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) |
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527 | #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF |
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528 | #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) |
||
529 | #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) |
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530 | #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF |
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531 | #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) |
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532 | #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) |
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533 | #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF |
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534 | #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) |
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535 | #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) |
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536 | #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF |
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537 | |||
538 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |