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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1221 | serge | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
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30 | * This file gather function specific to RS600 which is the IGP of |
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31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
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32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
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33 | * the avivo one, bios is an atombios, 3D block are the one of the |
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34 | * R4XX family. The GART is different from the RS400 one and is very |
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35 | * close to the one of the R600 family (R600 likely being an evolution |
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36 | * of the RS600 GART block). |
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37 | */ |
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2997 | Serge | 38 | #include |
1128 | serge | 39 | #include "radeon.h" |
1963 | serge | 40 | #include "radeon_asic.h" |
1221 | serge | 41 | #include "atom.h" |
42 | #include "rs600d.h" |
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1128 | serge | 43 | |
1179 | serge | 44 | #include "rs600_reg_safe.h" |
45 | |||
2997 | Serge | 46 | static void rs600_gpu_init(struct radeon_device *rdev); |
1128 | serge | 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | |||
2997 | Serge | 49 | static const u32 crtc_offsets[2] = |
50 | { |
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51 | 0, |
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52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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53 | }; |
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54 | |||
3764 | Serge | 55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
56 | { |
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57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
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58 | return true; |
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59 | else |
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60 | return false; |
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61 | } |
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62 | |||
63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
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64 | { |
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65 | u32 pos1, pos2; |
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66 | |||
67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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69 | |||
70 | if (pos1 != pos2) |
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71 | return true; |
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72 | else |
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73 | return false; |
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74 | } |
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75 | |||
76 | /** |
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77 | * avivo_wait_for_vblank - vblank wait asic callback. |
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78 | * |
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79 | * @rdev: radeon_device pointer |
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80 | * @crtc: crtc to wait for vblank on |
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81 | * |
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82 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
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83 | */ |
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2997 | Serge | 84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
85 | { |
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3764 | Serge | 86 | unsigned i = 0; |
2997 | Serge | 87 | |
88 | if (crtc >= rdev->num_crtc) |
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89 | return; |
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90 | |||
3764 | Serge | 91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
92 | return; |
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93 | |||
94 | /* depending on when we hit vblank, we may be close to active; if so, |
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95 | * wait for another frame. |
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96 | */ |
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97 | while (avivo_is_in_vblank(rdev, crtc)) { |
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98 | if (i++ % 100 == 0) { |
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99 | if (!avivo_is_counter_moving(rdev, crtc)) |
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2997 | Serge | 100 | break; |
101 | } |
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3764 | Serge | 102 | } |
103 | |||
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
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105 | if (i++ % 100 == 0) { |
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106 | if (!avivo_is_counter_moving(rdev, crtc)) |
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107 | break; |
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108 | } |
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5078 | serge | 109 | } |
110 | } |
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111 | void avivo_program_fmt(struct drm_encoder *encoder) |
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112 | { |
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113 | struct drm_device *dev = encoder->dev; |
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114 | struct radeon_device *rdev = dev->dev_private; |
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115 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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116 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
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117 | int bpc = 0; |
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118 | u32 tmp = 0; |
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119 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
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120 | |||
121 | if (connector) { |
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122 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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123 | bpc = radeon_get_monitor_bpc(connector); |
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124 | dither = radeon_connector->dither; |
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125 | } |
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126 | |||
127 | /* LVDS FMT is set up by atom */ |
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128 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
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129 | return; |
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130 | |||
131 | if (bpc == 0) |
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132 | return; |
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133 | |||
134 | switch (bpc) { |
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135 | case 6: |
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136 | if (dither == RADEON_FMT_DITHER_ENABLE) |
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137 | /* XXX sort out optimal dither settings */ |
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138 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
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139 | else |
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140 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
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141 | break; |
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142 | case 8: |
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143 | if (dither == RADEON_FMT_DITHER_ENABLE) |
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144 | /* XXX sort out optimal dither settings */ |
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145 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | |
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146 | AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); |
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147 | else |
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148 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | |
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149 | AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); |
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150 | break; |
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151 | case 10: |
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152 | default: |
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153 | /* not needed */ |
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154 | break; |
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155 | } |
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156 | |||
157 | switch (radeon_encoder->encoder_id) { |
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158 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
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159 | WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); |
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160 | break; |
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161 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
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162 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); |
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163 | break; |
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164 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
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165 | WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); |
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166 | break; |
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167 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
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168 | WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); |
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169 | break; |
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170 | default: |
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171 | break; |
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172 | } |
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173 | } |
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174 | |||
175 | void rs600_pm_misc(struct radeon_device *rdev) |
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176 | { |
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177 | int requested_index = rdev->pm.requested_power_state_index; |
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178 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
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179 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
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180 | u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; |
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181 | u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; |
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182 | |||
183 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
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184 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
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185 | tmp = RREG32(voltage->gpio.reg); |
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186 | if (voltage->active_high) |
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187 | tmp |= voltage->gpio.mask; |
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188 | else |
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189 | tmp &= ~(voltage->gpio.mask); |
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190 | WREG32(voltage->gpio.reg, tmp); |
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191 | if (voltage->delay) |
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192 | udelay(voltage->delay); |
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193 | } else { |
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194 | tmp = RREG32(voltage->gpio.reg); |
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195 | if (voltage->active_high) |
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196 | tmp &= ~voltage->gpio.mask; |
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197 | else |
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198 | tmp |= voltage->gpio.mask; |
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199 | WREG32(voltage->gpio.reg, tmp); |
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200 | if (voltage->delay) |
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201 | udelay(voltage->delay); |
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2997 | Serge | 202 | } |
5078 | serge | 203 | } else if (voltage->type == VOLTAGE_VDDC) |
204 | radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); |
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205 | |||
206 | dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); |
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207 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); |
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208 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); |
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209 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
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210 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { |
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211 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); |
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212 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); |
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213 | } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { |
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214 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); |
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215 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); |
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216 | } |
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217 | } else { |
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218 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); |
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219 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); |
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2997 | Serge | 220 | } |
5078 | serge | 221 | WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); |
222 | |||
223 | dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); |
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224 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
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225 | dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; |
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226 | if (voltage->delay) { |
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227 | dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; |
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228 | dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); |
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229 | } else |
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230 | dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; |
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231 | } else |
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232 | dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; |
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233 | WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); |
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234 | |||
235 | hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); |
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236 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
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237 | hdp_dyn_cntl &= ~HDP_FORCEON; |
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238 | else |
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239 | hdp_dyn_cntl |= HDP_FORCEON; |
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240 | WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); |
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241 | #if 0 |
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242 | /* mc_host_dyn seems to cause hangs from time to time */ |
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243 | mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); |
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244 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) |
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245 | mc_host_dyn_cntl &= ~MC_HOST_FORCEON; |
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246 | else |
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247 | mc_host_dyn_cntl |= MC_HOST_FORCEON; |
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248 | WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); |
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249 | #endif |
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250 | dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); |
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251 | if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) |
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252 | dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; |
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253 | else |
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254 | dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; |
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255 | WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); |
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256 | |||
257 | /* set pcie lanes */ |
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258 | if ((rdev->flags & RADEON_IS_PCIE) && |
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259 | !(rdev->flags & RADEON_IS_IGP) && |
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260 | rdev->asic->pm.set_pcie_lanes && |
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261 | (ps->pcie_lanes != |
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262 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
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263 | radeon_set_pcie_lanes(rdev, |
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264 | ps->pcie_lanes); |
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265 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
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266 | } |
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2997 | Serge | 267 | } |
5078 | serge | 268 | |
269 | void rs600_pm_prepare(struct radeon_device *rdev) |
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270 | { |
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271 | struct drm_device *ddev = rdev->ddev; |
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272 | struct drm_crtc *crtc; |
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273 | struct radeon_crtc *radeon_crtc; |
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274 | u32 tmp; |
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275 | |||
276 | /* disable any active CRTCs */ |
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277 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
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278 | radeon_crtc = to_radeon_crtc(crtc); |
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279 | if (radeon_crtc->enabled) { |
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280 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
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281 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
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282 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
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283 | } |
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284 | } |
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285 | } |
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286 | |||
287 | void rs600_pm_finish(struct radeon_device *rdev) |
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288 | { |
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289 | struct drm_device *ddev = rdev->ddev; |
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290 | struct drm_crtc *crtc; |
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291 | struct radeon_crtc *radeon_crtc; |
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292 | u32 tmp; |
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293 | |||
294 | /* enable any active CRTCs */ |
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295 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
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296 | radeon_crtc = to_radeon_crtc(crtc); |
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297 | if (radeon_crtc->enabled) { |
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298 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
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299 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
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300 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
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301 | } |
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302 | } |
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303 | } |
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304 | |||
1321 | serge | 305 | /* hpd for digital panel detect/disconnect */ |
306 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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307 | { |
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308 | u32 tmp; |
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309 | bool connected = false; |
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310 | |||
311 | switch (hpd) { |
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312 | case RADEON_HPD_1: |
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313 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
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314 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
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315 | connected = true; |
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316 | break; |
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317 | case RADEON_HPD_2: |
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318 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
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319 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
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320 | connected = true; |
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321 | break; |
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322 | default: |
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323 | break; |
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324 | } |
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325 | return connected; |
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326 | } |
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327 | |||
328 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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329 | enum radeon_hpd_id hpd) |
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330 | { |
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331 | u32 tmp; |
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332 | bool connected = rs600_hpd_sense(rdev, hpd); |
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333 | |||
334 | switch (hpd) { |
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335 | case RADEON_HPD_1: |
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336 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
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337 | if (connected) |
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338 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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339 | else |
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340 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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341 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
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342 | break; |
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343 | case RADEON_HPD_2: |
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344 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
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345 | if (connected) |
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346 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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347 | else |
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348 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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349 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
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350 | break; |
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351 | default: |
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352 | break; |
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353 | } |
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354 | } |
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355 | |||
356 | void rs600_hpd_init(struct radeon_device *rdev) |
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357 | { |
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358 | struct drm_device *dev = rdev->ddev; |
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359 | struct drm_connector *connector; |
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2997 | Serge | 360 | unsigned enable = 0; |
1321 | serge | 361 | |
362 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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363 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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364 | switch (radeon_connector->hpd.hpd) { |
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365 | case RADEON_HPD_1: |
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366 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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367 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
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368 | break; |
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369 | case RADEON_HPD_2: |
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370 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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371 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
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372 | break; |
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373 | default: |
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374 | break; |
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375 | } |
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2997 | Serge | 376 | enable |= 1 << radeon_connector->hpd.hpd; |
377 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
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1321 | serge | 378 | } |
2997 | Serge | 379 | // radeon_irq_kms_enable_hpd(rdev, enable); |
1321 | serge | 380 | } |
381 | |||
382 | void rs600_hpd_fini(struct radeon_device *rdev) |
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383 | { |
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384 | struct drm_device *dev = rdev->ddev; |
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385 | struct drm_connector *connector; |
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2997 | Serge | 386 | unsigned disable = 0; |
1321 | serge | 387 | |
388 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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389 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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390 | switch (radeon_connector->hpd.hpd) { |
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391 | case RADEON_HPD_1: |
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392 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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393 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
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394 | break; |
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395 | case RADEON_HPD_2: |
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396 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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397 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
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398 | break; |
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399 | default: |
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400 | break; |
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401 | } |
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2997 | Serge | 402 | disable |= 1 << radeon_connector->hpd.hpd; |
1321 | serge | 403 | } |
2997 | Serge | 404 | // radeon_irq_kms_disable_hpd(rdev, disable); |
1321 | serge | 405 | } |
406 | |||
1963 | serge | 407 | int rs600_asic_reset(struct radeon_device *rdev) |
408 | { |
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409 | struct rv515_mc_save save; |
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410 | u32 status, tmp; |
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411 | int ret = 0; |
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412 | |||
413 | status = RREG32(R_000E40_RBBM_STATUS); |
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414 | if (!G_000E40_GUI_ACTIVE(status)) { |
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415 | return 0; |
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416 | } |
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417 | /* Stops all mc clients */ |
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418 | rv515_mc_stop(rdev, &save); |
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419 | status = RREG32(R_000E40_RBBM_STATUS); |
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420 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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421 | /* stop CP */ |
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422 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
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423 | tmp = RREG32(RADEON_CP_RB_CNTL); |
||
424 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
||
425 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
||
426 | WREG32(RADEON_CP_RB_WPTR, 0); |
||
427 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
428 | // pci_save_state(rdev->pdev); |
||
429 | /* disable bus mastering */ |
||
2997 | Serge | 430 | // pci_clear_master(rdev->pdev); |
431 | mdelay(1); |
||
1963 | serge | 432 | /* reset GA+VAP */ |
433 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
||
434 | S_0000F0_SOFT_RESET_GA(1)); |
||
435 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
436 | mdelay(500); |
||
437 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
438 | mdelay(1); |
||
439 | status = RREG32(R_000E40_RBBM_STATUS); |
||
440 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
441 | /* reset CP */ |
||
442 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
||
443 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
444 | mdelay(500); |
||
445 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
446 | mdelay(1); |
||
447 | status = RREG32(R_000E40_RBBM_STATUS); |
||
448 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
449 | /* reset MC */ |
||
450 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
||
451 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
452 | mdelay(500); |
||
453 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
454 | mdelay(1); |
||
455 | status = RREG32(R_000E40_RBBM_STATUS); |
||
456 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
457 | /* restore PCI & busmastering */ |
||
458 | // pci_restore_state(rdev->pdev); |
||
459 | /* Check if GPU is idle */ |
||
460 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
||
461 | dev_err(rdev->dev, "failed to reset GPU\n"); |
||
462 | ret = -1; |
||
463 | } else |
||
464 | dev_info(rdev->dev, "GPU reset succeed\n"); |
||
465 | rv515_mc_resume(rdev, &save); |
||
466 | return ret; |
||
467 | } |
||
468 | |||
1128 | serge | 469 | /* |
470 | * GART. |
||
471 | */ |
||
472 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
||
473 | { |
||
474 | uint32_t tmp; |
||
475 | |||
1221 | serge | 476 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
477 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
||
478 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
||
1128 | serge | 479 | |
1221 | serge | 480 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
1963 | serge | 481 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
1221 | serge | 482 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
1128 | serge | 483 | |
1221 | serge | 484 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
485 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
||
486 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
||
487 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
||
1128 | serge | 488 | } |
489 | |||
2997 | Serge | 490 | static int rs600_gart_init(struct radeon_device *rdev) |
1128 | serge | 491 | { |
492 | int r; |
||
493 | |||
2997 | Serge | 494 | if (rdev->gart.robj) { |
1963 | serge | 495 | WARN(1, "RS600 GART already initialized\n"); |
1221 | serge | 496 | return 0; |
497 | } |
||
1128 | serge | 498 | /* Initialize common gart structure */ |
499 | r = radeon_gart_init(rdev); |
||
500 | if (r) { |
||
501 | return r; |
||
502 | } |
||
503 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
||
1221 | serge | 504 | return radeon_gart_table_vram_alloc(rdev); |
505 | } |
||
506 | |||
2005 | serge | 507 | static int rs600_gart_enable(struct radeon_device *rdev) |
1221 | serge | 508 | { |
509 | u32 tmp; |
||
510 | int r, i; |
||
511 | |||
2997 | Serge | 512 | if (rdev->gart.robj == NULL) { |
1221 | serge | 513 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
514 | return -EINVAL; |
||
515 | } |
||
516 | r = radeon_gart_table_vram_pin(rdev); |
||
517 | if (r) |
||
1128 | serge | 518 | return r; |
1221 | serge | 519 | /* Enable bus master */ |
2005 | serge | 520 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
521 | WREG32(RADEON_BUS_CNTL, tmp); |
||
1128 | serge | 522 | /* FIXME: setup default page */ |
1221 | serge | 523 | WREG32_MC(R_000100_MC_PT0_CNTL, |
524 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
||
525 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
||
1321 | serge | 526 | |
1128 | serge | 527 | for (i = 0; i < 19; i++) { |
1221 | serge | 528 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
529 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
||
530 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
||
1321 | serge | 531 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
1221 | serge | 532 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
1321 | serge | 533 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
534 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
||
1221 | serge | 535 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
1321 | serge | 536 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
1128 | serge | 537 | } |
538 | /* enable first context */ |
||
1221 | serge | 539 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
540 | S_000102_ENABLE_PAGE_TABLE(1) | |
||
541 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
||
1321 | serge | 542 | |
1128 | serge | 543 | /* disable all other contexts */ |
1321 | serge | 544 | for (i = 1; i < 8; i++) |
1221 | serge | 545 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
1128 | serge | 546 | |
547 | /* setup the page table */ |
||
1221 | serge | 548 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
1128 | serge | 549 | rdev->gart.table_addr); |
1321 | serge | 550 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
551 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
||
1221 | serge | 552 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
1128 | serge | 553 | |
1321 | serge | 554 | /* System context maps to VRAM space */ |
555 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
||
556 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
||
557 | |||
1128 | serge | 558 | /* enable page tables */ |
1221 | serge | 559 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
560 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
||
561 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
||
562 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
||
1128 | serge | 563 | rs600_gart_tlb_flush(rdev); |
2997 | Serge | 564 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
565 | (unsigned)(rdev->mc.gtt_size >> 20), |
||
566 | (unsigned long long)rdev->gart.table_addr); |
||
1128 | serge | 567 | rdev->gart.ready = true; |
568 | return 0; |
||
569 | } |
||
570 | |||
2997 | Serge | 571 | static void rs600_gart_disable(struct radeon_device *rdev) |
1128 | serge | 572 | { |
1321 | serge | 573 | u32 tmp; |
1128 | serge | 574 | |
575 | /* FIXME: disable out of gart access */ |
||
1221 | serge | 576 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
577 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
||
578 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
||
2997 | Serge | 579 | radeon_gart_table_vram_unpin(rdev); |
1128 | serge | 580 | } |
581 | |||
2997 | Serge | 582 | static void rs600_gart_fini(struct radeon_device *rdev) |
1221 | serge | 583 | { |
1963 | serge | 584 | radeon_gart_fini(rdev); |
1221 | serge | 585 | rs600_gart_disable(rdev); |
586 | radeon_gart_table_vram_free(rdev); |
||
587 | } |
||
588 | |||
5078 | serge | 589 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
590 | uint64_t addr, uint32_t flags) |
||
1128 | serge | 591 | { |
2997 | Serge | 592 | void __iomem *ptr = (void *)rdev->gart.ptr; |
1128 | serge | 593 | |
594 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
||
5078 | serge | 595 | addr |= R600_PTE_SYSTEM; |
596 | if (flags & RADEON_GART_PAGE_VALID) |
||
597 | addr |= R600_PTE_VALID; |
||
598 | if (flags & RADEON_GART_PAGE_READ) |
||
599 | addr |= R600_PTE_READABLE; |
||
600 | if (flags & RADEON_GART_PAGE_WRITE) |
||
601 | addr |= R600_PTE_WRITEABLE; |
||
602 | if (flags & RADEON_GART_PAGE_SNOOP) |
||
603 | addr |= R600_PTE_SNOOPED; |
||
2160 | serge | 604 | writeq(addr, ptr + (i * 8)); |
1128 | serge | 605 | } |
606 | |||
1321 | serge | 607 | int rs600_irq_set(struct radeon_device *rdev) |
608 | { |
||
609 | uint32_t tmp = 0; |
||
610 | uint32_t mode_int = 0; |
||
611 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
||
612 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
||
613 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
||
614 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
||
2997 | Serge | 615 | u32 hdmi0; |
616 | if (ASIC_IS_DCE2(rdev)) |
||
617 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
||
618 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
619 | else |
||
620 | hdmi0 = 0; |
||
1128 | serge | 621 | |
1403 | serge | 622 | if (!rdev->irq.installed) { |
1963 | serge | 623 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
1403 | serge | 624 | WREG32(R_000040_GEN_INT_CNTL, 0); |
625 | return -EINVAL; |
||
626 | } |
||
2997 | Serge | 627 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
1321 | serge | 628 | tmp |= S_000040_SW_INT_EN(1); |
629 | } |
||
1963 | serge | 630 | if (rdev->irq.crtc_vblank_int[0] || |
2997 | Serge | 631 | atomic_read(&rdev->irq.pflip[0])) { |
1321 | serge | 632 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
633 | } |
||
1963 | serge | 634 | if (rdev->irq.crtc_vblank_int[1] || |
2997 | Serge | 635 | atomic_read(&rdev->irq.pflip[1])) { |
1321 | serge | 636 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
637 | } |
||
638 | if (rdev->irq.hpd[0]) { |
||
639 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
||
640 | } |
||
641 | if (rdev->irq.hpd[1]) { |
||
642 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
||
643 | } |
||
2997 | Serge | 644 | if (rdev->irq.afmt[0]) { |
645 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
646 | } |
||
1321 | serge | 647 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
648 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
||
649 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
||
650 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
||
2997 | Serge | 651 | if (ASIC_IS_DCE2(rdev)) |
652 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1321 | serge | 653 | return 0; |
654 | } |
||
1128 | serge | 655 | |
1963 | serge | 656 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
1128 | serge | 657 | { |
1221 | serge | 658 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
1963 | serge | 659 | uint32_t irq_mask = S_000044_SW_INT(1); |
1321 | serge | 660 | u32 tmp; |
1128 | serge | 661 | |
1221 | serge | 662 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
1963 | serge | 663 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
664 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
1221 | serge | 665 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
666 | S_006534_D1MODE_VBLANK_ACK(1)); |
||
667 | } |
||
1963 | serge | 668 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1221 | serge | 669 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
670 | S_006D34_D2MODE_VBLANK_ACK(1)); |
||
671 | } |
||
1963 | serge | 672 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 673 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
674 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
||
675 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
||
676 | } |
||
1963 | serge | 677 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 678 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
679 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
||
680 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
||
681 | } |
||
1221 | serge | 682 | } else { |
1963 | serge | 683 | rdev->irq.stat_regs.r500.disp_int = 0; |
1129 | serge | 684 | } |
1128 | serge | 685 | |
2997 | Serge | 686 | if (ASIC_IS_DCE2(rdev)) { |
687 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
||
688 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
||
689 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
||
690 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
||
691 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
||
692 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
||
693 | } |
||
694 | } else |
||
695 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
||
696 | |||
1221 | serge | 697 | if (irqs) { |
698 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
||
1128 | serge | 699 | } |
1221 | serge | 700 | return irqs & irq_mask; |
1128 | serge | 701 | } |
702 | |||
1221 | serge | 703 | void rs600_irq_disable(struct radeon_device *rdev) |
1128 | serge | 704 | { |
2997 | Serge | 705 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
706 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
707 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1221 | serge | 708 | WREG32(R_000040_GEN_INT_CNTL, 0); |
709 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
||
710 | /* Wait and acknowledge irq */ |
||
711 | mdelay(1); |
||
1963 | serge | 712 | rs600_irq_ack(rdev); |
1128 | serge | 713 | } |
714 | |||
2005 | serge | 715 | int rs600_irq_process(struct radeon_device *rdev) |
716 | { |
||
717 | u32 status, msi_rearm; |
||
718 | bool queue_hotplug = false; |
||
2997 | Serge | 719 | bool queue_hdmi = false; |
1128 | serge | 720 | |
2005 | serge | 721 | status = rs600_irq_ack(rdev); |
2997 | Serge | 722 | if (!status && |
723 | !rdev->irq.stat_regs.r500.disp_int && |
||
724 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 725 | return IRQ_NONE; |
726 | } |
||
2997 | Serge | 727 | while (status || |
728 | rdev->irq.stat_regs.r500.disp_int || |
||
729 | rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 730 | /* SW interrupt */ |
731 | if (G_000044_SW_INT(status)) { |
||
2997 | Serge | 732 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2005 | serge | 733 | } |
734 | /* Vertical blank interrupts */ |
||
735 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
736 | if (rdev->irq.crtc_vblank_int[0]) { |
||
737 | // drm_handle_vblank(rdev->ddev, 0); |
||
738 | rdev->pm.vblank_sync = true; |
||
739 | // wake_up(&rdev->irq.vblank_queue); |
||
740 | } |
||
741 | // if (rdev->irq.pflip[0]) |
||
742 | // radeon_crtc_handle_flip(rdev, 0); |
||
743 | } |
||
744 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
745 | if (rdev->irq.crtc_vblank_int[1]) { |
||
746 | // drm_handle_vblank(rdev->ddev, 1); |
||
747 | rdev->pm.vblank_sync = true; |
||
748 | // wake_up(&rdev->irq.vblank_queue); |
||
749 | } |
||
750 | // if (rdev->irq.pflip[1]) |
||
751 | // radeon_crtc_handle_flip(rdev, 1); |
||
752 | } |
||
753 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
754 | queue_hotplug = true; |
||
755 | DRM_DEBUG("HPD1\n"); |
||
756 | } |
||
757 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
758 | queue_hotplug = true; |
||
759 | DRM_DEBUG("HPD2\n"); |
||
760 | } |
||
2997 | Serge | 761 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
762 | queue_hdmi = true; |
||
763 | DRM_DEBUG("HDMI0\n"); |
||
764 | } |
||
2005 | serge | 765 | status = rs600_irq_ack(rdev); |
766 | } |
||
767 | // if (queue_hotplug) |
||
768 | // schedule_work(&rdev->hotplug_work); |
||
2997 | Serge | 769 | // if (queue_hdmi) |
770 | // schedule_work(&rdev->audio_work); |
||
2005 | serge | 771 | if (rdev->msi_enabled) { |
772 | switch (rdev->family) { |
||
773 | case CHIP_RS600: |
||
774 | case CHIP_RS690: |
||
775 | case CHIP_RS740: |
||
776 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
||
777 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
||
778 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
||
779 | break; |
||
780 | default: |
||
2997 | Serge | 781 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
2005 | serge | 782 | break; |
783 | } |
||
784 | } |
||
785 | return IRQ_HANDLED; |
||
786 | } |
||
787 | |||
1221 | serge | 788 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
1128 | serge | 789 | { |
1221 | serge | 790 | if (crtc == 0) |
791 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
||
792 | else |
||
793 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
||
1128 | serge | 794 | } |
795 | |||
796 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
||
797 | { |
||
798 | unsigned i; |
||
799 | |||
800 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1221 | serge | 801 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
1128 | serge | 802 | return 0; |
1221 | serge | 803 | udelay(1); |
1128 | serge | 804 | } |
805 | return -1; |
||
806 | } |
||
807 | |||
2997 | Serge | 808 | static void rs600_gpu_init(struct radeon_device *rdev) |
1128 | serge | 809 | { |
810 | r420_pipes_init(rdev); |
||
1221 | serge | 811 | /* Wait for mc idle */ |
812 | if (rs600_mc_wait_for_idle(rdev)) |
||
813 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
1128 | serge | 814 | } |
815 | |||
2997 | Serge | 816 | static void rs600_mc_init(struct radeon_device *rdev) |
1128 | serge | 817 | { |
1430 | serge | 818 | u64 base; |
819 | |||
1963 | serge | 820 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
821 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
1128 | serge | 822 | rdev->mc.vram_is_ddr = true; |
823 | rdev->mc.vram_width = 128; |
||
1321 | serge | 824 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
825 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1430 | serge | 826 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
827 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
||
828 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
||
829 | base = G_000004_MC_FB_START(base) << 16; |
||
830 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 831 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 832 | radeon_gtt_location(rdev, &rdev->mc); |
1963 | serge | 833 | radeon_update_bandwidth_info(rdev); |
1128 | serge | 834 | } |
835 | |||
1179 | serge | 836 | void rs600_bandwidth_update(struct radeon_device *rdev) |
837 | { |
||
1963 | serge | 838 | struct drm_display_mode *mode0 = NULL; |
839 | struct drm_display_mode *mode1 = NULL; |
||
840 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
||
841 | /* FIXME: implement full support */ |
||
842 | |||
843 | radeon_update_display_priority(rdev); |
||
844 | |||
845 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
846 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
847 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
848 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
849 | |||
850 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
851 | |||
852 | if (rdev->disp_priority == 2) { |
||
853 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
||
854 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
||
855 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
||
856 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
||
857 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
858 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
859 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
860 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
861 | } |
||
1179 | serge | 862 | } |
1128 | serge | 863 | |
864 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
||
865 | { |
||
5078 | serge | 866 | unsigned long flags; |
867 | u32 r; |
||
868 | |||
869 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
||
1221 | serge | 870 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
871 | S_000070_MC_IND_CITF_ARB0(1)); |
||
5078 | serge | 872 | r = RREG32(R_000074_MC_IND_DATA); |
873 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
||
874 | return r; |
||
1221 | serge | 875 | } |
1128 | serge | 876 | |
1221 | serge | 877 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
878 | { |
||
5078 | serge | 879 | unsigned long flags; |
880 | |||
881 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
||
1221 | serge | 882 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
883 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
||
884 | WREG32(R_000074_MC_IND_DATA, v); |
||
5078 | serge | 885 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
1221 | serge | 886 | } |
887 | |||
2997 | Serge | 888 | static void rs600_debugfs(struct radeon_device *rdev) |
1221 | serge | 889 | { |
890 | if (r100_debugfs_rbbm_init(rdev)) |
||
891 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
||
892 | } |
||
893 | |||
894 | void rs600_set_safe_registers(struct radeon_device *rdev) |
||
895 | { |
||
896 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
||
897 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
||
898 | } |
||
899 | |||
900 | static void rs600_mc_program(struct radeon_device *rdev) |
||
901 | { |
||
902 | struct rv515_mc_save save; |
||
903 | |||
904 | /* Stops all mc clients */ |
||
905 | rv515_mc_stop(rdev, &save); |
||
906 | |||
907 | /* Wait for mc idle */ |
||
908 | if (rs600_mc_wait_for_idle(rdev)) |
||
909 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
910 | |||
911 | /* FIXME: What does AGP means for such chipset ? */ |
||
912 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
913 | WREG32_MC(R_000006_AGP_BASE, 0); |
||
914 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
||
915 | /* Program MC */ |
||
916 | WREG32_MC(R_000004_MC_FB_LOCATION, |
||
917 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
918 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
919 | WREG32(R_000134_HDP_FB_LOCATION, |
||
920 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
921 | |||
922 | rv515_mc_resume(rdev, &save); |
||
923 | } |
||
924 | |||
925 | static int rs600_startup(struct radeon_device *rdev) |
||
926 | { |
||
927 | int r; |
||
928 | |||
929 | rs600_mc_program(rdev); |
||
930 | /* Resume clock */ |
||
931 | rv515_clock_startup(rdev); |
||
932 | /* Initialize GPU configuration (# pipes, ...) */ |
||
933 | rs600_gpu_init(rdev); |
||
934 | /* Initialize GART (initialize after TTM so we can allocate |
||
935 | * memory through TTM but finalize after TTM) */ |
||
936 | r = rs600_gart_enable(rdev); |
||
937 | if (r) |
||
1128 | serge | 938 | return r; |
2005 | serge | 939 | |
940 | /* allocate wb buffer */ |
||
941 | r = radeon_wb_init(rdev); |
||
942 | if (r) |
||
943 | return r; |
||
944 | |||
3192 | Serge | 945 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
946 | if (r) { |
||
947 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
948 | return r; |
||
949 | } |
||
950 | |||
1221 | serge | 951 | /* Enable IRQ */ |
3764 | Serge | 952 | if (!rdev->irq.installed) { |
953 | r = radeon_irq_kms_init(rdev); |
||
954 | if (r) |
||
955 | return r; |
||
956 | } |
||
957 | |||
2005 | serge | 958 | rs600_irq_set(rdev); |
1403 | serge | 959 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 960 | /* 1M ring buffer */ |
1413 | serge | 961 | r = r100_cp_init(rdev, 1024 * 1024); |
962 | if (r) { |
||
1963 | serge | 963 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 964 | return r; |
965 | } |
||
2997 | Serge | 966 | |
967 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 968 | if (r) { |
2997 | Serge | 969 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 970 | return r; |
971 | } |
||
2997 | Serge | 972 | |
5078 | serge | 973 | r = r600_audio_init(rdev); |
974 | if (r) { |
||
975 | dev_err(rdev->dev, "failed initializing audio\n"); |
||
976 | return r; |
||
977 | } |
||
2997 | Serge | 978 | |
1221 | serge | 979 | return 0; |
1128 | serge | 980 | } |
981 | |||
1221 | serge | 982 | |
983 | |||
984 | int rs600_init(struct radeon_device *rdev) |
||
1128 | serge | 985 | { |
1221 | serge | 986 | int r; |
987 | |||
988 | /* Disable VGA */ |
||
989 | rv515_vga_render_disable(rdev); |
||
990 | /* Initialize scratch registers */ |
||
991 | radeon_scratch_init(rdev); |
||
992 | /* Initialize surface registers */ |
||
993 | radeon_surface_init(rdev); |
||
1963 | serge | 994 | /* restore some register to sane defaults */ |
995 | r100_restore_sanity(rdev); |
||
1221 | serge | 996 | /* BIOS */ |
997 | if (!radeon_get_bios(rdev)) { |
||
998 | if (ASIC_IS_AVIVO(rdev)) |
||
999 | return -EINVAL; |
||
1000 | } |
||
1001 | if (rdev->is_atom_bios) { |
||
1002 | r = radeon_atombios_init(rdev); |
||
1003 | if (r) |
||
1004 | return r; |
||
1005 | } else { |
||
1006 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
||
1007 | return -EINVAL; |
||
1008 | } |
||
1009 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 1010 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 1011 | dev_warn(rdev->dev, |
1012 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
1013 | RREG32(R_000E40_RBBM_STATUS), |
||
1014 | RREG32(R_0007C0_CP_STAT)); |
||
1015 | } |
||
1016 | /* check if cards are posted or not */ |
||
1321 | serge | 1017 | if (radeon_boot_test_post_card(rdev) == false) |
1018 | return -EINVAL; |
||
1019 | |||
1221 | serge | 1020 | /* Initialize clocks */ |
1021 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 1022 | /* initialize memory controller */ |
1023 | rs600_mc_init(rdev); |
||
1221 | serge | 1024 | rs600_debugfs(rdev); |
1025 | /* Fence driver */ |
||
2005 | serge | 1026 | r = radeon_fence_driver_init(rdev); |
1027 | if (r) |
||
1028 | return r; |
||
1221 | serge | 1029 | /* Memory manager */ |
1321 | serge | 1030 | r = radeon_bo_init(rdev); |
1221 | serge | 1031 | if (r) |
1032 | return r; |
||
1033 | r = rs600_gart_init(rdev); |
||
1034 | if (r) |
||
1035 | return r; |
||
1036 | rs600_set_safe_registers(rdev); |
||
2997 | Serge | 1037 | |
5078 | serge | 1038 | /* Initialize power management */ |
1039 | radeon_pm_init(rdev); |
||
1040 | |||
1221 | serge | 1041 | rdev->accel_working = true; |
1042 | r = rs600_startup(rdev); |
||
1043 | if (r) { |
||
1044 | /* Somethings want wront with the accel init stop accel */ |
||
1045 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
1046 | // r100_cp_fini(rdev); |
||
1047 | // r100_wb_fini(rdev); |
||
1048 | // r100_ib_fini(rdev); |
||
1049 | rs600_gart_fini(rdev); |
||
1050 | // radeon_irq_kms_fini(rdev); |
||
1051 | rdev->accel_working = false; |
||
1052 | } |
||
1053 | return 0; |
||
1128 | serge | 1054 | }><>>>>><>><> |