Subversion Repositories Kolibri OS

/*

 * Copyright 2008 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Dave Airlie

 *          Alex Deucher

 *          Jerome Glisse

 */

/* RS600 / Radeon X1250/X1270 integrated GPU

 *

 * This file gather function specific to RS600 which is the IGP of

 * the X1250/X1270 family supporting intel CPU (while RS690/RS740

 * is the X1250/X1270 supporting AMD CPU). The display engine are

 * the avivo one, bios is an atombios, 3D block are the one of the

 * R4XX family. The GART is different from the RS400 one and is very

 * close to the one of the R600 family (R600 likely being an evolution

 * of the RS600 GART block).

 */

#include 

#include "radeon.h"

#include "radeon_asic.h"

#include "atom.h"

#include "rs600d.h"

#include "rs600_reg_safe.h"

static void rs600_gpu_init(struct radeon_device *rdev);

int rs600_mc_wait_for_idle(struct radeon_device *rdev);

static const u32 crtc_offsets[2] =

{

	0,

	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL

};

void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)

{

	int i;

	if (crtc >= rdev->num_crtc)

		return;

	if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {

		for (i = 0; i < rdev->usec_timeout; i++) {

			if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))

				break;

			udelay(1);

		}

		for (i = 0; i < rdev->usec_timeout; i++) {

			if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)

				break;

			udelay(1);

		}

	}

}

/* hpd for digital panel detect/disconnect */

bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)

{

	u32 tmp;

	bool connected = false;

	switch (hpd) {

	case RADEON_HPD_1:

		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);

		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))

			connected = true;

		break;

	case RADEON_HPD_2:

		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);

		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))

			connected = true;

		break;

	default:

		break;

	}

	return connected;

}

void rs600_hpd_set_polarity(struct radeon_device *rdev,

			    enum radeon_hpd_id hpd)

{

	u32 tmp;

	bool connected = rs600_hpd_sense(rdev, hpd);

	switch (hpd) {

	case RADEON_HPD_1:

		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);

		if (connected)

			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);

		else

			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);

		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

		break;

	case RADEON_HPD_2:

		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);

		if (connected)

			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);

		else

			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);

		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

		break;

	default:

		break;

	}

}

void rs600_hpd_init(struct radeon_device *rdev)

{

	struct drm_device *dev = rdev->ddev;

	struct drm_connector *connector;

	unsigned enable = 0;

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);

		switch (radeon_connector->hpd.hpd) {

		case RADEON_HPD_1:

			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,

			       S_007D00_DC_HOT_PLUG_DETECT1_EN(1));

			break;

		case RADEON_HPD_2:

			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,

			       S_007D10_DC_HOT_PLUG_DETECT2_EN(1));

			break;

		default:

			break;

		}

		enable |= 1 << radeon_connector->hpd.hpd;

		radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);

	}

//	radeon_irq_kms_enable_hpd(rdev, enable);

}

void rs600_hpd_fini(struct radeon_device *rdev)

{

	struct drm_device *dev = rdev->ddev;

	struct drm_connector *connector;

	unsigned disable = 0;

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);

		switch (radeon_connector->hpd.hpd) {

		case RADEON_HPD_1:

			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,

			       S_007D00_DC_HOT_PLUG_DETECT1_EN(0));

			break;

		case RADEON_HPD_2:

			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,

			       S_007D10_DC_HOT_PLUG_DETECT2_EN(0));

			break;

		default:

			break;

		}

		disable |= 1 << radeon_connector->hpd.hpd;

	}

//	radeon_irq_kms_disable_hpd(rdev, disable);

}

int rs600_asic_reset(struct radeon_device *rdev)

{

	struct rv515_mc_save save;

	u32 status, tmp;

	int ret = 0;

	status = RREG32(R_000E40_RBBM_STATUS);

	if (!G_000E40_GUI_ACTIVE(status)) {

		return 0;

	}

	/* Stops all mc clients */

	rv515_mc_stop(rdev, &save);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* stop CP */

	WREG32(RADEON_CP_CSQ_CNTL, 0);

	tmp = RREG32(RADEON_CP_RB_CNTL);

	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

	WREG32(RADEON_CP_RB_RPTR_WR, 0);

	WREG32(RADEON_CP_RB_WPTR, 0);

	WREG32(RADEON_CP_RB_CNTL, tmp);

//   pci_save_state(rdev->pdev);

	/* disable bus mastering */

//	pci_clear_master(rdev->pdev);

	mdelay(1);

	/* reset GA+VAP */

	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |

					S_0000F0_SOFT_RESET_GA(1));

	RREG32(R_0000F0_RBBM_SOFT_RESET);

	mdelay(500);

	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

	mdelay(1);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* reset CP */

	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));

	RREG32(R_0000F0_RBBM_SOFT_RESET);

	mdelay(500);

	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

	mdelay(1);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* reset MC */

	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));

	RREG32(R_0000F0_RBBM_SOFT_RESET);

	mdelay(500);

	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

	mdelay(1);

	status = RREG32(R_000E40_RBBM_STATUS);

	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

	/* restore PCI & busmastering */

//   pci_restore_state(rdev->pdev);

	/* Check if GPU is idle */

	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {

		dev_err(rdev->dev, "failed to reset GPU\n");

		ret = -1;

	} else

		dev_info(rdev->dev, "GPU reset succeed\n");

	rv515_mc_resume(rdev, &save);

	return ret;

}

/*

 * GART.

 */

void rs600_gart_tlb_flush(struct radeon_device *rdev)

{

	uint32_t tmp;