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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1221 | serge | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
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30 | * This file gather function specific to RS600 which is the IGP of |
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31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
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32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
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33 | * the avivo one, bios is an atombios, 3D block are the one of the |
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34 | * R4XX family. The GART is different from the RS400 one and is very |
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35 | * close to the one of the R600 family (R600 likely being an evolution |
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36 | * of the RS600 GART block). |
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37 | */ |
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2997 | Serge | 38 | #include |
1128 | serge | 39 | #include "radeon.h" |
1963 | serge | 40 | #include "radeon_asic.h" |
1221 | serge | 41 | #include "atom.h" |
42 | #include "rs600d.h" |
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1128 | serge | 43 | |
1179 | serge | 44 | #include "rs600_reg_safe.h" |
45 | |||
2997 | Serge | 46 | static void rs600_gpu_init(struct radeon_device *rdev); |
1128 | serge | 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | |||
2997 | Serge | 49 | static const u32 crtc_offsets[2] = |
50 | { |
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51 | 0, |
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52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
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53 | }; |
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54 | |||
55 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
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56 | { |
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57 | int i; |
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58 | |||
59 | if (crtc >= rdev->num_crtc) |
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60 | return; |
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61 | |||
62 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
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63 | for (i = 0; i < rdev->usec_timeout; i++) { |
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64 | if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
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65 | break; |
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66 | udelay(1); |
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67 | } |
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68 | for (i = 0; i < rdev->usec_timeout; i++) { |
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69 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
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70 | break; |
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71 | udelay(1); |
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72 | } |
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73 | } |
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74 | } |
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1321 | serge | 75 | /* hpd for digital panel detect/disconnect */ |
76 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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77 | { |
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78 | u32 tmp; |
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79 | bool connected = false; |
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80 | |||
81 | switch (hpd) { |
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82 | case RADEON_HPD_1: |
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83 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
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84 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
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85 | connected = true; |
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86 | break; |
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87 | case RADEON_HPD_2: |
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88 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
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89 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
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90 | connected = true; |
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91 | break; |
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92 | default: |
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93 | break; |
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94 | } |
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95 | return connected; |
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96 | } |
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97 | |||
98 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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99 | enum radeon_hpd_id hpd) |
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100 | { |
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101 | u32 tmp; |
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102 | bool connected = rs600_hpd_sense(rdev, hpd); |
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103 | |||
104 | switch (hpd) { |
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105 | case RADEON_HPD_1: |
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106 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
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107 | if (connected) |
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108 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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109 | else |
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110 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
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111 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
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112 | break; |
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113 | case RADEON_HPD_2: |
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114 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
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115 | if (connected) |
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116 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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117 | else |
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118 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
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119 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
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120 | break; |
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121 | default: |
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122 | break; |
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123 | } |
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124 | } |
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125 | |||
126 | void rs600_hpd_init(struct radeon_device *rdev) |
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127 | { |
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128 | struct drm_device *dev = rdev->ddev; |
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129 | struct drm_connector *connector; |
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2997 | Serge | 130 | unsigned enable = 0; |
1321 | serge | 131 | |
132 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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133 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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134 | switch (radeon_connector->hpd.hpd) { |
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135 | case RADEON_HPD_1: |
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136 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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137 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
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138 | break; |
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139 | case RADEON_HPD_2: |
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140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
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142 | break; |
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143 | default: |
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144 | break; |
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145 | } |
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2997 | Serge | 146 | enable |= 1 << radeon_connector->hpd.hpd; |
147 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
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1321 | serge | 148 | } |
2997 | Serge | 149 | // radeon_irq_kms_enable_hpd(rdev, enable); |
1321 | serge | 150 | } |
151 | |||
152 | void rs600_hpd_fini(struct radeon_device *rdev) |
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153 | { |
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154 | struct drm_device *dev = rdev->ddev; |
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155 | struct drm_connector *connector; |
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2997 | Serge | 156 | unsigned disable = 0; |
1321 | serge | 157 | |
158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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159 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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160 | switch (radeon_connector->hpd.hpd) { |
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161 | case RADEON_HPD_1: |
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162 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
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163 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
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164 | break; |
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165 | case RADEON_HPD_2: |
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166 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
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167 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
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168 | break; |
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169 | default: |
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170 | break; |
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171 | } |
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2997 | Serge | 172 | disable |= 1 << radeon_connector->hpd.hpd; |
1321 | serge | 173 | } |
2997 | Serge | 174 | // radeon_irq_kms_disable_hpd(rdev, disable); |
1321 | serge | 175 | } |
176 | |||
1963 | serge | 177 | int rs600_asic_reset(struct radeon_device *rdev) |
178 | { |
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179 | struct rv515_mc_save save; |
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180 | u32 status, tmp; |
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181 | int ret = 0; |
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182 | |||
183 | status = RREG32(R_000E40_RBBM_STATUS); |
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184 | if (!G_000E40_GUI_ACTIVE(status)) { |
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185 | return 0; |
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186 | } |
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187 | /* Stops all mc clients */ |
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188 | rv515_mc_stop(rdev, &save); |
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189 | status = RREG32(R_000E40_RBBM_STATUS); |
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190 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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191 | /* stop CP */ |
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192 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
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193 | tmp = RREG32(RADEON_CP_RB_CNTL); |
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194 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
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195 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
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196 | WREG32(RADEON_CP_RB_WPTR, 0); |
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197 | WREG32(RADEON_CP_RB_CNTL, tmp); |
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198 | // pci_save_state(rdev->pdev); |
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199 | /* disable bus mastering */ |
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2997 | Serge | 200 | // pci_clear_master(rdev->pdev); |
201 | mdelay(1); |
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1963 | serge | 202 | /* reset GA+VAP */ |
203 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
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204 | S_0000F0_SOFT_RESET_GA(1)); |
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205 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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206 | mdelay(500); |
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207 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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208 | mdelay(1); |
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209 | status = RREG32(R_000E40_RBBM_STATUS); |
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210 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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211 | /* reset CP */ |
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212 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
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213 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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214 | mdelay(500); |
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215 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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216 | mdelay(1); |
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217 | status = RREG32(R_000E40_RBBM_STATUS); |
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218 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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219 | /* reset MC */ |
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220 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
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221 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
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222 | mdelay(500); |
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223 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
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224 | mdelay(1); |
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225 | status = RREG32(R_000E40_RBBM_STATUS); |
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226 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
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227 | /* restore PCI & busmastering */ |
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228 | // pci_restore_state(rdev->pdev); |
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229 | /* Check if GPU is idle */ |
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230 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
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231 | dev_err(rdev->dev, "failed to reset GPU\n"); |
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232 | ret = -1; |
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233 | } else |
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234 | dev_info(rdev->dev, "GPU reset succeed\n"); |
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235 | rv515_mc_resume(rdev, &save); |
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236 | return ret; |
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237 | } |
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238 | |||
1128 | serge | 239 | /* |
240 | * GART. |
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241 | */ |
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242 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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243 | { |
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244 | uint32_t tmp; |
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245 | |||
1221 | serge | 246 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
247 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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248 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 249 | |
1221 | serge | 250 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
1963 | serge | 251 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
1221 | serge | 252 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
1128 | serge | 253 | |
1221 | serge | 254 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
255 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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256 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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257 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
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1128 | serge | 258 | } |
259 | |||
2997 | Serge | 260 | static int rs600_gart_init(struct radeon_device *rdev) |
1128 | serge | 261 | { |
262 | int r; |
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263 | |||
2997 | Serge | 264 | if (rdev->gart.robj) { |
1963 | serge | 265 | WARN(1, "RS600 GART already initialized\n"); |
1221 | serge | 266 | return 0; |
267 | } |
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1128 | serge | 268 | /* Initialize common gart structure */ |
269 | r = radeon_gart_init(rdev); |
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270 | if (r) { |
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271 | return r; |
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272 | } |
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273 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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1221 | serge | 274 | return radeon_gart_table_vram_alloc(rdev); |
275 | } |
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276 | |||
2005 | serge | 277 | static int rs600_gart_enable(struct radeon_device *rdev) |
1221 | serge | 278 | { |
279 | u32 tmp; |
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280 | int r, i; |
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281 | |||
2997 | Serge | 282 | if (rdev->gart.robj == NULL) { |
1221 | serge | 283 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
284 | return -EINVAL; |
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285 | } |
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286 | r = radeon_gart_table_vram_pin(rdev); |
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287 | if (r) |
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1128 | serge | 288 | return r; |
1430 | serge | 289 | radeon_gart_restore(rdev); |
1221 | serge | 290 | /* Enable bus master */ |
2005 | serge | 291 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
292 | WREG32(RADEON_BUS_CNTL, tmp); |
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1128 | serge | 293 | /* FIXME: setup default page */ |
1221 | serge | 294 | WREG32_MC(R_000100_MC_PT0_CNTL, |
295 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
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296 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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1321 | serge | 297 | |
1128 | serge | 298 | for (i = 0; i < 19; i++) { |
1221 | serge | 299 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
300 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
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301 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
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1321 | serge | 302 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
1221 | serge | 303 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
1321 | serge | 304 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
305 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
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1221 | serge | 306 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
1321 | serge | 307 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
1128 | serge | 308 | } |
309 | /* enable first context */ |
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1221 | serge | 310 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
311 | S_000102_ENABLE_PAGE_TABLE(1) | |
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312 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
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1321 | serge | 313 | |
1128 | serge | 314 | /* disable all other contexts */ |
1321 | serge | 315 | for (i = 1; i < 8; i++) |
1221 | serge | 316 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
1128 | serge | 317 | |
318 | /* setup the page table */ |
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1221 | serge | 319 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
1128 | serge | 320 | rdev->gart.table_addr); |
1321 | serge | 321 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
322 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
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1221 | serge | 323 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
1128 | serge | 324 | |
1321 | serge | 325 | /* System context maps to VRAM space */ |
326 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
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327 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
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328 | |||
1128 | serge | 329 | /* enable page tables */ |
1221 | serge | 330 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
331 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
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332 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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333 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
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1128 | serge | 334 | rs600_gart_tlb_flush(rdev); |
2997 | Serge | 335 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
336 | (unsigned)(rdev->mc.gtt_size >> 20), |
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337 | (unsigned long long)rdev->gart.table_addr); |
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1128 | serge | 338 | rdev->gart.ready = true; |
339 | return 0; |
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340 | } |
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341 | |||
2997 | Serge | 342 | static void rs600_gart_disable(struct radeon_device *rdev) |
1128 | serge | 343 | { |
1321 | serge | 344 | u32 tmp; |
1128 | serge | 345 | |
346 | /* FIXME: disable out of gart access */ |
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1221 | serge | 347 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
348 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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349 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
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2997 | Serge | 350 | radeon_gart_table_vram_unpin(rdev); |
1128 | serge | 351 | } |
352 | |||
2997 | Serge | 353 | static void rs600_gart_fini(struct radeon_device *rdev) |
1221 | serge | 354 | { |
1963 | serge | 355 | radeon_gart_fini(rdev); |
1221 | serge | 356 | rs600_gart_disable(rdev); |
357 | radeon_gart_table_vram_free(rdev); |
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358 | } |
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359 | |||
1128 | serge | 360 | #define R600_PTE_VALID (1 << 0) |
361 | #define R600_PTE_SYSTEM (1 << 1) |
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362 | #define R600_PTE_SNOOPED (1 << 2) |
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363 | #define R600_PTE_READABLE (1 << 5) |
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364 | #define R600_PTE_WRITEABLE (1 << 6) |
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365 | |||
366 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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367 | { |
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2997 | Serge | 368 | void __iomem *ptr = (void *)rdev->gart.ptr; |
1128 | serge | 369 | |
370 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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371 | return -EINVAL; |
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372 | } |
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373 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
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374 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
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375 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
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2160 | serge | 376 | writeq(addr, ptr + (i * 8)); |
1128 | serge | 377 | return 0; |
378 | } |
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379 | |||
1321 | serge | 380 | int rs600_irq_set(struct radeon_device *rdev) |
381 | { |
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382 | uint32_t tmp = 0; |
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383 | uint32_t mode_int = 0; |
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384 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
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385 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
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386 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
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387 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
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2997 | Serge | 388 | u32 hdmi0; |
389 | if (ASIC_IS_DCE2(rdev)) |
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390 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
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391 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
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392 | else |
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393 | hdmi0 = 0; |
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1128 | serge | 394 | |
1403 | serge | 395 | if (!rdev->irq.installed) { |
1963 | serge | 396 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
1403 | serge | 397 | WREG32(R_000040_GEN_INT_CNTL, 0); |
398 | return -EINVAL; |
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399 | } |
||
2997 | Serge | 400 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
1321 | serge | 401 | tmp |= S_000040_SW_INT_EN(1); |
402 | } |
||
1963 | serge | 403 | if (rdev->irq.crtc_vblank_int[0] || |
2997 | Serge | 404 | atomic_read(&rdev->irq.pflip[0])) { |
1321 | serge | 405 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
406 | } |
||
1963 | serge | 407 | if (rdev->irq.crtc_vblank_int[1] || |
2997 | Serge | 408 | atomic_read(&rdev->irq.pflip[1])) { |
1321 | serge | 409 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
410 | } |
||
411 | if (rdev->irq.hpd[0]) { |
||
412 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
||
413 | } |
||
414 | if (rdev->irq.hpd[1]) { |
||
415 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
||
416 | } |
||
2997 | Serge | 417 | if (rdev->irq.afmt[0]) { |
418 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
419 | } |
||
1321 | serge | 420 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
421 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
||
422 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
||
423 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
||
2997 | Serge | 424 | if (ASIC_IS_DCE2(rdev)) |
425 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1321 | serge | 426 | return 0; |
427 | } |
||
1128 | serge | 428 | |
1963 | serge | 429 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
1128 | serge | 430 | { |
1221 | serge | 431 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
1963 | serge | 432 | uint32_t irq_mask = S_000044_SW_INT(1); |
1321 | serge | 433 | u32 tmp; |
1128 | serge | 434 | |
1221 | serge | 435 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
1963 | serge | 436 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
437 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
1221 | serge | 438 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
439 | S_006534_D1MODE_VBLANK_ACK(1)); |
||
440 | } |
||
1963 | serge | 441 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1221 | serge | 442 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
443 | S_006D34_D2MODE_VBLANK_ACK(1)); |
||
444 | } |
||
1963 | serge | 445 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 446 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
447 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
||
448 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
||
449 | } |
||
1963 | serge | 450 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
1321 | serge | 451 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
452 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
||
453 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
||
454 | } |
||
1221 | serge | 455 | } else { |
1963 | serge | 456 | rdev->irq.stat_regs.r500.disp_int = 0; |
1129 | serge | 457 | } |
1128 | serge | 458 | |
2997 | Serge | 459 | if (ASIC_IS_DCE2(rdev)) { |
460 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
||
461 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
||
462 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
||
463 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
||
464 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
||
465 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
||
466 | } |
||
467 | } else |
||
468 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
||
469 | |||
1221 | serge | 470 | if (irqs) { |
471 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
||
1128 | serge | 472 | } |
1221 | serge | 473 | return irqs & irq_mask; |
1128 | serge | 474 | } |
475 | |||
1221 | serge | 476 | void rs600_irq_disable(struct radeon_device *rdev) |
1128 | serge | 477 | { |
2997 | Serge | 478 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
479 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
||
480 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
||
1221 | serge | 481 | WREG32(R_000040_GEN_INT_CNTL, 0); |
482 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
||
483 | /* Wait and acknowledge irq */ |
||
484 | mdelay(1); |
||
1963 | serge | 485 | rs600_irq_ack(rdev); |
1128 | serge | 486 | } |
487 | |||
2005 | serge | 488 | int rs600_irq_process(struct radeon_device *rdev) |
489 | { |
||
490 | u32 status, msi_rearm; |
||
491 | bool queue_hotplug = false; |
||
2997 | Serge | 492 | bool queue_hdmi = false; |
1128 | serge | 493 | |
2005 | serge | 494 | status = rs600_irq_ack(rdev); |
2997 | Serge | 495 | if (!status && |
496 | !rdev->irq.stat_regs.r500.disp_int && |
||
497 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 498 | return IRQ_NONE; |
499 | } |
||
2997 | Serge | 500 | while (status || |
501 | rdev->irq.stat_regs.r500.disp_int || |
||
502 | rdev->irq.stat_regs.r500.hdmi0_status) { |
||
2005 | serge | 503 | /* SW interrupt */ |
504 | if (G_000044_SW_INT(status)) { |
||
2997 | Serge | 505 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2005 | serge | 506 | } |
507 | /* Vertical blank interrupts */ |
||
508 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
509 | if (rdev->irq.crtc_vblank_int[0]) { |
||
510 | // drm_handle_vblank(rdev->ddev, 0); |
||
511 | rdev->pm.vblank_sync = true; |
||
512 | // wake_up(&rdev->irq.vblank_queue); |
||
513 | } |
||
514 | // if (rdev->irq.pflip[0]) |
||
515 | // radeon_crtc_handle_flip(rdev, 0); |
||
516 | } |
||
517 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
518 | if (rdev->irq.crtc_vblank_int[1]) { |
||
519 | // drm_handle_vblank(rdev->ddev, 1); |
||
520 | rdev->pm.vblank_sync = true; |
||
521 | // wake_up(&rdev->irq.vblank_queue); |
||
522 | } |
||
523 | // if (rdev->irq.pflip[1]) |
||
524 | // radeon_crtc_handle_flip(rdev, 1); |
||
525 | } |
||
526 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
527 | queue_hotplug = true; |
||
528 | DRM_DEBUG("HPD1\n"); |
||
529 | } |
||
530 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
||
531 | queue_hotplug = true; |
||
532 | DRM_DEBUG("HPD2\n"); |
||
533 | } |
||
2997 | Serge | 534 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
535 | queue_hdmi = true; |
||
536 | DRM_DEBUG("HDMI0\n"); |
||
537 | } |
||
2005 | serge | 538 | status = rs600_irq_ack(rdev); |
539 | } |
||
540 | // if (queue_hotplug) |
||
541 | // schedule_work(&rdev->hotplug_work); |
||
2997 | Serge | 542 | // if (queue_hdmi) |
543 | // schedule_work(&rdev->audio_work); |
||
2005 | serge | 544 | if (rdev->msi_enabled) { |
545 | switch (rdev->family) { |
||
546 | case CHIP_RS600: |
||
547 | case CHIP_RS690: |
||
548 | case CHIP_RS740: |
||
549 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
||
550 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
||
551 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
||
552 | break; |
||
553 | default: |
||
2997 | Serge | 554 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
2005 | serge | 555 | break; |
556 | } |
||
557 | } |
||
558 | return IRQ_HANDLED; |
||
559 | } |
||
560 | |||
1221 | serge | 561 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
1128 | serge | 562 | { |
1221 | serge | 563 | if (crtc == 0) |
564 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
||
565 | else |
||
566 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
||
1128 | serge | 567 | } |
568 | |||
569 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
||
570 | { |
||
571 | unsigned i; |
||
572 | |||
573 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1221 | serge | 574 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
1128 | serge | 575 | return 0; |
1221 | serge | 576 | udelay(1); |
1128 | serge | 577 | } |
578 | return -1; |
||
579 | } |
||
580 | |||
2997 | Serge | 581 | static void rs600_gpu_init(struct radeon_device *rdev) |
1128 | serge | 582 | { |
583 | r420_pipes_init(rdev); |
||
1221 | serge | 584 | /* Wait for mc idle */ |
585 | if (rs600_mc_wait_for_idle(rdev)) |
||
586 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
1128 | serge | 587 | } |
588 | |||
2997 | Serge | 589 | static void rs600_mc_init(struct radeon_device *rdev) |
1128 | serge | 590 | { |
1430 | serge | 591 | u64 base; |
592 | |||
1963 | serge | 593 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
594 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
1128 | serge | 595 | rdev->mc.vram_is_ddr = true; |
596 | rdev->mc.vram_width = 128; |
||
1321 | serge | 597 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
598 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1430 | serge | 599 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
600 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
||
601 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
||
602 | base = G_000004_MC_FB_START(base) << 16; |
||
603 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 604 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 605 | radeon_gtt_location(rdev, &rdev->mc); |
1963 | serge | 606 | radeon_update_bandwidth_info(rdev); |
1128 | serge | 607 | } |
608 | |||
1179 | serge | 609 | void rs600_bandwidth_update(struct radeon_device *rdev) |
610 | { |
||
1963 | serge | 611 | struct drm_display_mode *mode0 = NULL; |
612 | struct drm_display_mode *mode1 = NULL; |
||
613 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
||
614 | /* FIXME: implement full support */ |
||
615 | |||
616 | radeon_update_display_priority(rdev); |
||
617 | |||
618 | if (rdev->mode_info.crtcs[0]->base.enabled) |
||
619 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
||
620 | if (rdev->mode_info.crtcs[1]->base.enabled) |
||
621 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
||
622 | |||
623 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
||
624 | |||
625 | if (rdev->disp_priority == 2) { |
||
626 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
||
627 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
||
628 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
||
629 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
||
630 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
||
631 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
||
632 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
||
633 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
||
634 | } |
||
1179 | serge | 635 | } |
1128 | serge | 636 | |
637 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
||
638 | { |
||
1221 | serge | 639 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
640 | S_000070_MC_IND_CITF_ARB0(1)); |
||
641 | return RREG32(R_000074_MC_IND_DATA); |
||
642 | } |
||
1128 | serge | 643 | |
1221 | serge | 644 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
645 | { |
||
646 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
||
647 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
||
648 | WREG32(R_000074_MC_IND_DATA, v); |
||
649 | } |
||
650 | |||
2997 | Serge | 651 | static void rs600_debugfs(struct radeon_device *rdev) |
1221 | serge | 652 | { |
653 | if (r100_debugfs_rbbm_init(rdev)) |
||
654 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
||
655 | } |
||
656 | |||
657 | void rs600_set_safe_registers(struct radeon_device *rdev) |
||
658 | { |
||
659 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
||
660 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
||
661 | } |
||
662 | |||
663 | static void rs600_mc_program(struct radeon_device *rdev) |
||
664 | { |
||
665 | struct rv515_mc_save save; |
||
666 | |||
667 | /* Stops all mc clients */ |
||
668 | rv515_mc_stop(rdev, &save); |
||
669 | |||
670 | /* Wait for mc idle */ |
||
671 | if (rs600_mc_wait_for_idle(rdev)) |
||
672 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
||
673 | |||
674 | /* FIXME: What does AGP means for such chipset ? */ |
||
675 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
676 | WREG32_MC(R_000006_AGP_BASE, 0); |
||
677 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
||
678 | /* Program MC */ |
||
679 | WREG32_MC(R_000004_MC_FB_LOCATION, |
||
680 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
681 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
682 | WREG32(R_000134_HDP_FB_LOCATION, |
||
683 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
||
684 | |||
685 | rv515_mc_resume(rdev, &save); |
||
686 | } |
||
687 | |||
688 | static int rs600_startup(struct radeon_device *rdev) |
||
689 | { |
||
690 | int r; |
||
691 | |||
692 | rs600_mc_program(rdev); |
||
693 | /* Resume clock */ |
||
694 | rv515_clock_startup(rdev); |
||
695 | /* Initialize GPU configuration (# pipes, ...) */ |
||
696 | rs600_gpu_init(rdev); |
||
697 | /* Initialize GART (initialize after TTM so we can allocate |
||
698 | * memory through TTM but finalize after TTM) */ |
||
699 | r = rs600_gart_enable(rdev); |
||
700 | if (r) |
||
1128 | serge | 701 | return r; |
2005 | serge | 702 | |
703 | /* allocate wb buffer */ |
||
704 | r = radeon_wb_init(rdev); |
||
705 | if (r) |
||
706 | return r; |
||
707 | |||
1221 | serge | 708 | /* Enable IRQ */ |
2005 | serge | 709 | rs600_irq_set(rdev); |
1403 | serge | 710 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 711 | /* 1M ring buffer */ |
1413 | serge | 712 | r = r100_cp_init(rdev, 1024 * 1024); |
713 | if (r) { |
||
1963 | serge | 714 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 715 | return r; |
716 | } |
||
2997 | Serge | 717 | |
718 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 719 | if (r) { |
2997 | Serge | 720 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 721 | return r; |
722 | } |
||
2997 | Serge | 723 | |
724 | |||
1221 | serge | 725 | return 0; |
1128 | serge | 726 | } |
727 | |||
1221 | serge | 728 | |
729 | |||
730 | int rs600_init(struct radeon_device *rdev) |
||
1128 | serge | 731 | { |
1221 | serge | 732 | int r; |
733 | |||
734 | /* Disable VGA */ |
||
735 | rv515_vga_render_disable(rdev); |
||
736 | /* Initialize scratch registers */ |
||
737 | radeon_scratch_init(rdev); |
||
738 | /* Initialize surface registers */ |
||
739 | radeon_surface_init(rdev); |
||
1963 | serge | 740 | /* restore some register to sane defaults */ |
741 | r100_restore_sanity(rdev); |
||
1221 | serge | 742 | /* BIOS */ |
743 | if (!radeon_get_bios(rdev)) { |
||
744 | if (ASIC_IS_AVIVO(rdev)) |
||
745 | return -EINVAL; |
||
746 | } |
||
747 | if (rdev->is_atom_bios) { |
||
748 | r = radeon_atombios_init(rdev); |
||
749 | if (r) |
||
750 | return r; |
||
751 | } else { |
||
752 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
||
753 | return -EINVAL; |
||
754 | } |
||
755 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 756 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 757 | dev_warn(rdev->dev, |
758 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
759 | RREG32(R_000E40_RBBM_STATUS), |
||
760 | RREG32(R_0007C0_CP_STAT)); |
||
761 | } |
||
762 | /* check if cards are posted or not */ |
||
1321 | serge | 763 | if (radeon_boot_test_post_card(rdev) == false) |
764 | return -EINVAL; |
||
765 | |||
1221 | serge | 766 | /* Initialize clocks */ |
767 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 768 | /* initialize memory controller */ |
769 | rs600_mc_init(rdev); |
||
1221 | serge | 770 | rs600_debugfs(rdev); |
771 | /* Fence driver */ |
||
2005 | serge | 772 | r = radeon_fence_driver_init(rdev); |
773 | if (r) |
||
774 | return r; |
||
775 | r = radeon_irq_kms_init(rdev); |
||
776 | if (r) |
||
777 | return r; |
||
1221 | serge | 778 | /* Memory manager */ |
1321 | serge | 779 | r = radeon_bo_init(rdev); |
1221 | serge | 780 | if (r) |
781 | return r; |
||
782 | r = rs600_gart_init(rdev); |
||
783 | if (r) |
||
784 | return r; |
||
785 | rs600_set_safe_registers(rdev); |
||
2997 | Serge | 786 | |
1221 | serge | 787 | rdev->accel_working = true; |
788 | r = rs600_startup(rdev); |
||
789 | if (r) { |
||
790 | /* Somethings want wront with the accel init stop accel */ |
||
791 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
792 | // r100_cp_fini(rdev); |
||
793 | // r100_wb_fini(rdev); |
||
794 | // r100_ib_fini(rdev); |
||
795 | rs600_gart_fini(rdev); |
||
796 | // radeon_irq_kms_fini(rdev); |
||
797 | rdev->accel_working = false; |
||
798 | } |
||
799 | return 0; |
||
1128 | serge | 800 | }><>>>><>><>><>><>><>>>><>><>>> |