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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1221 | serge | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
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30 | * This file gather function specific to RS600 which is the IGP of |
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31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
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32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
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33 | * the avivo one, bios is an atombios, 3D block are the one of the |
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34 | * R4XX family. The GART is different from the RS400 one and is very |
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35 | * close to the one of the R600 family (R600 likely being an evolution |
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36 | * of the RS600 GART block). |
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37 | */ |
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1128 | serge | 38 | #include "drmP.h" |
39 | #include "radeon.h" |
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1221 | serge | 40 | #include "atom.h" |
41 | #include "rs600d.h" |
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1128 | serge | 42 | |
1179 | serge | 43 | #include "rs600_reg_safe.h" |
44 | |||
1128 | serge | 45 | void rs600_gpu_init(struct radeon_device *rdev); |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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47 | |||
48 | /* |
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49 | * GART. |
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50 | */ |
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51 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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52 | { |
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53 | uint32_t tmp; |
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54 | |||
1221 | serge | 55 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
56 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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57 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 58 | |
1221 | serge | 59 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
60 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); |
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61 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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1128 | serge | 62 | |
1221 | serge | 63 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
64 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
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65 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
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66 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
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1128 | serge | 67 | } |
68 | |||
1221 | serge | 69 | int rs600_gart_init(struct radeon_device *rdev) |
1128 | serge | 70 | { |
71 | int r; |
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72 | |||
1221 | serge | 73 | if (rdev->gart.table.vram.robj) { |
74 | WARN(1, "RS600 GART already initialized.\n"); |
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75 | return 0; |
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76 | } |
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1128 | serge | 77 | /* Initialize common gart structure */ |
78 | r = radeon_gart_init(rdev); |
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79 | if (r) { |
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80 | return r; |
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81 | } |
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82 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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1221 | serge | 83 | return radeon_gart_table_vram_alloc(rdev); |
84 | } |
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85 | |||
86 | int rs600_gart_enable(struct radeon_device *rdev) |
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87 | { |
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88 | u32 tmp; |
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89 | int r, i; |
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90 | |||
91 | if (rdev->gart.table.vram.robj == NULL) { |
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92 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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93 | return -EINVAL; |
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94 | } |
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95 | r = radeon_gart_table_vram_pin(rdev); |
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96 | if (r) |
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1128 | serge | 97 | return r; |
1221 | serge | 98 | /* Enable bus master */ |
99 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
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100 | WREG32(R_00004C_BUS_CNTL, tmp); |
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1128 | serge | 101 | /* FIXME: setup default page */ |
1221 | serge | 102 | WREG32_MC(R_000100_MC_PT0_CNTL, |
103 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
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104 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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1128 | serge | 105 | for (i = 0; i < 19; i++) { |
1221 | serge | 106 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
107 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
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108 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
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109 | V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | |
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110 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
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111 | V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | |
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112 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | |
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113 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
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114 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); |
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1128 | serge | 115 | } |
116 | |||
117 | /* System context map to GART space */ |
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1221 | serge | 118 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); |
119 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); |
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1128 | serge | 120 | |
121 | /* enable first context */ |
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1221 | serge | 122 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
123 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
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124 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
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125 | S_000102_ENABLE_PAGE_TABLE(1) | |
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126 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
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1128 | serge | 127 | /* disable all other contexts */ |
128 | for (i = 1; i < 8; i++) { |
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1221 | serge | 129 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
1128 | serge | 130 | } |
131 | |||
132 | /* setup the page table */ |
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1221 | serge | 133 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
1128 | serge | 134 | rdev->gart.table_addr); |
1221 | serge | 135 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
1128 | serge | 136 | |
137 | /* enable page tables */ |
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1221 | serge | 138 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
139 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
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140 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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141 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
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1128 | serge | 142 | rs600_gart_tlb_flush(rdev); |
143 | rdev->gart.ready = true; |
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144 | return 0; |
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145 | } |
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146 | |||
147 | void rs600_gart_disable(struct radeon_device *rdev) |
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148 | { |
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149 | uint32_t tmp; |
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150 | |||
151 | /* FIXME: disable out of gart access */ |
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1221 | serge | 152 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
153 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
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154 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
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155 | if (rdev->gart.table.vram.robj) { |
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1128 | serge | 156 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
157 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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1221 | serge | 158 | } |
1128 | serge | 159 | } |
160 | |||
1221 | serge | 161 | void rs600_gart_fini(struct radeon_device *rdev) |
162 | { |
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163 | rs600_gart_disable(rdev); |
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164 | radeon_gart_table_vram_free(rdev); |
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165 | radeon_gart_fini(rdev); |
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166 | } |
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167 | |||
1128 | serge | 168 | #define R600_PTE_VALID (1 << 0) |
169 | #define R600_PTE_SYSTEM (1 << 1) |
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170 | #define R600_PTE_SNOOPED (1 << 2) |
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171 | #define R600_PTE_READABLE (1 << 5) |
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172 | #define R600_PTE_WRITEABLE (1 << 6) |
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173 | |||
174 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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175 | { |
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176 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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177 | |||
178 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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179 | return -EINVAL; |
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180 | } |
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181 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
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182 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
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183 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
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184 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
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185 | return 0; |
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186 | } |
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187 | |||
188 | |||
189 | |||
1221 | serge | 190 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
1128 | serge | 191 | { |
1221 | serge | 192 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
193 | uint32_t irq_mask = ~C_000044_SW_INT; |
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1128 | serge | 194 | |
1221 | serge | 195 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
196 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
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197 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
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198 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
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199 | S_006534_D1MODE_VBLANK_ACK(1)); |
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200 | } |
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201 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
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202 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
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203 | S_006D34_D2MODE_VBLANK_ACK(1)); |
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204 | } |
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205 | } else { |
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206 | *r500_disp_int = 0; |
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1129 | serge | 207 | } |
1128 | serge | 208 | |
1221 | serge | 209 | if (irqs) { |
210 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
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1128 | serge | 211 | } |
1221 | serge | 212 | return irqs & irq_mask; |
1128 | serge | 213 | } |
214 | |||
1221 | serge | 215 | void rs600_irq_disable(struct radeon_device *rdev) |
1128 | serge | 216 | { |
1221 | serge | 217 | u32 tmp; |
218 | |||
219 | WREG32(R_000040_GEN_INT_CNTL, 0); |
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220 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
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221 | /* Wait and acknowledge irq */ |
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222 | mdelay(1); |
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223 | rs600_irq_ack(rdev, &tmp); |
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1128 | serge | 224 | } |
225 | |||
226 | |||
1221 | serge | 227 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
1128 | serge | 228 | { |
1221 | serge | 229 | if (crtc == 0) |
230 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
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231 | else |
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232 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
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1128 | serge | 233 | } |
234 | |||
235 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
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236 | { |
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237 | unsigned i; |
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238 | |||
239 | for (i = 0; i < rdev->usec_timeout; i++) { |
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1221 | serge | 240 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
1128 | serge | 241 | return 0; |
1221 | serge | 242 | udelay(1); |
1128 | serge | 243 | } |
244 | return -1; |
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245 | } |
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246 | |||
247 | void rs600_gpu_init(struct radeon_device *rdev) |
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248 | { |
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249 | /* FIXME: HDP same place on rs600 ? */ |
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250 | r100_hdp_reset(rdev); |
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251 | /* FIXME: is this correct ? */ |
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252 | r420_pipes_init(rdev); |
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1221 | serge | 253 | /* Wait for mc idle */ |
254 | if (rs600_mc_wait_for_idle(rdev)) |
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255 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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1128 | serge | 256 | } |
257 | |||
258 | void rs600_vram_info(struct radeon_device *rdev) |
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259 | { |
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260 | /* FIXME: to do or is these values sane ? */ |
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261 | rdev->mc.vram_is_ddr = true; |
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262 | rdev->mc.vram_width = 128; |
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263 | } |
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264 | |||
1179 | serge | 265 | void rs600_bandwidth_update(struct radeon_device *rdev) |
266 | { |
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267 | /* FIXME: implement, should this be like rs690 ? */ |
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268 | } |
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1128 | serge | 269 | |
270 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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271 | { |
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1221 | serge | 272 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
273 | S_000070_MC_IND_CITF_ARB0(1)); |
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274 | return RREG32(R_000074_MC_IND_DATA); |
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275 | } |
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1128 | serge | 276 | |
1221 | serge | 277 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
278 | { |
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279 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
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280 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
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281 | WREG32(R_000074_MC_IND_DATA, v); |
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282 | } |
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283 | |||
284 | void rs600_debugfs(struct radeon_device *rdev) |
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285 | { |
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286 | if (r100_debugfs_rbbm_init(rdev)) |
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287 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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288 | } |
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289 | |||
290 | void rs600_set_safe_registers(struct radeon_device *rdev) |
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291 | { |
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292 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
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293 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
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294 | } |
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295 | |||
296 | static void rs600_mc_program(struct radeon_device *rdev) |
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297 | { |
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298 | struct rv515_mc_save save; |
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299 | |||
300 | /* Stops all mc clients */ |
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301 | rv515_mc_stop(rdev, &save); |
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302 | |||
303 | /* Wait for mc idle */ |
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304 | if (rs600_mc_wait_for_idle(rdev)) |
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305 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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306 | |||
307 | /* FIXME: What does AGP means for such chipset ? */ |
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308 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
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309 | WREG32_MC(R_000006_AGP_BASE, 0); |
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310 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
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311 | /* Program MC */ |
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312 | WREG32_MC(R_000004_MC_FB_LOCATION, |
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313 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
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314 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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315 | WREG32(R_000134_HDP_FB_LOCATION, |
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316 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
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317 | |||
318 | rv515_mc_resume(rdev, &save); |
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319 | } |
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320 | |||
321 | static int rs600_startup(struct radeon_device *rdev) |
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322 | { |
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323 | int r; |
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324 | |||
325 | rs600_mc_program(rdev); |
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326 | /* Resume clock */ |
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327 | rv515_clock_startup(rdev); |
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328 | /* Initialize GPU configuration (# pipes, ...) */ |
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329 | rs600_gpu_init(rdev); |
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330 | /* Initialize GART (initialize after TTM so we can allocate |
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331 | * memory through TTM but finalize after TTM) */ |
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332 | r = rs600_gart_enable(rdev); |
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333 | if (r) |
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1128 | serge | 334 | return r; |
1221 | serge | 335 | /* Enable IRQ */ |
336 | // rdev->irq.sw_int = true; |
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337 | // rs600_irq_set(rdev); |
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338 | /* 1M ring buffer */ |
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339 | // r = r100_cp_init(rdev, 1024 * 1024); |
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340 | // if (r) { |
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341 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
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342 | // return r; |
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343 | // } |
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344 | // r = r100_wb_init(rdev); |
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345 | // if (r) |
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346 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
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347 | // r = r100_ib_init(rdev); |
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348 | // if (r) { |
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349 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
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350 | // return r; |
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351 | // } |
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352 | return 0; |
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1128 | serge | 353 | } |
354 | |||
1221 | serge | 355 | |
356 | |||
357 | int rs600_init(struct radeon_device *rdev) |
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1128 | serge | 358 | { |
1221 | serge | 359 | int r; |
360 | |||
361 | /* Disable VGA */ |
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362 | rv515_vga_render_disable(rdev); |
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363 | /* Initialize scratch registers */ |
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364 | radeon_scratch_init(rdev); |
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365 | /* Initialize surface registers */ |
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366 | radeon_surface_init(rdev); |
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367 | /* BIOS */ |
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368 | if (!radeon_get_bios(rdev)) { |
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369 | if (ASIC_IS_AVIVO(rdev)) |
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370 | return -EINVAL; |
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371 | } |
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372 | if (rdev->is_atom_bios) { |
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373 | r = radeon_atombios_init(rdev); |
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374 | if (r) |
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375 | return r; |
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376 | } else { |
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377 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
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378 | return -EINVAL; |
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379 | } |
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380 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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381 | if (radeon_gpu_reset(rdev)) { |
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382 | dev_warn(rdev->dev, |
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383 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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384 | RREG32(R_000E40_RBBM_STATUS), |
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385 | RREG32(R_0007C0_CP_STAT)); |
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386 | } |
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387 | /* check if cards are posted or not */ |
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388 | if (!radeon_card_posted(rdev) && rdev->bios) { |
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389 | DRM_INFO("GPU not posted. posting now...\n"); |
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390 | atom_asic_init(rdev->mode_info.atom_context); |
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391 | } |
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392 | /* Initialize clocks */ |
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393 | radeon_get_clock_info(rdev->ddev); |
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394 | /* Get vram informations */ |
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395 | rs600_vram_info(rdev); |
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396 | /* Initialize memory controller (also test AGP) */ |
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397 | r = r420_mc_init(rdev); |
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398 | if (r) |
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399 | return r; |
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400 | rs600_debugfs(rdev); |
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401 | /* Fence driver */ |
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402 | // r = radeon_fence_driver_init(rdev); |
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403 | // if (r) |
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404 | // return r; |
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405 | // r = radeon_irq_kms_init(rdev); |
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406 | // if (r) |
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407 | // return r; |
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408 | /* Memory manager */ |
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409 | r = radeon_object_init(rdev); |
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410 | if (r) |
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411 | return r; |
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412 | r = rs600_gart_init(rdev); |
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413 | if (r) |
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414 | return r; |
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415 | rs600_set_safe_registers(rdev); |
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416 | rdev->accel_working = true; |
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417 | r = rs600_startup(rdev); |
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418 | if (r) { |
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419 | /* Somethings want wront with the accel init stop accel */ |
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420 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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421 | // rs600_suspend(rdev); |
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422 | // r100_cp_fini(rdev); |
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423 | // r100_wb_fini(rdev); |
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424 | // r100_ib_fini(rdev); |
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425 | rs600_gart_fini(rdev); |
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426 | // radeon_irq_kms_fini(rdev); |
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427 | rdev->accel_working = false; |
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428 | } |
||
429 | return 0; |
||
1128 | serge | 430 | }>>><>><>><>><>><>>> |