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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include "drmP.h" |
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29 | #include "radeon_reg.h" |
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30 | #include "radeon.h" |
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1179 | serge | 31 | #include "avivod.h" |
1128 | serge | 32 | |
1179 | serge | 33 | #include "rs600_reg_safe.h" |
34 | |||
1128 | serge | 35 | /* rs600 depends on : */ |
36 | void r100_hdp_reset(struct radeon_device *rdev); |
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37 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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38 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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39 | void r420_pipes_init(struct radeon_device *rdev); |
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40 | |||
41 | /* This files gather functions specifics to : |
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42 | * rs600 |
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43 | * |
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44 | * Some of these functions might be used by newer ASICs. |
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45 | */ |
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46 | void rs600_gpu_init(struct radeon_device *rdev); |
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47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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48 | void rs600_disable_vga(struct radeon_device *rdev); |
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49 | |||
50 | |||
51 | /* |
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52 | * GART. |
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53 | */ |
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54 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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55 | { |
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56 | uint32_t tmp; |
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57 | |||
58 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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59 | tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
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60 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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61 | |||
62 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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63 | tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; |
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64 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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65 | |||
66 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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67 | tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
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68 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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69 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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70 | } |
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71 | |||
72 | int rs600_gart_enable(struct radeon_device *rdev) |
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73 | { |
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74 | uint32_t tmp; |
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75 | int i; |
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76 | int r; |
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77 | |||
78 | /* Initialize common gart structure */ |
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79 | r = radeon_gart_init(rdev); |
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80 | if (r) { |
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81 | return r; |
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82 | } |
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83 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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84 | r = radeon_gart_table_vram_alloc(rdev); |
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85 | if (r) { |
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86 | return r; |
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87 | } |
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88 | /* FIXME: setup default page */ |
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89 | WREG32_MC(RS600_MC_PT0_CNTL, |
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90 | (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | |
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91 | RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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92 | for (i = 0; i < 19; i++) { |
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93 | WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i, |
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94 | (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | |
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95 | RS600_SYSTEM_ACCESS_MODE_IN_SYS | |
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96 | RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE | |
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97 | RS600_EFFECTIVE_L1_CACHE_SIZE(3) | |
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98 | RS600_ENABLE_FRAGMENT_PROCESSING | |
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99 | RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); |
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100 | } |
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101 | |||
102 | /* System context map to GART space */ |
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103 | WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location); |
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104 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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105 | WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
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106 | |||
107 | /* enable first context */ |
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108 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location); |
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109 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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110 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp); |
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111 | WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL, |
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112 | (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT)); |
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113 | /* disable all other contexts */ |
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114 | for (i = 1; i < 8; i++) { |
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115 | WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); |
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116 | } |
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117 | |||
118 | /* setup the page table */ |
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119 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
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120 | rdev->gart.table_addr); |
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121 | WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
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122 | |||
123 | /* enable page tables */ |
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124 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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125 | WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT)); |
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126 | tmp = RREG32_MC(RS600_MC_CNTL1); |
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127 | WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES)); |
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128 | rs600_gart_tlb_flush(rdev); |
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129 | rdev->gart.ready = true; |
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130 | return 0; |
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131 | } |
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132 | |||
133 | void rs600_gart_disable(struct radeon_device *rdev) |
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134 | { |
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135 | uint32_t tmp; |
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136 | |||
137 | /* FIXME: disable out of gart access */ |
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138 | WREG32_MC(RS600_MC_PT0_CNTL, 0); |
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139 | tmp = RREG32_MC(RS600_MC_CNTL1); |
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140 | tmp &= ~RS600_ENABLE_PAGE_TABLES; |
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141 | WREG32_MC(RS600_MC_CNTL1, tmp); |
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142 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
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143 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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144 | } |
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145 | |||
146 | #define R600_PTE_VALID (1 << 0) |
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147 | #define R600_PTE_SYSTEM (1 << 1) |
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148 | #define R600_PTE_SNOOPED (1 << 2) |
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149 | #define R600_PTE_READABLE (1 << 5) |
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150 | #define R600_PTE_WRITEABLE (1 << 6) |
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151 | |||
152 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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153 | { |
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154 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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155 | |||
156 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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157 | return -EINVAL; |
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158 | } |
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159 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
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160 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
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161 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
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162 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
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163 | return 0; |
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164 | } |
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165 | |||
166 | |||
167 | /* |
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168 | * MC. |
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169 | */ |
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170 | void rs600_mc_disable_clients(struct radeon_device *rdev) |
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171 | { |
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172 | unsigned tmp; |
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173 | |||
174 | if (r100_gui_wait_for_idle(rdev)) { |
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175 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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176 | "programming pipes. Bad things might happen.\n"); |
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177 | } |
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178 | |||
179 | tmp = RREG32(AVIVO_D1VGA_CONTROL); |
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180 | WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
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181 | tmp = RREG32(AVIVO_D2VGA_CONTROL); |
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182 | WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
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183 | |||
184 | tmp = RREG32(AVIVO_D1CRTC_CONTROL); |
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185 | WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
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186 | tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
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187 | WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
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188 | |||
189 | /* make sure all previous write got through */ |
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190 | tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
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191 | |||
192 | mdelay(1); |
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193 | } |
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194 | |||
195 | int rs600_mc_init(struct radeon_device *rdev) |
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196 | { |
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197 | uint32_t tmp; |
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198 | int r; |
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199 | |||
1129 | serge | 200 | if (r100_debugfs_rbbm_init(rdev)) { |
201 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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202 | } |
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1128 | serge | 203 | |
204 | rs600_gpu_init(rdev); |
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205 | rs600_gart_disable(rdev); |
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206 | |||
207 | /* Setup GPU memory space */ |
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208 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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209 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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210 | r = radeon_mc_setup(rdev); |
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211 | if (r) { |
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212 | return r; |
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213 | } |
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214 | |||
215 | /* Program GPU memory space */ |
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216 | /* Enable bus master */ |
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217 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
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218 | WREG32(RADEON_BUS_CNTL, tmp); |
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219 | /* FIXME: What does AGP means for such chipset ? */ |
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220 | WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF); |
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221 | /* FIXME: are this AGP reg in indirect MC range ? */ |
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222 | WREG32_MC(RS600_MC_AGP_BASE, 0); |
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223 | WREG32_MC(RS600_MC_AGP_BASE_2, 0); |
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224 | rs600_mc_disable_clients(rdev); |
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225 | if (rs600_mc_wait_for_idle(rdev)) { |
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226 | printk(KERN_WARNING "Failed to wait MC idle while " |
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227 | "programming pipes. Bad things might happen.\n"); |
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228 | } |
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1179 | serge | 229 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
1128 | serge | 230 | tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); |
231 | tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); |
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232 | WREG32_MC(RS600_MC_FB_LOCATION, tmp); |
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233 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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234 | return 0; |
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235 | } |
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236 | |||
237 | void rs600_mc_fini(struct radeon_device *rdev) |
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238 | { |
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239 | rs600_gart_disable(rdev); |
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240 | radeon_gart_table_vram_free(rdev); |
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241 | radeon_gart_fini(rdev); |
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242 | } |
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243 | |||
244 | |||
245 | /* |
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246 | * Global GPU functions |
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247 | */ |
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248 | void rs600_disable_vga(struct radeon_device *rdev) |
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249 | { |
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250 | unsigned tmp; |
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251 | |||
252 | WREG32(0x330, 0); |
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253 | WREG32(0x338, 0); |
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254 | tmp = RREG32(0x300); |
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255 | tmp &= ~(3 << 16); |
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256 | WREG32(0x300, tmp); |
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257 | WREG32(0x308, (1 << 8)); |
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258 | WREG32(0x310, rdev->mc.vram_location); |
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259 | WREG32(0x594, 0); |
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260 | } |
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261 | |||
262 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
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263 | { |
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264 | unsigned i; |
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265 | uint32_t tmp; |
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266 | |||
267 | for (i = 0; i < rdev->usec_timeout; i++) { |
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268 | /* read MC_STATUS */ |
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269 | tmp = RREG32_MC(RS600_MC_STATUS); |
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270 | if (tmp & RS600_MC_STATUS_IDLE) { |
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271 | return 0; |
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272 | } |
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273 | DRM_UDELAY(1); |
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274 | } |
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275 | return -1; |
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276 | } |
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277 | |||
278 | void rs600_errata(struct radeon_device *rdev) |
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279 | { |
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280 | rdev->pll_errata = 0; |
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281 | } |
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282 | |||
283 | void rs600_gpu_init(struct radeon_device *rdev) |
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284 | { |
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285 | /* FIXME: HDP same place on rs600 ? */ |
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286 | r100_hdp_reset(rdev); |
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287 | rs600_disable_vga(rdev); |
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288 | /* FIXME: is this correct ? */ |
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289 | r420_pipes_init(rdev); |
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290 | if (rs600_mc_wait_for_idle(rdev)) { |
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291 | printk(KERN_WARNING "Failed to wait MC idle while " |
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292 | "programming pipes. Bad things might happen.\n"); |
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293 | } |
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294 | } |
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295 | |||
296 | |||
297 | /* |
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298 | * VRAM info. |
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299 | */ |
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300 | void rs600_vram_info(struct radeon_device *rdev) |
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301 | { |
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302 | /* FIXME: to do or is these values sane ? */ |
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303 | rdev->mc.vram_is_ddr = true; |
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304 | rdev->mc.vram_width = 128; |
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305 | } |
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306 | |||
1179 | serge | 307 | void rs600_bandwidth_update(struct radeon_device *rdev) |
308 | { |
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309 | /* FIXME: implement, should this be like rs690 ? */ |
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310 | } |
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1128 | serge | 311 | |
1179 | serge | 312 | |
1128 | serge | 313 | /* |
314 | * Indirect registers accessor |
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315 | */ |
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316 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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317 | { |
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318 | uint32_t r; |
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319 | |||
320 | WREG32(RS600_MC_INDEX, |
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321 | ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); |
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322 | r = RREG32(RS600_MC_DATA); |
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323 | return r; |
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324 | } |
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325 | |||
326 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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327 | { |
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328 | WREG32(RS600_MC_INDEX, |
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329 | RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | |
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330 | ((reg) & RS600_MC_ADDR_MASK)); |
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331 | WREG32(RS600_MC_DATA, v); |
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332 | }>><>><>>><>><>><>><>><>>> |