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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include "drmP.h" |
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29 | #include "radeon_reg.h" |
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30 | #include "radeon.h" |
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31 | |||
32 | /* rs600 depends on : */ |
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33 | void r100_hdp_reset(struct radeon_device *rdev); |
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34 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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35 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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36 | void r420_pipes_init(struct radeon_device *rdev); |
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37 | |||
38 | /* This files gather functions specifics to : |
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39 | * rs600 |
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40 | * |
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41 | * Some of these functions might be used by newer ASICs. |
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42 | */ |
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43 | void rs600_gpu_init(struct radeon_device *rdev); |
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44 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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45 | void rs600_disable_vga(struct radeon_device *rdev); |
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46 | |||
47 | |||
48 | /* |
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49 | * GART. |
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50 | */ |
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51 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
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52 | { |
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53 | uint32_t tmp; |
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54 | |||
55 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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56 | tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
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57 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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58 | |||
59 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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60 | tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; |
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61 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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62 | |||
63 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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64 | tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
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65 | WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
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66 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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67 | } |
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68 | |||
69 | int rs600_gart_enable(struct radeon_device *rdev) |
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70 | { |
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71 | uint32_t tmp; |
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72 | int i; |
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73 | int r; |
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74 | |||
75 | /* Initialize common gart structure */ |
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76 | r = radeon_gart_init(rdev); |
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77 | if (r) { |
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78 | return r; |
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79 | } |
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80 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
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81 | r = radeon_gart_table_vram_alloc(rdev); |
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82 | if (r) { |
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83 | return r; |
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84 | } |
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85 | /* FIXME: setup default page */ |
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86 | WREG32_MC(RS600_MC_PT0_CNTL, |
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87 | (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | |
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88 | RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); |
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89 | for (i = 0; i < 19; i++) { |
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90 | WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i, |
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91 | (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | |
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92 | RS600_SYSTEM_ACCESS_MODE_IN_SYS | |
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93 | RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE | |
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94 | RS600_EFFECTIVE_L1_CACHE_SIZE(3) | |
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95 | RS600_ENABLE_FRAGMENT_PROCESSING | |
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96 | RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); |
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97 | } |
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98 | |||
99 | /* System context map to GART space */ |
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100 | WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location); |
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101 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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102 | WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
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103 | |||
104 | /* enable first context */ |
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105 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location); |
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106 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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107 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp); |
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108 | WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL, |
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109 | (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT)); |
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110 | /* disable all other contexts */ |
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111 | for (i = 1; i < 8; i++) { |
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112 | WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); |
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113 | } |
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114 | |||
115 | /* setup the page table */ |
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116 | WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
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117 | rdev->gart.table_addr); |
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118 | WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
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119 | |||
120 | /* enable page tables */ |
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121 | tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
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122 | WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT)); |
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123 | tmp = RREG32_MC(RS600_MC_CNTL1); |
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124 | WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES)); |
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125 | rs600_gart_tlb_flush(rdev); |
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126 | rdev->gart.ready = true; |
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127 | return 0; |
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128 | } |
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129 | |||
130 | void rs600_gart_disable(struct radeon_device *rdev) |
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131 | { |
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132 | uint32_t tmp; |
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133 | |||
134 | /* FIXME: disable out of gart access */ |
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135 | WREG32_MC(RS600_MC_PT0_CNTL, 0); |
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136 | tmp = RREG32_MC(RS600_MC_CNTL1); |
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137 | tmp &= ~RS600_ENABLE_PAGE_TABLES; |
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138 | WREG32_MC(RS600_MC_CNTL1, tmp); |
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139 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
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140 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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141 | } |
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142 | |||
143 | #define R600_PTE_VALID (1 << 0) |
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144 | #define R600_PTE_SYSTEM (1 << 1) |
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145 | #define R600_PTE_SNOOPED (1 << 2) |
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146 | #define R600_PTE_READABLE (1 << 5) |
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147 | #define R600_PTE_WRITEABLE (1 << 6) |
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148 | |||
149 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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150 | { |
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151 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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152 | |||
153 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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154 | return -EINVAL; |
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155 | } |
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156 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
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157 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
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158 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
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159 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
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160 | return 0; |
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161 | } |
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162 | |||
163 | |||
164 | /* |
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165 | * MC. |
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166 | */ |
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167 | void rs600_mc_disable_clients(struct radeon_device *rdev) |
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168 | { |
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169 | unsigned tmp; |
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170 | |||
171 | if (r100_gui_wait_for_idle(rdev)) { |
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172 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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173 | "programming pipes. Bad things might happen.\n"); |
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174 | } |
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175 | |||
176 | tmp = RREG32(AVIVO_D1VGA_CONTROL); |
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177 | WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
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178 | tmp = RREG32(AVIVO_D2VGA_CONTROL); |
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179 | WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
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180 | |||
181 | tmp = RREG32(AVIVO_D1CRTC_CONTROL); |
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182 | WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
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183 | tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
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184 | WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
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185 | |||
186 | /* make sure all previous write got through */ |
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187 | tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
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188 | |||
189 | mdelay(1); |
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190 | } |
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191 | |||
192 | int rs600_mc_init(struct radeon_device *rdev) |
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193 | { |
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194 | uint32_t tmp; |
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195 | int r; |
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196 | |||
1129 | serge | 197 | if (r100_debugfs_rbbm_init(rdev)) { |
198 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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199 | } |
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1128 | serge | 200 | |
201 | rs600_gpu_init(rdev); |
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202 | rs600_gart_disable(rdev); |
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203 | |||
204 | /* Setup GPU memory space */ |
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205 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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206 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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207 | r = radeon_mc_setup(rdev); |
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208 | if (r) { |
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209 | return r; |
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210 | } |
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211 | |||
212 | /* Program GPU memory space */ |
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213 | /* Enable bus master */ |
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214 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
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215 | WREG32(RADEON_BUS_CNTL, tmp); |
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216 | /* FIXME: What does AGP means for such chipset ? */ |
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217 | WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF); |
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218 | /* FIXME: are this AGP reg in indirect MC range ? */ |
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219 | WREG32_MC(RS600_MC_AGP_BASE, 0); |
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220 | WREG32_MC(RS600_MC_AGP_BASE_2, 0); |
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221 | rs600_mc_disable_clients(rdev); |
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222 | if (rs600_mc_wait_for_idle(rdev)) { |
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223 | printk(KERN_WARNING "Failed to wait MC idle while " |
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224 | "programming pipes. Bad things might happen.\n"); |
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225 | } |
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226 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
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227 | tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); |
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228 | tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); |
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229 | WREG32_MC(RS600_MC_FB_LOCATION, tmp); |
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230 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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231 | return 0; |
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232 | } |
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233 | |||
234 | void rs600_mc_fini(struct radeon_device *rdev) |
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235 | { |
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236 | rs600_gart_disable(rdev); |
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237 | radeon_gart_table_vram_free(rdev); |
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238 | radeon_gart_fini(rdev); |
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239 | } |
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240 | |||
241 | |||
242 | /* |
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243 | * Global GPU functions |
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244 | */ |
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245 | void rs600_disable_vga(struct radeon_device *rdev) |
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246 | { |
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247 | unsigned tmp; |
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248 | |||
249 | WREG32(0x330, 0); |
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250 | WREG32(0x338, 0); |
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251 | tmp = RREG32(0x300); |
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252 | tmp &= ~(3 << 16); |
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253 | WREG32(0x300, tmp); |
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254 | WREG32(0x308, (1 << 8)); |
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255 | WREG32(0x310, rdev->mc.vram_location); |
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256 | WREG32(0x594, 0); |
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257 | } |
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258 | |||
259 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
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260 | { |
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261 | unsigned i; |
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262 | uint32_t tmp; |
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263 | |||
264 | for (i = 0; i < rdev->usec_timeout; i++) { |
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265 | /* read MC_STATUS */ |
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266 | tmp = RREG32_MC(RS600_MC_STATUS); |
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267 | if (tmp & RS600_MC_STATUS_IDLE) { |
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268 | return 0; |
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269 | } |
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270 | DRM_UDELAY(1); |
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271 | } |
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272 | return -1; |
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273 | } |
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274 | |||
275 | void rs600_errata(struct radeon_device *rdev) |
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276 | { |
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277 | rdev->pll_errata = 0; |
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278 | } |
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279 | |||
280 | void rs600_gpu_init(struct radeon_device *rdev) |
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281 | { |
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282 | /* FIXME: HDP same place on rs600 ? */ |
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283 | r100_hdp_reset(rdev); |
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284 | rs600_disable_vga(rdev); |
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285 | /* FIXME: is this correct ? */ |
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286 | r420_pipes_init(rdev); |
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287 | if (rs600_mc_wait_for_idle(rdev)) { |
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288 | printk(KERN_WARNING "Failed to wait MC idle while " |
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289 | "programming pipes. Bad things might happen.\n"); |
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290 | } |
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291 | } |
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292 | |||
293 | |||
294 | /* |
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295 | * VRAM info. |
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296 | */ |
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297 | void rs600_vram_info(struct radeon_device *rdev) |
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298 | { |
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299 | /* FIXME: to do or is these values sane ? */ |
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300 | rdev->mc.vram_is_ddr = true; |
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301 | rdev->mc.vram_width = 128; |
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302 | } |
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303 | |||
304 | |||
305 | /* |
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306 | * Indirect registers accessor |
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307 | */ |
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308 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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309 | { |
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310 | uint32_t r; |
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311 | |||
312 | WREG32(RS600_MC_INDEX, |
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313 | ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); |
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314 | r = RREG32(RS600_MC_DATA); |
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315 | return r; |
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316 | } |
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317 | |||
318 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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319 | { |
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320 | WREG32(RS600_MC_INDEX, |
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321 | RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | |
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322 | ((reg) & RS600_MC_ADDR_MASK)); |
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323 | WREG32(RS600_MC_DATA, v); |
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324 | }>><>><>>><>><>><>><>><>>> |