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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
29 | #include |
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1128 | serge | 30 | #include "radeon_reg.h" |
31 | #include "radeon.h" |
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32 | |||
33 | /* rs400,rs480 depends on : */ |
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34 | void r100_hdp_reset(struct radeon_device *rdev); |
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35 | void r100_mc_disable_clients(struct radeon_device *rdev); |
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36 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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37 | void r420_pipes_init(struct radeon_device *rdev); |
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38 | |||
39 | /* This files gather functions specifics to : |
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40 | * rs400,rs480 |
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41 | * |
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42 | * Some of these functions might be used by newer ASICs. |
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43 | */ |
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44 | void rs400_gpu_init(struct radeon_device *rdev); |
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45 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
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46 | |||
47 | |||
48 | /* |
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49 | * GART functions. |
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50 | */ |
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51 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
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52 | { |
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53 | /* Check gart size */ |
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54 | switch (rdev->mc.gtt_size/(1024*1024)) { |
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55 | case 32: |
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56 | case 64: |
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57 | case 128: |
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58 | case 256: |
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59 | case 512: |
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60 | case 1024: |
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61 | case 2048: |
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62 | break; |
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63 | default: |
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64 | DRM_ERROR("Unable to use IGP GART size %uM\n", |
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1179 | serge | 65 | (unsigned)(rdev->mc.gtt_size >> 20)); |
1128 | serge | 66 | DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); |
67 | DRM_ERROR("Forcing to 32M GART size\n"); |
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68 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
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69 | return; |
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70 | } |
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71 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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72 | /* FIXME: RS400 & RS480 seems to have issue with GART size |
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73 | * if 4G of system memory (needs more testing) */ |
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74 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
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75 | DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); |
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76 | } |
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77 | } |
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78 | |||
79 | void rs400_gart_tlb_flush(struct radeon_device *rdev) |
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80 | { |
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81 | uint32_t tmp; |
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82 | unsigned int timeout = rdev->usec_timeout; |
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83 | |||
84 | WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); |
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85 | do { |
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86 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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87 | if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) |
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88 | break; |
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89 | DRM_UDELAY(1); |
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90 | timeout--; |
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91 | } while (timeout > 0); |
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92 | WREG32_MC(RS480_GART_CACHE_CNTRL, 0); |
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93 | } |
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94 | |||
1179 | serge | 95 | int rs400_gart_init(struct radeon_device *rdev) |
1128 | serge | 96 | { |
97 | int r; |
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98 | |||
1179 | serge | 99 | if (rdev->gart.table.ram.ptr) { |
100 | WARN(1, "RS400 GART already initialized.\n"); |
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101 | return 0; |
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102 | } |
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103 | /* Check gart size */ |
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104 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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105 | case 32: |
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106 | case 64: |
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107 | case 128: |
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108 | case 256: |
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109 | case 512: |
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110 | case 1024: |
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111 | case 2048: |
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112 | break; |
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113 | default: |
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114 | return -EINVAL; |
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115 | } |
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1128 | serge | 116 | /* Initialize common gart structure */ |
117 | r = radeon_gart_init(rdev); |
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1179 | serge | 118 | if (r) |
1128 | serge | 119 | return r; |
1179 | serge | 120 | if (rs400_debugfs_pcie_gart_info_init(rdev)) |
1128 | serge | 121 | DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); |
1179 | serge | 122 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
123 | return radeon_gart_table_ram_alloc(rdev); |
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124 | } |
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1128 | serge | 125 | |
1179 | serge | 126 | int rs400_gart_enable(struct radeon_device *rdev) |
127 | { |
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128 | uint32_t size_reg; |
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129 | uint32_t tmp; |
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130 | |||
1128 | serge | 131 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
132 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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133 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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134 | /* Check gart size */ |
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135 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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136 | case 32: |
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137 | size_reg = RS480_VA_SIZE_32MB; |
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138 | break; |
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139 | case 64: |
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140 | size_reg = RS480_VA_SIZE_64MB; |
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141 | break; |
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142 | case 128: |
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143 | size_reg = RS480_VA_SIZE_128MB; |
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144 | break; |
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145 | case 256: |
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146 | size_reg = RS480_VA_SIZE_256MB; |
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147 | break; |
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148 | case 512: |
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149 | size_reg = RS480_VA_SIZE_512MB; |
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150 | break; |
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151 | case 1024: |
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152 | size_reg = RS480_VA_SIZE_1GB; |
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153 | break; |
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154 | case 2048: |
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155 | size_reg = RS480_VA_SIZE_2GB; |
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156 | break; |
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157 | default: |
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158 | return -EINVAL; |
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159 | } |
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160 | /* It should be fine to program it to max value */ |
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161 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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162 | WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); |
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163 | WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); |
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164 | } else { |
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165 | WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); |
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166 | WREG32(RS480_AGP_BASE_2, 0); |
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167 | } |
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168 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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169 | tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); |
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170 | tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16); |
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171 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
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172 | WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); |
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173 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
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174 | WREG32(RADEON_BUS_CNTL, tmp); |
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175 | } else { |
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176 | WREG32(RADEON_MC_AGP_LOCATION, tmp); |
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177 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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178 | WREG32(RADEON_BUS_CNTL, tmp); |
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179 | } |
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180 | /* Table should be in 32bits address space so ignore bits above. */ |
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1179 | serge | 181 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
182 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; |
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183 | |||
1128 | serge | 184 | WREG32_MC(RS480_GART_BASE, tmp); |
185 | /* TODO: more tweaking here */ |
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186 | WREG32_MC(RS480_GART_FEATURE_ID, |
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187 | (RS480_TLB_ENABLE | |
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188 | RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); |
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189 | /* Disable snooping */ |
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190 | WREG32_MC(RS480_AGP_MODE_CNTL, |
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191 | (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); |
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192 | /* Disable AGP mode */ |
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193 | /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
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194 | * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
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195 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
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196 | WREG32_MC(RS480_MC_MISC_CNTL, |
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197 | (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); |
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198 | } else { |
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199 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
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200 | } |
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201 | /* Enable gart */ |
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202 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
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203 | rs400_gart_tlb_flush(rdev); |
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204 | rdev->gart.ready = true; |
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205 | return 0; |
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206 | } |
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207 | |||
208 | void rs400_gart_disable(struct radeon_device *rdev) |
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209 | { |
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210 | uint32_t tmp; |
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211 | |||
212 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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213 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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214 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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215 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
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216 | } |
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217 | |||
1179 | serge | 218 | void rs400_gart_fini(struct radeon_device *rdev) |
219 | { |
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220 | rs400_gart_disable(rdev); |
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221 | radeon_gart_table_ram_free(rdev); |
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222 | radeon_gart_fini(rdev); |
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223 | } |
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224 | |||
1128 | serge | 225 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
226 | { |
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1179 | serge | 227 | uint32_t entry; |
228 | |||
1128 | serge | 229 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
230 | return -EINVAL; |
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231 | } |
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1179 | serge | 232 | |
233 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
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234 | ((upper_32_bits(addr) & 0xff) << 4) | |
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235 | 0xc; |
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236 | entry = cpu_to_le32(entry); |
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237 | rdev->gart.table.ram.ptr[i] = entry; |
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1128 | serge | 238 | return 0; |
239 | } |
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240 | |||
241 | |||
242 | /* |
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243 | * MC functions. |
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244 | */ |
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245 | int rs400_mc_init(struct radeon_device *rdev) |
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246 | { |
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247 | uint32_t tmp; |
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248 | int r; |
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249 | |||
1129 | serge | 250 | if (r100_debugfs_rbbm_init(rdev)) { |
251 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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252 | } |
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1128 | serge | 253 | |
254 | rs400_gpu_init(rdev); |
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255 | rs400_gart_disable(rdev); |
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1179 | serge | 256 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
1128 | serge | 257 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
258 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
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259 | r = radeon_mc_setup(rdev); |
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260 | if (r) { |
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261 | return r; |
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262 | } |
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263 | |||
264 | r100_mc_disable_clients(rdev); |
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265 | if (r300_mc_wait_for_idle(rdev)) { |
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266 | printk(KERN_WARNING "Failed to wait MC idle while " |
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267 | "programming pipes. Bad things might happen.\n"); |
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268 | } |
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269 | |||
1179 | serge | 270 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
1128 | serge | 271 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
272 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
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273 | WREG32(RADEON_MC_FB_LOCATION, tmp); |
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274 | tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS; |
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275 | WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
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276 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
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277 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
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278 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
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1179 | serge | 279 | |
1128 | serge | 280 | return 0; |
281 | } |
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282 | |||
283 | void rs400_mc_fini(struct radeon_device *rdev) |
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284 | { |
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285 | } |
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286 | |||
287 | |||
288 | /* |
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289 | * Global GPU functions |
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290 | */ |
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291 | void rs400_errata(struct radeon_device *rdev) |
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292 | { |
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293 | rdev->pll_errata = 0; |
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294 | } |
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295 | |||
296 | void rs400_gpu_init(struct radeon_device *rdev) |
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297 | { |
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298 | /* FIXME: HDP same place on rs400 ? */ |
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299 | r100_hdp_reset(rdev); |
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300 | /* FIXME: is this correct ? */ |
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301 | r420_pipes_init(rdev); |
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302 | if (r300_mc_wait_for_idle(rdev)) { |
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303 | printk(KERN_WARNING "Failed to wait MC idle while " |
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304 | "programming pipes. Bad things might happen.\n"); |
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305 | } |
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306 | } |
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307 | |||
308 | |||
309 | /* |
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310 | * VRAM info. |
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311 | */ |
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312 | void rs400_vram_info(struct radeon_device *rdev) |
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313 | { |
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314 | rs400_gart_adjust_size(rdev); |
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315 | /* DDR for all card after R300 & IGP */ |
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316 | rdev->mc.vram_is_ddr = true; |
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317 | rdev->mc.vram_width = 128; |
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318 | |||
1179 | serge | 319 | r100_vram_init_sizes(rdev); |
1128 | serge | 320 | } |
321 | |||
322 | |||
323 | /* |
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324 | * Indirect registers accessor |
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325 | */ |
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326 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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327 | { |
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328 | uint32_t r; |
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329 | |||
330 | WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
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331 | r = RREG32(RS480_NB_MC_DATA); |
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332 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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333 | return r; |
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334 | } |
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335 | |||
336 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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337 | { |
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338 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
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339 | WREG32(RS480_NB_MC_DATA, (v)); |
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340 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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341 | } |
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342 | |||
343 | |||
344 | /* |
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345 | * Debugfs info |
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346 | */ |
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347 | #if defined(CONFIG_DEBUG_FS) |
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348 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
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349 | { |
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350 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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351 | struct drm_device *dev = node->minor->dev; |
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352 | struct radeon_device *rdev = dev->dev_private; |
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353 | uint32_t tmp; |
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354 | |||
355 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
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356 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
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357 | tmp = RREG32(RADEON_BUS_CNTL); |
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358 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
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359 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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360 | seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); |
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361 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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362 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); |
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363 | seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); |
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364 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); |
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365 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
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366 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
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367 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
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368 | tmp = RREG32_MC(0x100); |
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369 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
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370 | tmp = RREG32(0x134); |
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371 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
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372 | } else { |
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373 | tmp = RREG32(RADEON_AGP_BASE); |
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374 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
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375 | tmp = RREG32(RS480_AGP_BASE_2); |
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376 | seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); |
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377 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
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378 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
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379 | } |
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380 | tmp = RREG32_MC(RS480_GART_BASE); |
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381 | seq_printf(m, "GART_BASE 0x%08x\n", tmp); |
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382 | tmp = RREG32_MC(RS480_GART_FEATURE_ID); |
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383 | seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); |
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384 | tmp = RREG32_MC(RS480_AGP_MODE_CNTL); |
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385 | seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); |
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386 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
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387 | seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); |
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388 | tmp = RREG32_MC(0x5F); |
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389 | seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); |
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390 | tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); |
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391 | seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); |
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392 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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393 | seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); |
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394 | tmp = RREG32_MC(0x3B); |
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395 | seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); |
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396 | tmp = RREG32_MC(0x3C); |
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397 | seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); |
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398 | tmp = RREG32_MC(0x30); |
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399 | seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); |
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400 | tmp = RREG32_MC(0x31); |
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401 | seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); |
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402 | tmp = RREG32_MC(0x32); |
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403 | seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); |
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404 | tmp = RREG32_MC(0x33); |
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405 | seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); |
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406 | tmp = RREG32_MC(0x34); |
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407 | seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); |
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408 | tmp = RREG32_MC(0x35); |
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409 | seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); |
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410 | tmp = RREG32_MC(0x36); |
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411 | seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); |
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412 | tmp = RREG32_MC(0x37); |
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413 | seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); |
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414 | return 0; |
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415 | } |
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416 | |||
417 | static struct drm_info_list rs400_gart_info_list[] = { |
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418 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
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419 | }; |
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420 | #endif |
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421 | |||
422 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
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423 | { |
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424 | #if defined(CONFIG_DEBUG_FS) |
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425 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
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426 | #else |
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427 | return 0; |
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428 | #endif |
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429 | }><>>><>><> |