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1246 serge 1
 
2
#include 
3
#include 
4
#include "radeon_drm.h"
5
#include "radeon.h"
6
#include "radeon_object.h"
7
#include "drm_fb_helper.h"
3120 serge 8
#include "hmm.h"
9
#include "bitmap.h"
10
#include "display.h"
1246 serge 11
12
 
1986 serge 13
    struct drm_fb_helper        helper;
14
    struct radeon_framebuffer   rfb;
15
    struct list_head fbdev_list;
16
    struct radeon_device        *rdev;
17
};
18
1246 serge 19
 
1986 serge 20
21
 
22
 
1246 serge 23
static void       __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
24
25
 
26
27
 
1313 serge 28
29
 
1246 serge 30
{
31
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
32
    struct radeon_device *rdev = crtc->dev->dev_private;
33
34
 
2004 serge 35
        WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
36
        WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
37
               EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
38
    } else if (ASIC_IS_AVIVO(rdev)) {
39
        WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
1246 serge 40
        WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
41
                 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
42
    } else {
43
        switch (radeon_crtc->crtc_id) {
44
        case 0:
45
            WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
46
            break;
47
        case 1:
48
            WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
49
            break;
50
        default:
51
            return;
52
        }
53
54
 
55
                      (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
56
             ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
57
    }
58
}
59
60
 
61
{
62
    struct radeon_device *rdev = crtc->dev->dev_private;
63
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
64
    uint32_t cur_lock;
65
66
 
2004 serge 67
        cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
68
        if (lock)
69
            cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
70
        else
71
            cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
72
        WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
73
    } else if (ASIC_IS_AVIVO(rdev)) {
74
        cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
1246 serge 75
        if (lock)
76
            cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
77
        else
78
            cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
79
        WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
80
    } else {
81
        cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
82
        if (lock)
83
            cur_lock |= RADEON_CUR_LOCK;
84
        else
85
            cur_lock &= ~RADEON_CUR_LOCK;
86
        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
87
    }
88
}
89
90
 
91
{
92
    struct radeon_device *rdev;
93
    struct radeon_crtc   *radeon_crtc;
94
    cursor_t *old;
95
    uint32_t  gpu_addr;
96
97
 
98
    radeon_crtc = to_radeon_crtc(rdisplay->crtc);
99
100
 
101
102
 
103
    gpu_addr = radeon_bo_gpu_offset(cursor->robj);
1404 serge 104
1246 serge 105
 
2004 serge 106
        WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
107
               0);
108
        WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
109
               gpu_addr);
110
    } else if (ASIC_IS_AVIVO(rdev)) {
111
        if (rdev->family >= CHIP_RV770)
112
            WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);
113
        WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
1246 serge 114
    }
2004 serge 115
    else {
1246 serge 116
        radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start;
1430 serge 117
        /* offset is from DISP(2)_BASE_ADDRESS */
1246 serge 118
        WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
119
    }
120
121
 
122
};
123
124
 
125
{
126
    struct radeon_device *rdev;
127
    rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
128
    struct drm_crtc *crtc = rdisplay->crtc;
129
    struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
130
131
 
132
    int hot_y = cursor->hot_y;
133
    int w = 32;
2004 serge 134
1246 serge 135
 
136
137
 
2004 serge 138
        WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
139
               (x << 16) | y);
140
        WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset,
141
               (hot_x << 16) | hot_y);
142
        WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
143
               ((w - 1) << 16) | 31);
144
    } else if (ASIC_IS_AVIVO(rdev)) {
145
        WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
1246 serge 146
               (x << 16) | y);
147
        WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,
148
               (hot_x << 16) | hot_y);
149
        WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
150
               ((w - 1) << 16) | 31);
151
    } else {
152
        if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
153
            y *= 2;
154
155
 
1404 serge 156
        int       xorg =0, yorg=0;
157
158
 
159
        y = y - hot_y;
160
161
 
162
        {
163
            xorg = -x + 1;
164
            x = 0;
165
        }
166
167
 
168
        {
169
            yorg = -hot_y + 1;
170
            y = 0;
171
        };
172
173
 
174
               (RADEON_CUR_LOCK | (xorg << 16) | yorg ));
175
        WREG32(RADEON_CUR_HORZ_VERT_POSN,
176
               (RADEON_CUR_LOCK | (x << 16) | y));
1246 serge 177
178
 
1404 serge 179
180
 
1246 serge 181
        WREG32(RADEON_CUR_OFFSET,
1404 serge 182
         (gpu_addr - rdev->mc.vram_start + (yorg * 256)));
1430 serge 183
    }
1246 serge 184
    radeon_lock_cursor_kms(crtc, false);
185
}
186
187
 
188
{
189
    static char name[4];
190
191
 
192
    name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@';
193
    name[2] = (x[1] & 0x1F) + '@';
194
    name[3] = 0;
195
196
 
197
}
198
199
 
200
              videomode_t *reqmode, bool strict)
1403 serge 201
{
1246 serge 202
    struct drm_display_mode  *mode = NULL, *tmpmode;
203
204
 
1986 serge 205
206
 
207
208
 
209
 
1246 serge 210
211
 
212
213
 
214
               reqmode->width, reqmode->height, reqmode->freq);
215
216
 
217
    {
218
        if( (drm_mode_width(tmpmode)    == reqmode->width)  &&
219
            (drm_mode_height(tmpmode)   == reqmode->height) &&
220
            (drm_mode_vrefresh(tmpmode) == reqmode->freq) )
221
        {
222
            mode = tmpmode;
223
            goto do_set;
224
        }
225
    };
226
227
 
228
    {
229
        list_for_each_entry(tmpmode, &connector->modes, head)
230
        {
231
            if( (drm_mode_width(tmpmode)  == reqmode->width)  &&
232
                (drm_mode_height(tmpmode) == reqmode->height) )
233
            {
234
                mode = tmpmode;
235
                goto do_set;
236
            }
237
        };
238
    };
239
240
 
241
242
 
243
    {
244
        struct drm_framebuffer   *fb;
245
        struct drm_encoder       *encoder;
246
        struct drm_crtc          *crtc;
247
248
 
249
        char *con_name;
250
        char *enc_name;
251
252
 
253
        crtc = encoder->crtc;
254
255
 
1963 serge 256
//                              struct drm_framebuffer, filp_head);
257
1246 serge 258
 
259
260
 
261
//        manufacturer_name(con_edid + 0x08),
262
//        (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)),
263
//        (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8)
264
//            + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24)));
265
266
 
267
        enc_name = drm_get_encoder_name(encoder);
268
269
 
270
                   reqmode->width, reqmode->height, con_name, enc_name);
271
272
 
1986 serge 273
274
 
1246 serge 275
        fb->height = reqmode->height;
276
2997 Serge 277
 
278
                         fb->pitches[3] = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8);
279
        fb->bits_per_pixel = 32;
1986 serge 280
        fb->depth = 24;
2997 Serge 281
1246 serge 282
 
283
        crtc->enabled = true;
284
        rdisplay->crtc = crtc;
285
286
 
287
288
 
289
        radeon_show_cursor_kms(crtc);
290
291
 
292
        {
293
            rdisplay->width    = fb->width;
294
            rdisplay->height   = fb->height;
295
            rdisplay->pitch    = fb->pitches[0];
2997 Serge 296
            rdisplay->vrefresh = drm_mode_vrefresh(mode);
1246 serge 297
298
 
2997 Serge 299
1246 serge 300
 
301
                       fb->width, fb->height, fb->pitches[0]);
2997 Serge 302
        }
1246 serge 303
        else
304
            DRM_ERROR("failed to set mode %d_%d on crtc %p\n",
305
                       fb->width, fb->height, crtc);
306
    }
307
308
 
309
    return ret;
310
};
311
312
 
313
{
314
    struct drm_display_mode  *mode;
315
    int count = 0;
316
317
 
318
    {
319
        count++;
320
    };
321
    return count;
322
};
323
324
 
325
{
326
    struct drm_connector  *connector;
327
    struct drm_connector_helper_funcs *connector_funcs;
1963 serge 328
329
 
1246 serge 330
331
 
332
    {
333
        struct drm_encoder  *encoder;
334
        struct drm_crtc     *crtc;
335
336
 
337
            continue;
338
339
 
1963 serge 340
        encoder = connector_funcs->best_encoder(connector);
341
        if( encoder == NULL)
1246 serge 342
            continue;
343
344
 
1963 serge 345
346
 
1246 serge 347
1963 serge 348
 
1986 serge 349
                   connector, connector->base.id,
350
                   connector->status, connector->encoder,
351
                   crtc);
352
1246 serge 353
 
1986 serge 354
//            continue;
355
356
 
1246 serge 357
1986 serge 358
 
1246 serge 359
    };
360
361
 
362
};
363
364
 
1986 serge 365
 
366
 
1403 serge 367
{
1246 serge 368
    struct drm_device   *dev;
369
370
 
2997 Serge 371
    struct drm_connector_helper_funcs *connector_funcs;
372
    struct drm_encoder      *encoder;
373
    struct drm_crtc         *crtc = NULL;
374
    struct drm_framebuffer  *fb;
375
    struct drm_display_mode *native;
376
377
 
378
 
1246 serge 379
    bool                 retval = false;
380
    u32_t                ifl;
381
382
 
1986 serge 383
    struct drm_fb_helper *fb_helper;
384
385
 
386
387
 
1246 serge 388
389
 
2997 Serge 390
1246 serge 391
 
2997 Serge 392
    {
393
        if( connector->status != connector_status_connected)
394
            continue;
395
1246 serge 396
 
2997 Serge 397
        encoder = connector_funcs->best_encoder(connector);
398
        if( encoder == NULL)
399
        {
400
            dbgprintf("CONNECTOR %x ID: %d no active encoders\n",
401
                      connector, connector->base.id);
402
            continue;
403
        }
404
        connector->encoder = encoder;
405
406
 
407
               connector, connector->base.id,
408
               connector->status, connector->encoder,
409
               encoder->crtc);
410
411
 
412
        break;
413
    };
414
415
 
416
    {
1246 serge 417
        dbgprintf("No active connectors!\n");
2997 Serge 418
        return -1;
419
    };
420
421
 
422
        struct drm_display_mode *tmp;
423
424
 
425
            if (drm_mode_width(tmp) > 16384 ||
426
                drm_mode_height(tmp) > 16384)
427
                continue;
428
            if (tmp->type & DRM_MODE_TYPE_PREFERRED)
429
            {
430
                native = tmp;
431
                break;
432
            };
433
        }
434
    }
435
436
 
437
    {
438
        dbgprintf("native w %d h %d\n", native->hdisplay, native->vdisplay);
439
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(connector->encoder);
440
        radeon_encoder->rmx_type = RMX_FULL;
441
        radeon_encoder->native_mode = *native;
442
    };
443
444
 
445
 
446
    {
447
        struct drm_crtc *tmp_crtc;
448
        int crtc_mask = 1;
449
450
 
451
        {
1246 serge 452
            if (encoder->possible_crtcs & crtc_mask)
2997 Serge 453
            {
454
                crtc = tmp_crtc;
455
                encoder->crtc = crtc;
456
                break;
457
            };
458
            crtc_mask <<= 1;
459
        };
1246 serge 460
    };
461
462
 
2997 Serge 463
    {
464
        dbgprintf("No CRTC for encoder %d\n", encoder->base.id);
465
        return -1;
466
    };
467
1986 serge 468
 
469
 
2997 Serge 470
1986 serge 471
 
472
 
2997 Serge 473
1986 serge 474
 
2997 Serge 475
    rdisplay->ddev = dev;
476
    rdisplay->connector = connector;
477
    rdisplay->crtc = crtc;
478
1986 serge 479
 
2997 Serge 480
1986 serge 481
 
482
 
483
 
2997 Serge 484
    {
485
        list_for_each_entry(cursor, &rdisplay->cursors, list)
486
        {
487
            init_cursor(cursor);
488
        };
489
1986 serge 490
 
1246 serge 491
    safe_sti(ifl);
2997 Serge 492
1246 serge 493
 
1986 serge 494
 
1268 serge 495
              rdisplay->width, rdisplay->height, rdisplay->vrefresh);
496
    dbgprintf("user mode mode %d x %d x %d\n",
497
              usermode->width, usermode->height, usermode->freq);
498
499
 
2997 Serge 500
 
1246 serge 501
        (usermode->height != 0) &&
502
        ( (usermode->width  != rdisplay->width)  ||
503
          (usermode->height != rdisplay->height) ||
504
          (usermode->freq   != rdisplay->vrefresh) ) )
505
    {
506
507
 
508
    }
509
    else
2997 Serge 510
    {
511
        usermode->width  = rdisplay->width;
512
        usermode->height = rdisplay->height;
513
        usermode->freq   = 60;
514
        retval = set_mode(dev, rdisplay->connector, usermode, false);
515
    };
516
1246 serge 517
 
518
    {
519
        rdisplay->restore_cursor(0,0);
520
        rdisplay->init_cursor    = init_cursor;
521
        rdisplay->select_cursor  = select_cursor_kms;
522
        rdisplay->show_cursor    = NULL;
523
        rdisplay->move_cursor    = move_cursor_kms;
524
        rdisplay->restore_cursor = restore_cursor;
525
        rdisplay->disable_mouse  = disable_mouse;
1313 serge 526
1268 serge 527
 
528
        radeon_show_cursor_kms(rdisplay->crtc);
1246 serge 529
    };
530
    safe_sti(ifl);
531
532
 
3764 Serge 533
3120 serge 534
 
1246 serge 535
536
 
537
};
538
539
 
1403 serge 540
{
1246 serge 541
    int err = -1;
542
543
 
2997 Serge 544
1246 serge 545
 
546
547
 
548
    {
549
        *count = rdisplay->supported_modes;
550
        err = 0;
551
    }
552
    else if( mode != NULL )
553
    {
554
        struct drm_display_mode  *drmmode;
555
        int i = 0;
556
557
 
558
            *count = rdisplay->supported_modes;
559
560
 
561
        {
562
            if( i < *count)
563
            {
564
                mode->width  = drm_mode_width(drmmode);
565
                mode->height = drm_mode_height(drmmode);
566
                mode->bpp    = 32;
567
                mode->freq   = drm_mode_vrefresh(drmmode);
568
                i++;
569
                mode++;
570
            }
571
            else break;
572
        };
573
        *count = i;
574
        err = 0;
575
    };
576
//    LEAVE();
2997 Serge 577
    return err;
1246 serge 578
}
579
580
 
1403 serge 581
{
1246 serge 582
    int err = -1;
583
584
 
2997 Serge 585
1246 serge 586
 
587
               mode->width, mode->height, mode->freq);
588
589
 
590
        (mode->height != 0)  &&
591
        (mode->freq   != 0 ) &&
592
        ( (mode->width   != rdisplay->width)  ||
593
          (mode->height  != rdisplay->height) ||
594
          (mode->freq    != rdisplay->vrefresh) ) )
595
    {
596
        if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) )
597
            err = 0;
598
    };
599
600
 
2997 Serge 601
    return err;
1246 serge 602
};
603
604
 
1986 serge 605
 
2997 Serge 606
                     struct drm_mode_fb_cmd2 *mode_cmd,
607
                     struct drm_gem_object **gobj_p)
1986 serge 608
{
1404 serge 609
    struct radeon_device *rdev = rfbdev->rdev;
1986 serge 610
    struct drm_gem_object *gobj = NULL;
611
    struct radeon_bo *rbo = NULL;
612
    bool fb_tiled = false; /* useful for testing */
613
    u32 tiling_flags = 0;
614
    int ret;
615
    int aligned_size, size;
616
    int height = mode_cmd->height;
617
    u32 bpp, depth;
2997 Serge 618
1404 serge 619
 
1986 serge 620
    static struct drm_mm_node  vm_node;
621
622
 
2997 Serge 623
 
624
625
 
1986 serge 626
    mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
2997 Serge 627
                          fb_tiled) * ((bpp + 1) / 8);
628
1986 serge 629
 
630
        height = ALIGN(mode_cmd->height, 8);
631
    size = mode_cmd->pitches[0] * height;
2997 Serge 632
    aligned_size = ALIGN(size, PAGE_SIZE);
1986 serge 633
634
 
3764 Serge 635
    ret = drm_gem_object_init(rdev->ddev, &kos_bo.gem_base, aligned_size);
1986 serge 636
    if (unlikely(ret)) {
637
        printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
2997 Serge 638
               aligned_size);
639
        return -ENOMEM;
640
    }
1404 serge 641
#endif
3764 Serge 642
1404 serge 643
 
1986 serge 644
    kos_bo.gem_base.driver_private = NULL;
645
    kos_bo.surface_reg = -1;
646
//    kos_bo.domain = RADEON_GEM_DOMAIN_VRAM;
3764 Serge 647
1986 serge 648
 
649
650
 
651
    rbo = gem_to_radeon_bo(gobj);
652
653
 
654
        tiling_flags = RADEON_TILING_MACRO;
655
656
 
2997 Serge 657
//        ret = radeon_bo_set_tiling_flags(rbo,
658
//                         tiling_flags | RADEON_TILING_SURFACE,
659
//                         mode_cmd->pitches[0]);
660
//        if (ret)
661
//            dev_err(rdev->dev, "FB failed to set tiling flags\n");
662
//    }
663
1404 serge 664
 
1986 serge 665
    vm_node.start = 0;
666
    vm_node.mm = NULL;
667
668
 
669
    rbo->tbo.offset  = rbo->tbo.vm_node->start << PAGE_SHIFT;
670
    rbo->tbo.offset += (u64)rbo->rdev->mc.vram_start;
671
    rbo->kptr        = (void*)0xFE000000;
672
    rbo->pin_count   = 1;
673
674
 
675
 
676
    return 0;
677
}
1404 serge 678
1986 serge 679
 
3764 Serge 680
typedef struct
3120 serge 681
{
682
    int left;
683
    int top;
684
    int right;
685
    int bottom;
686
}rect_t;
687
688
 
689
struct drm_device *main_drm_device;
690
691
 
692
693
 
694
695
 
696
{
697
    u32_t   addr;
698
699
 
700
    addr+= sizeof(display_t);            /*  shoot me  */
701
    return *(u32_t*)addr;
702
}
703
704
 
705
#include "r100d.h"
706
707
 
3764 Serge 708
# define PACKET3_TRANS_BITBLT           0x9C
3124 serge 709
# define R5XX_SRC_CMP_EQ_COLOR      (4 <<  0)
710
# define R5XX_SRC_CMP_NEQ_COLOR     (5 <<  0)
711
# define R5XX_CLR_CMP_SRC_SOURCE    (1 << 24)
712
3120 serge 713
 
714
               int src_x, int src_y, u32 w, u32 h)
715
{
716
    struct context *context;
717
718
 
719
    rect_t     winrc;
720
    clip_t     dst_clip;
721
    clip_t     src_clip;
722
    u32_t      width;
723
    u32_t      height;
724
725
 
726
    u32_t      offset;
727
    u8         slot;
728
    int        n=0;
729
    int        ret;
730
731
 
732
        return -1;
733
734
 
735
736
 
737
        return -1;
738
739
 
740
    if(unlikely(context == NULL))
741
        return -1;
742
743
 
744
    {
745
        static warn_count;
746
747
 
748
        {
749
            printf("left %d top %d right %d bottom %d\n",
750
                    winrc.left, winrc.top, winrc.right, winrc.bottom);
751
            printf("bitmap width %d height %d\n", w, h);
752
            warn_count++;
753
        };
754
    };
755
756
 
757
 
758
    dst_clip.ymin   = 0;
759
    dst_clip.xmax   = winrc.right-winrc.left;
760
    dst_clip.ymax   = winrc.bottom -winrc.top;
761
762
 
763
    src_clip.ymin   = 0;
764
    src_clip.xmax   = bitmap->width  - 1;
765
    src_clip.ymax   = bitmap->height - 1;
766
767
 
768
    height = h;
769
770
 
771
                  &src_clip, &src_x, &src_y,
772
                  &width, &height) )
773
        return 0;
774
775
 
776
    dst_y+= winrc.top;
777
778
 
779
780
 
781
782
 
783
#if 0
3124 serge 784
#else
3120 serge 785
        u8* src_offset;
786
        u8* dst_offset;
787
        u32 color;
3124 serge 788
789
 
3120 serge 790
791
 
792
        src_offset += (u32)bitmap->uaddr;
793
794
 
795
        dst_offset+= get_display_map();
796
797
 
798
799
 
800
        while( tmp_h--)
801
        {
802
            u32 tmp_w = width;
3124 serge 803
3120 serge 804
 
3124 serge 805
            u8*  tmp_dst = dst_offset;
3764 Serge 806
3120 serge 807
 
808
            dst_offset+= rdisplay->width;
809
810
 
811
            {
812
                color = *tmp_src;
3124 serge 813
814
 
815
                    color |= 0xFF000000;
816
                else
817
                    color = 0x00;
818
819
 
820
                tmp_src++;
821
                tmp_dst++;
3120 serge 822
            };
823
        };
824
      safe_sti(ifl);
825
#endif
826
    }
827
828
 
829
        static warn_count;
830
831
 
832
        {
833
            printf("blit width %d height %d\n",
834
                    width, height);
835
            warn_count++;
836
        };
837
    };
838
839
 
840
 
841
//        context->cmd_buffer&= 0xFFFFF000;
842
843
 
844
845
 
846
847
 
848
 
849
850
 
851
    struct radeon_ib *ib = &context->ib;
852
853
 
3124 serge 854
    ib->ptr[1] = 0xFFFFFFFF;
855
    ib->ptr[2] = PACKET3(PACKET3_TRANS_BITBLT, 11);
856
    ib->ptr[3] =  RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
857
                  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
3120 serge 858
                  RADEON_GMC_SRC_CLIPPING |
859
                  RADEON_GMC_DST_CLIPPING |
860
                  RADEON_GMC_BRUSH_NONE |
861
                  (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
862
                  RADEON_GMC_SRC_DATATYPE_COLOR |
863
                  RADEON_ROP3_S |
864
                  RADEON_DP_SRC_SOURCE_MEMORY |
865
                  RADEON_GMC_WR_MSK_DIS;
866
867
 
3124 serge 868
    ib->ptr[5] = ((rdisplay->pitch/64) << 22) | (rdev->mc.vram_start >> 10);
869
    ib->ptr[6] = (0x1fff) | (0x1fff << 16);
3120 serge 870
    ib->ptr[7] = 0;
3124 serge 871
    ib->ptr[8] = (0x1fff) | (0x1fff << 16);
872
3120 serge 873
 
3124 serge 874
    ib->ptr[10] = 0x00000000;
875
    ib->ptr[11] = 0xFFFFFFFF;
876
3120 serge 877
 
3124 serge 878
    ib->ptr[13] = (dst_x << 16) | dst_y;
879
    ib->ptr[14] = (width << 16) | height;
880
881
 
3120 serge 882
883
 
884
885
 
886
    if (ret) {
887
        DRM_ERROR("radeon: failed to schedule ib (%d).\n", ret);
888
        goto fail;
889
    }
890
891
 
892
    if (ret) {
893
        DRM_ERROR("radeon: fence wait failed (%d).\n", ret);
894
        goto fail;
895
    }
896
897
 
3192 Serge 898
899
 
3120 serge 900
    return ret;
901
};
902
903
 
3764 Serge 904