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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include "radeon_drm.h" |
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5 | #include "radeon.h" |
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6 | #include "radeon_object.h" |
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7 | #include "drm_fb_helper.h" |
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3120 | serge | 8 | #include "hmm.h" |
9 | #include "bitmap.h" |
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10 | #include "display.h" |
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1246 | serge | 11 | |
12 | |||
1986 | serge | 13 | struct drm_fb_helper helper; |
14 | struct radeon_framebuffer rfb; |
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15 | struct list_head fbdev_list; |
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16 | struct radeon_device *rdev; |
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17 | }; |
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18 | |||
1246 | serge | 19 | |
1986 | serge | 20 | |
21 | |||
22 | |||
1246 | serge | 23 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
24 | |||
25 | |||
26 | |||
27 | |||
1313 | serge | 28 | |
29 | |||
1246 | serge | 30 | { |
31 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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32 | struct radeon_device *rdev = crtc->dev->dev_private; |
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33 | |||
34 | |||
2004 | serge | 35 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
36 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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37 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); |
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38 | } else if (ASIC_IS_AVIVO(rdev)) { |
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39 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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1246 | serge | 40 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
41 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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42 | } else { |
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43 | switch (radeon_crtc->crtc_id) { |
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44 | case 0: |
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45 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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46 | break; |
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47 | case 1: |
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48 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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49 | break; |
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50 | default: |
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51 | return; |
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52 | } |
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53 | |||
54 | |||
55 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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56 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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57 | } |
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58 | } |
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59 | |||
60 | |||
61 | { |
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62 | struct radeon_device *rdev = crtc->dev->dev_private; |
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63 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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64 | uint32_t cur_lock; |
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65 | |||
66 | |||
2004 | serge | 67 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); |
68 | if (lock) |
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69 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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70 | else |
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71 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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72 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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73 | } else if (ASIC_IS_AVIVO(rdev)) { |
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74 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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1246 | serge | 75 | if (lock) |
76 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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77 | else |
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78 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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79 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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80 | } else { |
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81 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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82 | if (lock) |
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83 | cur_lock |= RADEON_CUR_LOCK; |
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84 | else |
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85 | cur_lock &= ~RADEON_CUR_LOCK; |
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86 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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87 | } |
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88 | } |
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89 | |||
90 | |||
91 | { |
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92 | struct radeon_device *rdev; |
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93 | struct radeon_crtc *radeon_crtc; |
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94 | cursor_t *old; |
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95 | uint32_t gpu_addr; |
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96 | |||
97 | |||
98 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
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99 | |||
100 | |||
101 | |||
102 | |||
103 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
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1404 | serge | 104 | |
1246 | serge | 105 | |
2004 | serge | 106 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
107 | 0); |
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108 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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109 | gpu_addr); |
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110 | } else if (ASIC_IS_AVIVO(rdev)) { |
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111 | if (rdev->family >= CHIP_RV770) |
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112 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); |
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113 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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1246 | serge | 114 | } |
2004 | serge | 115 | else { |
1246 | serge | 116 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start; |
1430 | serge | 117 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 118 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
119 | } |
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120 | |||
121 | |||
122 | }; |
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123 | |||
124 | |||
125 | { |
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126 | struct radeon_device *rdev; |
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127 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
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128 | struct drm_crtc *crtc = rdisplay->crtc; |
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129 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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130 | |||
131 | |||
132 | int hot_y = cursor->hot_y; |
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133 | int w = 32; |
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2004 | serge | 134 | |
1246 | serge | 135 | |
136 | |||
137 | |||
2004 | serge | 138 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, |
139 | (x << 16) | y); |
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140 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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141 | (hot_x << 16) | hot_y); |
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142 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, |
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143 | ((w - 1) << 16) | 31); |
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144 | } else if (ASIC_IS_AVIVO(rdev)) { |
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145 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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1246 | serge | 146 | (x << 16) | y); |
147 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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148 | (hot_x << 16) | hot_y); |
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149 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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150 | ((w - 1) << 16) | 31); |
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151 | } else { |
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152 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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153 | y *= 2; |
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154 | |||
155 | |||
1404 | serge | 156 | int xorg =0, yorg=0; |
157 | |||
158 | |||
159 | y = y - hot_y; |
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160 | |||
161 | |||
162 | { |
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163 | xorg = -x + 1; |
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164 | x = 0; |
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165 | } |
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166 | |||
167 | |||
168 | { |
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169 | yorg = -hot_y + 1; |
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170 | y = 0; |
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171 | }; |
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172 | |||
173 | |||
174 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
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175 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
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176 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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1246 | serge | 177 | |
178 | |||
1404 | serge | 179 | |
180 | |||
1246 | serge | 181 | WREG32(RADEON_CUR_OFFSET, |
1404 | serge | 182 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 183 | } |
1246 | serge | 184 | radeon_lock_cursor_kms(crtc, false); |
185 | } |
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186 | |||
187 | |||
188 | { |
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189 | static char name[4]; |
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190 | |||
191 | |||
192 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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193 | name[2] = (x[1] & 0x1F) + '@'; |
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194 | name[3] = 0; |
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195 | |||
196 | |||
197 | } |
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198 | |||
199 | |||
200 | videomode_t *reqmode, bool strict) |
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1403 | serge | 201 | { |
1246 | serge | 202 | struct drm_display_mode *mode = NULL, *tmpmode; |
203 | |||
204 | |||
1986 | serge | 205 | |
206 | |||
207 | |||
208 | |||
209 | |||
1246 | serge | 210 | |
211 | |||
212 | |||
213 | |||
214 | reqmode->width, reqmode->height, reqmode->freq); |
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215 | |||
216 | |||
217 | { |
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218 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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219 | (drm_mode_height(tmpmode) == reqmode->height) && |
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220 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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221 | { |
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222 | mode = tmpmode; |
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223 | goto do_set; |
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224 | } |
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225 | }; |
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226 | |||
227 | |||
228 | { |
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229 | list_for_each_entry(tmpmode, &connector->modes, head) |
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230 | { |
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231 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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232 | (drm_mode_height(tmpmode) == reqmode->height) ) |
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233 | { |
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234 | mode = tmpmode; |
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235 | goto do_set; |
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236 | } |
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237 | }; |
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238 | }; |
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239 | |||
240 | |||
241 | |||
242 | |||
243 | { |
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244 | struct drm_framebuffer *fb; |
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245 | struct drm_encoder *encoder; |
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246 | struct drm_crtc *crtc; |
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247 | |||
248 | |||
249 | char *con_name; |
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250 | char *enc_name; |
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251 | |||
252 | |||
253 | crtc = encoder->crtc; |
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254 | |||
255 | |||
1963 | serge | 256 | // struct drm_framebuffer, filp_head); |
257 | |||
1246 | serge | 258 | |
259 | |||
260 | |||
261 | // manufacturer_name(con_edid + 0x08), |
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262 | // (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
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263 | // (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
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264 | // + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
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265 | |||
266 | |||
267 | enc_name = drm_get_encoder_name(encoder); |
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268 | |||
269 | |||
270 | reqmode->width, reqmode->height, con_name, enc_name); |
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271 | |||
272 | |||
1986 | serge | 273 | |
274 | |||
1246 | serge | 275 | fb->height = reqmode->height; |
276 | |||
2997 | Serge | 277 | |
278 | fb->pitches[3] = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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279 | fb->bits_per_pixel = 32; |
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1986 | serge | 280 | fb->depth = 24; |
2997 | Serge | 281 | |
1246 | serge | 282 | |
283 | crtc->enabled = true; |
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284 | rdisplay->crtc = crtc; |
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285 | |||
286 | |||
287 | |||
288 | |||
289 | radeon_show_cursor_kms(crtc); |
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290 | |||
291 | |||
292 | { |
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293 | rdisplay->width = fb->width; |
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294 | rdisplay->height = fb->height; |
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295 | rdisplay->pitch = fb->pitches[0]; |
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2997 | Serge | 296 | rdisplay->vrefresh = drm_mode_vrefresh(mode); |
1246 | serge | 297 | |
298 | |||
2997 | Serge | 299 | |
1246 | serge | 300 | |
301 | fb->width, fb->height, fb->pitches[0]); |
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2997 | Serge | 302 | } |
1246 | serge | 303 | else |
304 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
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305 | fb->width, fb->height, crtc); |
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306 | } |
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307 | |||
308 | |||
309 | return ret; |
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310 | }; |
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311 | |||
312 | |||
313 | { |
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314 | struct drm_display_mode *mode; |
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315 | int count = 0; |
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316 | |||
317 | |||
318 | { |
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319 | count++; |
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320 | }; |
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321 | return count; |
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322 | }; |
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323 | |||
324 | |||
325 | { |
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326 | struct drm_connector *connector; |
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327 | struct drm_connector_helper_funcs *connector_funcs; |
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1963 | serge | 328 | |
329 | |||
1246 | serge | 330 | |
331 | |||
332 | { |
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333 | struct drm_encoder *encoder; |
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334 | struct drm_crtc *crtc; |
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335 | |||
336 | |||
337 | continue; |
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338 | |||
339 | |||
1963 | serge | 340 | encoder = connector_funcs->best_encoder(connector); |
341 | if( encoder == NULL) |
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1246 | serge | 342 | continue; |
343 | |||
344 | |||
1963 | serge | 345 | |
346 | |||
1246 | serge | 347 | |
1963 | serge | 348 | |
1986 | serge | 349 | connector, connector->base.id, |
350 | connector->status, connector->encoder, |
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351 | crtc); |
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352 | |||
1246 | serge | 353 | |
1986 | serge | 354 | // continue; |
355 | |||
356 | |||
1246 | serge | 357 | |
1986 | serge | 358 | |
1246 | serge | 359 | }; |
360 | |||
361 | |||
362 | }; |
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363 | |||
364 | |||
1986 | serge | 365 | |
366 | |||
1403 | serge | 367 | { |
1246 | serge | 368 | struct drm_device *dev; |
369 | |||
370 | |||
2997 | Serge | 371 | struct drm_connector_helper_funcs *connector_funcs; |
372 | struct drm_encoder *encoder; |
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373 | struct drm_crtc *crtc = NULL; |
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374 | struct drm_framebuffer *fb; |
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375 | struct drm_display_mode *native; |
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376 | |||
377 | |||
378 | |||
1246 | serge | 379 | bool retval = false; |
380 | u32_t ifl; |
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381 | |||
382 | |||
1986 | serge | 383 | struct drm_fb_helper *fb_helper; |
384 | |||
385 | |||
386 | |||
387 | |||
1246 | serge | 388 | |
389 | |||
2997 | Serge | 390 | |
1246 | serge | 391 | |
2997 | Serge | 392 | { |
393 | if( connector->status != connector_status_connected) |
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394 | continue; |
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395 | |||
1246 | serge | 396 | |
2997 | Serge | 397 | encoder = connector_funcs->best_encoder(connector); |
398 | if( encoder == NULL) |
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399 | { |
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400 | dbgprintf("CONNECTOR %x ID: %d no active encoders\n", |
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401 | connector, connector->base.id); |
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402 | continue; |
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403 | } |
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404 | connector->encoder = encoder; |
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405 | |||
406 | |||
407 | connector, connector->base.id, |
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408 | connector->status, connector->encoder, |
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409 | encoder->crtc); |
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410 | |||
411 | |||
412 | break; |
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413 | }; |
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414 | |||
415 | |||
416 | { |
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1246 | serge | 417 | dbgprintf("No active connectors!\n"); |
2997 | Serge | 418 | return -1; |
419 | }; |
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420 | |||
421 | |||
422 | struct drm_display_mode *tmp; |
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423 | |||
424 | |||
425 | if (drm_mode_width(tmp) > 16384 || |
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426 | drm_mode_height(tmp) > 16384) |
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427 | continue; |
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428 | if (tmp->type & DRM_MODE_TYPE_PREFERRED) |
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429 | { |
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430 | native = tmp; |
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431 | break; |
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432 | }; |
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433 | } |
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434 | } |
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435 | |||
436 | |||
437 | { |
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438 | dbgprintf("native w %d h %d\n", native->hdisplay, native->vdisplay); |
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439 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(connector->encoder); |
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440 | radeon_encoder->rmx_type = RMX_FULL; |
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441 | radeon_encoder->native_mode = *native; |
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442 | }; |
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443 | |||
444 | |||
445 | |||
446 | { |
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447 | struct drm_crtc *tmp_crtc; |
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448 | int crtc_mask = 1; |
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449 | |||
450 | |||
451 | { |
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1246 | serge | 452 | if (encoder->possible_crtcs & crtc_mask) |
2997 | Serge | 453 | { |
454 | crtc = tmp_crtc; |
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455 | encoder->crtc = crtc; |
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456 | break; |
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457 | }; |
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458 | crtc_mask <<= 1; |
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459 | }; |
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1246 | serge | 460 | }; |
461 | |||
462 | |||
2997 | Serge | 463 | { |
464 | dbgprintf("No CRTC for encoder %d\n", encoder->base.id); |
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465 | return -1; |
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466 | }; |
||
467 | |||
1986 | serge | 468 | |
469 | |||
2997 | Serge | 470 | |
1986 | serge | 471 | |
472 | |||
2997 | Serge | 473 | |
1986 | serge | 474 | |
2997 | Serge | 475 | rdisplay->ddev = dev; |
476 | rdisplay->connector = connector; |
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477 | rdisplay->crtc = crtc; |
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478 | |||
1986 | serge | 479 | |
2997 | Serge | 480 | |
1986 | serge | 481 | |
482 | |||
483 | |||
2997 | Serge | 484 | { |
485 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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486 | { |
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487 | init_cursor(cursor); |
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488 | }; |
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489 | |||
1986 | serge | 490 | |
1246 | serge | 491 | safe_sti(ifl); |
2997 | Serge | 492 | |
1246 | serge | 493 | |
1986 | serge | 494 | |
1268 | serge | 495 | rdisplay->width, rdisplay->height, rdisplay->vrefresh); |
496 | dbgprintf("user mode mode %d x %d x %d\n", |
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497 | usermode->width, usermode->height, usermode->freq); |
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498 | |||
499 | |||
2997 | Serge | 500 | |
1246 | serge | 501 | (usermode->height != 0) && |
502 | ( (usermode->width != rdisplay->width) || |
||
503 | (usermode->height != rdisplay->height) || |
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504 | (usermode->freq != rdisplay->vrefresh) ) ) |
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505 | { |
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506 | |||
507 | |||
508 | } |
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509 | else |
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2997 | Serge | 510 | { |
511 | usermode->width = rdisplay->width; |
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512 | usermode->height = rdisplay->height; |
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513 | usermode->freq = 60; |
||
514 | retval = set_mode(dev, rdisplay->connector, usermode, false); |
||
515 | }; |
||
516 | |||
1246 | serge | 517 | |
518 | { |
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519 | rdisplay->restore_cursor(0,0); |
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520 | rdisplay->init_cursor = init_cursor; |
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521 | rdisplay->select_cursor = select_cursor_kms; |
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522 | rdisplay->show_cursor = NULL; |
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523 | rdisplay->move_cursor = move_cursor_kms; |
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524 | rdisplay->restore_cursor = restore_cursor; |
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525 | rdisplay->disable_mouse = disable_mouse; |
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1313 | serge | 526 | |
1268 | serge | 527 | |
528 | radeon_show_cursor_kms(rdisplay->crtc); |
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1246 | serge | 529 | }; |
530 | safe_sti(ifl); |
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531 | |||
532 | |||
3764 | Serge | 533 | |
3120 | serge | 534 | |
1246 | serge | 535 | |
536 | |||
537 | }; |
||
538 | |||
539 | |||
1403 | serge | 540 | { |
1246 | serge | 541 | int err = -1; |
542 | |||
543 | |||
2997 | Serge | 544 | |
1246 | serge | 545 | |
546 | |||
547 | |||
548 | { |
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549 | *count = rdisplay->supported_modes; |
||
550 | err = 0; |
||
551 | } |
||
552 | else if( mode != NULL ) |
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553 | { |
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554 | struct drm_display_mode *drmmode; |
||
555 | int i = 0; |
||
556 | |||
557 | |||
558 | *count = rdisplay->supported_modes; |
||
559 | |||
560 | |||
561 | { |
||
562 | if( i < *count) |
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563 | { |
||
564 | mode->width = drm_mode_width(drmmode); |
||
565 | mode->height = drm_mode_height(drmmode); |
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566 | mode->bpp = 32; |
||
567 | mode->freq = drm_mode_vrefresh(drmmode); |
||
568 | i++; |
||
569 | mode++; |
||
570 | } |
||
571 | else break; |
||
572 | }; |
||
573 | *count = i; |
||
574 | err = 0; |
||
575 | }; |
||
576 | // LEAVE(); |
||
2997 | Serge | 577 | return err; |
1246 | serge | 578 | } |
579 | |||
580 | |||
1403 | serge | 581 | { |
1246 | serge | 582 | int err = -1; |
583 | |||
584 | |||
2997 | Serge | 585 | |
1246 | serge | 586 | |
587 | mode->width, mode->height, mode->freq); |
||
588 | |||
589 | |||
590 | (mode->height != 0) && |
||
591 | (mode->freq != 0 ) && |
||
592 | ( (mode->width != rdisplay->width) || |
||
593 | (mode->height != rdisplay->height) || |
||
594 | (mode->freq != rdisplay->vrefresh) ) ) |
||
595 | { |
||
596 | if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) ) |
||
597 | err = 0; |
||
598 | }; |
||
599 | |||
600 | |||
2997 | Serge | 601 | return err; |
1246 | serge | 602 | }; |
603 | |||
604 | |||
1986 | serge | 605 | |
2997 | Serge | 606 | struct drm_mode_fb_cmd2 *mode_cmd, |
607 | struct drm_gem_object **gobj_p) |
||
1986 | serge | 608 | { |
1404 | serge | 609 | struct radeon_device *rdev = rfbdev->rdev; |
1986 | serge | 610 | struct drm_gem_object *gobj = NULL; |
611 | struct radeon_bo *rbo = NULL; |
||
612 | bool fb_tiled = false; /* useful for testing */ |
||
613 | u32 tiling_flags = 0; |
||
614 | int ret; |
||
615 | int aligned_size, size; |
||
616 | int height = mode_cmd->height; |
||
617 | u32 bpp, depth; |
||
2997 | Serge | 618 | |
1404 | serge | 619 | |
1986 | serge | 620 | static struct drm_mm_node vm_node; |
621 | |||
622 | |||
2997 | Serge | 623 | |
624 | |||
625 | |||
1986 | serge | 626 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, |
2997 | Serge | 627 | fb_tiled) * ((bpp + 1) / 8); |
628 | |||
1986 | serge | 629 | |
630 | height = ALIGN(mode_cmd->height, 8); |
||
631 | size = mode_cmd->pitches[0] * height; |
||
2997 | Serge | 632 | aligned_size = ALIGN(size, PAGE_SIZE); |
1986 | serge | 633 | |
634 | |||
3764 | Serge | 635 | ret = drm_gem_object_init(rdev->ddev, &kos_bo.gem_base, aligned_size); |
1986 | serge | 636 | if (unlikely(ret)) { |
637 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
||
2997 | Serge | 638 | aligned_size); |
639 | return -ENOMEM; |
||
640 | } |
||
1404 | serge | 641 | #endif |
3764 | Serge | 642 | |
1404 | serge | 643 | |
1986 | serge | 644 | kos_bo.gem_base.driver_private = NULL; |
645 | kos_bo.surface_reg = -1; |
||
646 | // kos_bo.domain = RADEON_GEM_DOMAIN_VRAM; |
||
3764 | Serge | 647 | |
1986 | serge | 648 | |
649 | |||
650 | |||
651 | rbo = gem_to_radeon_bo(gobj); |
||
652 | |||
653 | |||
654 | tiling_flags = RADEON_TILING_MACRO; |
||
655 | |||
656 | |||
2997 | Serge | 657 | // ret = radeon_bo_set_tiling_flags(rbo, |
658 | // tiling_flags | RADEON_TILING_SURFACE, |
||
659 | // mode_cmd->pitches[0]); |
||
660 | // if (ret) |
||
661 | // dev_err(rdev->dev, "FB failed to set tiling flags\n"); |
||
662 | // } |
||
663 | |||
1404 | serge | 664 | |
1986 | serge | 665 | vm_node.start = 0; |
666 | vm_node.mm = NULL; |
||
667 | |||
668 | |||
669 | rbo->tbo.offset = rbo->tbo.vm_node->start << PAGE_SHIFT; |
||
670 | rbo->tbo.offset += (u64)rbo->rdev->mc.vram_start; |
||
671 | rbo->kptr = (void*)0xFE000000; |
||
672 | rbo->pin_count = 1; |
||
673 | |||
674 | |||
675 | |||
676 | return 0; |
||
677 | } |
||
1404 | serge | 678 | |
1986 | serge | 679 | |
3764 | Serge | 680 | typedef struct |
3120 | serge | 681 | { |
682 | int left; |
||
683 | int top; |
||
684 | int right; |
||
685 | int bottom; |
||
686 | }rect_t; |
||
687 | |||
688 | |||
689 | struct drm_device *main_drm_device; |
||
690 | |||
691 | |||
692 | |||
693 | |||
694 | |||
695 | |||
696 | { |
||
697 | u32_t addr; |
||
698 | |||
699 | |||
700 | addr+= sizeof(display_t); /* shoot me */ |
||
701 | return *(u32_t*)addr; |
||
702 | } |
||
703 | |||
704 | |||
705 | #include "r100d.h" |
||
706 | |||
707 | |||
3764 | Serge | 708 | # define PACKET3_TRANS_BITBLT 0x9C |
3124 | serge | 709 | # define R5XX_SRC_CMP_EQ_COLOR (4 << 0) |
710 | # define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) |
||
711 | # define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) |
||
712 | |||
3120 | serge | 713 | |
714 | int src_x, int src_y, u32 w, u32 h) |
||
715 | { |
||
716 | struct context *context; |
||
717 | |||
718 | |||
719 | rect_t winrc; |
||
720 | clip_t dst_clip; |
||
721 | clip_t src_clip; |
||
722 | u32_t width; |
||
723 | u32_t height; |
||
724 | |||
725 | |||
726 | u32_t offset; |
||
727 | u8 slot; |
||
728 | int n=0; |
||
729 | int ret; |
||
730 | |||
731 | |||
732 | return -1; |
||
733 | |||
734 | |||
735 | |||
736 | |||
737 | return -1; |
||
738 | |||
739 | |||
740 | if(unlikely(context == NULL)) |
||
741 | return -1; |
||
742 | |||
743 | |||
744 | { |
||
745 | static warn_count; |
||
746 | |||
747 | |||
748 | { |
||
749 | printf("left %d top %d right %d bottom %d\n", |
||
750 | winrc.left, winrc.top, winrc.right, winrc.bottom); |
||
751 | printf("bitmap width %d height %d\n", w, h); |
||
752 | warn_count++; |
||
753 | }; |
||
754 | }; |
||
755 | |||
756 | |||
757 | |||
758 | dst_clip.ymin = 0; |
||
759 | dst_clip.xmax = winrc.right-winrc.left; |
||
760 | dst_clip.ymax = winrc.bottom -winrc.top; |
||
761 | |||
762 | |||
763 | src_clip.ymin = 0; |
||
764 | src_clip.xmax = bitmap->width - 1; |
||
765 | src_clip.ymax = bitmap->height - 1; |
||
766 | |||
767 | |||
768 | height = h; |
||
769 | |||
770 | |||
771 | &src_clip, &src_x, &src_y, |
||
772 | &width, &height) ) |
||
773 | return 0; |
||
774 | |||
775 | |||
776 | dst_y+= winrc.top; |
||
777 | |||
778 | |||
779 | |||
780 | |||
781 | |||
782 | |||
783 | #if 0 |
||
3124 | serge | 784 | #else |
3120 | serge | 785 | u8* src_offset; |
786 | u8* dst_offset; |
||
787 | u32 color; |
||
3124 | serge | 788 | |
789 | |||
3120 | serge | 790 | |
791 | |||
792 | src_offset += (u32)bitmap->uaddr; |
||
793 | |||
794 | |||
795 | dst_offset+= get_display_map(); |
||
796 | |||
797 | |||
798 | |||
799 | |||
800 | while( tmp_h--) |
||
801 | { |
||
802 | u32 tmp_w = width; |
||
3124 | serge | 803 | |
3120 | serge | 804 | |
3124 | serge | 805 | u8* tmp_dst = dst_offset; |
3764 | Serge | 806 | |
3120 | serge | 807 | |
808 | dst_offset+= rdisplay->width; |
||
809 | |||
810 | |||
811 | { |
||
812 | color = *tmp_src; |
||
3124 | serge | 813 | |
814 | |||
815 | color |= 0xFF000000; |
||
816 | else |
||
817 | color = 0x00; |
||
818 | |||
819 | |||
820 | tmp_src++; |
||
821 | tmp_dst++; |
||
3120 | serge | 822 | }; |
823 | }; |
||
824 | safe_sti(ifl); |
||
825 | #endif |
||
826 | } |
||
827 | |||
828 | |||
829 | static warn_count; |
||
830 | |||
831 | |||
832 | { |
||
833 | printf("blit width %d height %d\n", |
||
834 | width, height); |
||
835 | warn_count++; |
||
836 | }; |
||
837 | }; |
||
838 | |||
839 | |||
840 | |||
841 | // context->cmd_buffer&= 0xFFFFF000; |
||
842 | |||
843 | |||
844 | |||
845 | |||
846 | |||
847 | |||
848 | |||
849 | |||
850 | |||
851 | struct radeon_ib *ib = &context->ib; |
||
852 | |||
853 | |||
3124 | serge | 854 | ib->ptr[1] = 0xFFFFFFFF; |
855 | ib->ptr[2] = PACKET3(PACKET3_TRANS_BITBLT, 11); |
||
856 | ib->ptr[3] = RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
||
857 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
||
3120 | serge | 858 | RADEON_GMC_SRC_CLIPPING | |
859 | RADEON_GMC_DST_CLIPPING | |
||
860 | RADEON_GMC_BRUSH_NONE | |
||
861 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
||
862 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
863 | RADEON_ROP3_S | |
||
864 | RADEON_DP_SRC_SOURCE_MEMORY | |
||
865 | RADEON_GMC_WR_MSK_DIS; |
||
866 | |||
867 | |||
3124 | serge | 868 | ib->ptr[5] = ((rdisplay->pitch/64) << 22) | (rdev->mc.vram_start >> 10); |
869 | ib->ptr[6] = (0x1fff) | (0x1fff << 16); |
||
3120 | serge | 870 | ib->ptr[7] = 0; |
3124 | serge | 871 | ib->ptr[8] = (0x1fff) | (0x1fff << 16); |
872 | |||
3120 | serge | 873 | |
3124 | serge | 874 | ib->ptr[10] = 0x00000000; |
875 | ib->ptr[11] = 0xFFFFFFFF; |
||
876 | |||
3120 | serge | 877 | |
3124 | serge | 878 | ib->ptr[13] = (dst_x << 16) | dst_y; |
879 | ib->ptr[14] = (width << 16) | height; |
||
880 | |||
881 | |||
3120 | serge | 882 | |
883 | |||
884 | |||
885 | |||
886 | if (ret) { |
||
887 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", ret); |
||
888 | goto fail; |
||
889 | } |
||
890 | |||
891 | |||
892 | if (ret) { |
||
893 | DRM_ERROR("radeon: fence wait failed (%d).\n", ret); |
||
894 | goto fail; |
||
895 | } |
||
896 | |||
897 | |||
3192 | Serge | 898 | |
899 | |||
3120 | serge | 900 | return ret; |
901 | }; |
||
902 | |||
903 | |||
3764 | Serge | 904 |