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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include "radeon_drm.h" |
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5 | #include "radeon.h" |
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6 | #include "radeon_object.h" |
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7 | #include "display.h" |
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8 | #include "drm_fb_helper.h" |
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1986 | serge | 9 | |
1246 | serge | 10 | |
1986 | serge | 11 | struct drm_fb_helper helper; |
12 | struct radeon_framebuffer rfb; |
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13 | struct list_head fbdev_list; |
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14 | struct radeon_device *rdev; |
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15 | }; |
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16 | |||
1246 | serge | 17 | |
1986 | serge | 18 | |
19 | |||
20 | |||
1246 | serge | 21 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
22 | |||
23 | |||
24 | |||
25 | |||
1313 | serge | 26 | |
27 | |||
1246 | serge | 28 | { |
29 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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30 | struct radeon_device *rdev = crtc->dev->dev_private; |
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31 | |||
32 | |||
2004 | serge | 33 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
34 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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35 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); |
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36 | } else if (ASIC_IS_AVIVO(rdev)) { |
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37 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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1246 | serge | 38 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
39 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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40 | } else { |
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41 | switch (radeon_crtc->crtc_id) { |
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42 | case 0: |
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43 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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44 | break; |
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45 | case 1: |
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46 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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47 | break; |
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48 | default: |
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49 | return; |
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50 | } |
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51 | |||
52 | |||
53 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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54 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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55 | } |
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56 | } |
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57 | |||
58 | |||
59 | { |
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60 | struct radeon_device *rdev = crtc->dev->dev_private; |
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61 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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62 | uint32_t cur_lock; |
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63 | |||
64 | |||
2004 | serge | 65 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); |
66 | if (lock) |
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67 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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68 | else |
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69 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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70 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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71 | } else if (ASIC_IS_AVIVO(rdev)) { |
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72 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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1246 | serge | 73 | if (lock) |
74 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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75 | else |
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76 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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77 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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78 | } else { |
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79 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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80 | if (lock) |
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81 | cur_lock |= RADEON_CUR_LOCK; |
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82 | else |
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83 | cur_lock &= ~RADEON_CUR_LOCK; |
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84 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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85 | } |
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86 | } |
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87 | |||
88 | |||
89 | { |
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90 | struct radeon_device *rdev; |
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91 | struct radeon_crtc *radeon_crtc; |
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92 | cursor_t *old; |
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93 | uint32_t gpu_addr; |
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94 | |||
95 | |||
96 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
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97 | |||
98 | |||
99 | |||
100 | |||
101 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
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1404 | serge | 102 | |
1246 | serge | 103 | |
2004 | serge | 104 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
105 | 0); |
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106 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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107 | gpu_addr); |
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108 | } else if (ASIC_IS_AVIVO(rdev)) { |
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109 | if (rdev->family >= CHIP_RV770) |
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110 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); |
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111 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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1246 | serge | 112 | } |
2004 | serge | 113 | else { |
1246 | serge | 114 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start; |
1430 | serge | 115 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 116 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
117 | } |
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118 | |||
119 | |||
120 | }; |
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121 | |||
122 | |||
123 | { |
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124 | struct radeon_device *rdev; |
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125 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
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126 | struct drm_crtc *crtc = rdisplay->crtc; |
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127 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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128 | |||
129 | |||
130 | int hot_y = cursor->hot_y; |
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131 | int w = 32; |
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2004 | serge | 132 | |
1246 | serge | 133 | |
134 | |||
135 | |||
2004 | serge | 136 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, |
137 | (x << 16) | y); |
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138 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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139 | (hot_x << 16) | hot_y); |
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140 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, |
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141 | ((w - 1) << 16) | 31); |
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142 | } else if (ASIC_IS_AVIVO(rdev)) { |
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143 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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1246 | serge | 144 | (x << 16) | y); |
145 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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146 | (hot_x << 16) | hot_y); |
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147 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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148 | ((w - 1) << 16) | 31); |
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149 | } else { |
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150 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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151 | y *= 2; |
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152 | |||
153 | |||
1404 | serge | 154 | int xorg =0, yorg=0; |
155 | |||
156 | |||
157 | y = y - hot_y; |
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158 | |||
159 | |||
160 | { |
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161 | xorg = -x + 1; |
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162 | x = 0; |
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163 | } |
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164 | |||
165 | |||
166 | { |
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167 | yorg = -hot_y + 1; |
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168 | y = 0; |
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169 | }; |
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170 | |||
171 | |||
172 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
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173 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
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174 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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1246 | serge | 175 | |
176 | |||
1404 | serge | 177 | |
178 | |||
1246 | serge | 179 | WREG32(RADEON_CUR_OFFSET, |
1404 | serge | 180 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 181 | } |
1246 | serge | 182 | radeon_lock_cursor_kms(crtc, false); |
183 | } |
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184 | |||
185 | |||
186 | { |
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187 | static char name[4]; |
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188 | |||
189 | |||
190 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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191 | name[2] = (x[1] & 0x1F) + '@'; |
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192 | name[3] = 0; |
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193 | |||
194 | |||
195 | } |
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196 | |||
197 | |||
198 | videomode_t *reqmode, bool strict) |
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1403 | serge | 199 | { |
1246 | serge | 200 | struct drm_display_mode *mode = NULL, *tmpmode; |
201 | |||
202 | |||
1986 | serge | 203 | |
204 | |||
205 | |||
206 | |||
207 | |||
1246 | serge | 208 | |
209 | |||
210 | |||
211 | |||
212 | reqmode->width, reqmode->height, reqmode->freq); |
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213 | |||
214 | |||
215 | { |
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216 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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217 | (drm_mode_height(tmpmode) == reqmode->height) && |
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218 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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219 | { |
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220 | mode = tmpmode; |
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221 | goto do_set; |
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222 | } |
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223 | }; |
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224 | |||
225 | |||
226 | { |
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227 | list_for_each_entry(tmpmode, &connector->modes, head) |
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228 | { |
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229 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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230 | (drm_mode_height(tmpmode) == reqmode->height) ) |
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231 | { |
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232 | mode = tmpmode; |
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233 | goto do_set; |
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234 | } |
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235 | }; |
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236 | }; |
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237 | |||
238 | |||
239 | |||
240 | |||
241 | { |
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242 | struct drm_framebuffer *fb; |
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243 | struct drm_encoder *encoder; |
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244 | struct drm_crtc *crtc; |
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245 | |||
246 | |||
247 | char *con_name; |
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248 | char *enc_name; |
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249 | |||
250 | |||
251 | crtc = encoder->crtc; |
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252 | |||
253 | |||
1963 | serge | 254 | // struct drm_framebuffer, filp_head); |
255 | |||
1246 | serge | 256 | |
257 | |||
258 | |||
259 | // manufacturer_name(con_edid + 0x08), |
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260 | // (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
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261 | // (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
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262 | // + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
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263 | |||
264 | |||
265 | enc_name = drm_get_encoder_name(encoder); |
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266 | |||
267 | |||
268 | reqmode->width, reqmode->height, con_name, enc_name); |
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269 | |||
270 | |||
1986 | serge | 271 | |
272 | |||
1246 | serge | 273 | fb->height = reqmode->height; |
274 | |||
2997 | Serge | 275 | |
276 | fb->pitches[3] = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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277 | fb->bits_per_pixel = 32; |
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1986 | serge | 278 | fb->depth = 24; |
2997 | Serge | 279 | |
1246 | serge | 280 | |
281 | crtc->enabled = true; |
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282 | rdisplay->crtc = crtc; |
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283 | |||
284 | |||
285 | |||
286 | |||
287 | radeon_show_cursor_kms(crtc); |
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288 | |||
289 | |||
290 | { |
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291 | rdisplay->width = fb->width; |
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292 | rdisplay->height = fb->height; |
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293 | rdisplay->pitch = fb->pitches[0]; |
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2997 | Serge | 294 | rdisplay->vrefresh = drm_mode_vrefresh(mode); |
1246 | serge | 295 | |
296 | |||
2997 | Serge | 297 | |
1246 | serge | 298 | |
299 | fb->width, fb->height, fb->pitches[0]); |
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2997 | Serge | 300 | } |
1246 | serge | 301 | else |
302 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
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303 | fb->width, fb->height, crtc); |
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304 | } |
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305 | |||
306 | |||
307 | return ret; |
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308 | }; |
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309 | |||
310 | |||
311 | { |
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312 | struct drm_display_mode *mode; |
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313 | int count = 0; |
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314 | |||
315 | |||
316 | { |
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317 | count++; |
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318 | }; |
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319 | return count; |
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320 | }; |
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321 | |||
322 | |||
323 | { |
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324 | struct drm_connector *connector; |
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325 | struct drm_connector_helper_funcs *connector_funcs; |
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1963 | serge | 326 | |
327 | |||
1246 | serge | 328 | |
329 | |||
330 | { |
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331 | struct drm_encoder *encoder; |
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332 | struct drm_crtc *crtc; |
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333 | |||
334 | |||
335 | continue; |
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336 | |||
337 | |||
1963 | serge | 338 | encoder = connector_funcs->best_encoder(connector); |
339 | if( encoder == NULL) |
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1246 | serge | 340 | continue; |
341 | |||
342 | |||
1963 | serge | 343 | |
344 | |||
1246 | serge | 345 | |
1963 | serge | 346 | |
1986 | serge | 347 | connector, connector->base.id, |
348 | connector->status, connector->encoder, |
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349 | crtc); |
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350 | |||
1246 | serge | 351 | |
1986 | serge | 352 | // continue; |
353 | |||
354 | |||
1246 | serge | 355 | |
1986 | serge | 356 | |
1246 | serge | 357 | }; |
358 | |||
359 | |||
360 | }; |
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361 | |||
362 | |||
1986 | serge | 363 | |
364 | |||
1403 | serge | 365 | { |
1246 | serge | 366 | struct drm_device *dev; |
367 | |||
368 | |||
2997 | Serge | 369 | struct drm_connector_helper_funcs *connector_funcs; |
370 | struct drm_encoder *encoder; |
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371 | struct drm_crtc *crtc = NULL; |
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372 | struct drm_framebuffer *fb; |
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373 | struct drm_display_mode *native; |
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374 | |||
375 | |||
376 | |||
1246 | serge | 377 | bool retval = false; |
378 | u32_t ifl; |
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379 | |||
380 | |||
1986 | serge | 381 | struct drm_fb_helper *fb_helper; |
382 | |||
383 | |||
384 | |||
385 | |||
1246 | serge | 386 | |
387 | |||
2997 | Serge | 388 | |
1246 | serge | 389 | |
2997 | Serge | 390 | { |
391 | if( connector->status != connector_status_connected) |
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392 | continue; |
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393 | |||
1246 | serge | 394 | |
2997 | Serge | 395 | encoder = connector_funcs->best_encoder(connector); |
396 | if( encoder == NULL) |
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397 | { |
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398 | dbgprintf("CONNECTOR %x ID: %d no active encoders\n", |
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399 | connector, connector->base.id); |
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400 | continue; |
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401 | } |
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402 | connector->encoder = encoder; |
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403 | |||
404 | |||
405 | connector, connector->base.id, |
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406 | connector->status, connector->encoder, |
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407 | encoder->crtc); |
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408 | |||
409 | |||
410 | break; |
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411 | }; |
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412 | |||
413 | |||
414 | { |
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1246 | serge | 415 | dbgprintf("No active connectors!\n"); |
2997 | Serge | 416 | return -1; |
417 | }; |
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418 | |||
419 | |||
420 | struct drm_display_mode *tmp; |
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421 | |||
422 | |||
423 | if (drm_mode_width(tmp) > 16384 || |
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424 | drm_mode_height(tmp) > 16384) |
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425 | continue; |
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426 | if (tmp->type & DRM_MODE_TYPE_PREFERRED) |
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427 | { |
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428 | native = tmp; |
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429 | break; |
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430 | }; |
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431 | } |
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432 | } |
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433 | |||
434 | |||
435 | { |
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436 | dbgprintf("native w %d h %d\n", native->hdisplay, native->vdisplay); |
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437 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(connector->encoder); |
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438 | radeon_encoder->rmx_type = RMX_FULL; |
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439 | radeon_encoder->native_mode = *native; |
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440 | }; |
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441 | |||
442 | |||
443 | |||
444 | { |
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445 | struct drm_crtc *tmp_crtc; |
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446 | int crtc_mask = 1; |
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447 | |||
448 | |||
449 | { |
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1246 | serge | 450 | if (encoder->possible_crtcs & crtc_mask) |
2997 | Serge | 451 | { |
452 | crtc = tmp_crtc; |
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453 | encoder->crtc = crtc; |
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454 | break; |
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455 | }; |
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456 | crtc_mask <<= 1; |
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457 | }; |
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1246 | serge | 458 | }; |
459 | |||
460 | |||
2997 | Serge | 461 | { |
462 | dbgprintf("No CRTC for encoder %d\n", encoder->base.id); |
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463 | return -1; |
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464 | }; |
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465 | |||
1986 | serge | 466 | |
467 | |||
2997 | Serge | 468 | |
1986 | serge | 469 | |
470 | |||
2997 | Serge | 471 | |
1986 | serge | 472 | |
2997 | Serge | 473 | rdisplay->ddev = dev; |
474 | rdisplay->connector = connector; |
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475 | rdisplay->crtc = crtc; |
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476 | |||
1986 | serge | 477 | |
2997 | Serge | 478 | |
1986 | serge | 479 | |
480 | |||
481 | |||
2997 | Serge | 482 | { |
483 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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484 | { |
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485 | init_cursor(cursor); |
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486 | }; |
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487 | |||
1986 | serge | 488 | |
1246 | serge | 489 | safe_sti(ifl); |
2997 | Serge | 490 | |
1246 | serge | 491 | |
1986 | serge | 492 | |
1268 | serge | 493 | rdisplay->width, rdisplay->height, rdisplay->vrefresh); |
494 | dbgprintf("user mode mode %d x %d x %d\n", |
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495 | usermode->width, usermode->height, usermode->freq); |
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496 | |||
497 | |||
2997 | Serge | 498 | |
1246 | serge | 499 | (usermode->height != 0) && |
500 | ( (usermode->width != rdisplay->width) || |
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501 | (usermode->height != rdisplay->height) || |
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502 | (usermode->freq != rdisplay->vrefresh) ) ) |
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503 | { |
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504 | |||
505 | |||
506 | } |
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507 | else |
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2997 | Serge | 508 | { |
509 | usermode->width = rdisplay->width; |
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510 | usermode->height = rdisplay->height; |
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511 | usermode->freq = 60; |
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512 | retval = set_mode(dev, rdisplay->connector, usermode, false); |
||
513 | }; |
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514 | |||
1246 | serge | 515 | |
516 | { |
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517 | rdisplay->restore_cursor(0,0); |
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518 | rdisplay->init_cursor = init_cursor; |
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519 | rdisplay->select_cursor = select_cursor_kms; |
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520 | rdisplay->show_cursor = NULL; |
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521 | rdisplay->move_cursor = move_cursor_kms; |
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522 | rdisplay->restore_cursor = restore_cursor; |
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523 | rdisplay->disable_mouse = disable_mouse; |
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1313 | serge | 524 | |
1268 | serge | 525 | |
526 | radeon_show_cursor_kms(rdisplay->crtc); |
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1246 | serge | 527 | }; |
528 | safe_sti(ifl); |
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529 | |||
530 | |||
531 | |||
532 | |||
533 | }; |
||
534 | |||
535 | |||
1403 | serge | 536 | { |
1246 | serge | 537 | int err = -1; |
538 | |||
539 | |||
2997 | Serge | 540 | |
1246 | serge | 541 | |
542 | |||
543 | |||
544 | { |
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545 | *count = rdisplay->supported_modes; |
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546 | err = 0; |
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547 | } |
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548 | else if( mode != NULL ) |
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549 | { |
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550 | struct drm_display_mode *drmmode; |
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551 | int i = 0; |
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552 | |||
553 | |||
554 | *count = rdisplay->supported_modes; |
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555 | |||
556 | |||
557 | { |
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558 | if( i < *count) |
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559 | { |
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560 | mode->width = drm_mode_width(drmmode); |
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561 | mode->height = drm_mode_height(drmmode); |
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562 | mode->bpp = 32; |
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563 | mode->freq = drm_mode_vrefresh(drmmode); |
||
564 | i++; |
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565 | mode++; |
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566 | } |
||
567 | else break; |
||
568 | }; |
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569 | *count = i; |
||
570 | err = 0; |
||
571 | }; |
||
572 | // LEAVE(); |
||
2997 | Serge | 573 | return err; |
1246 | serge | 574 | } |
575 | |||
576 | |||
1403 | serge | 577 | { |
1246 | serge | 578 | int err = -1; |
579 | |||
580 | |||
2997 | Serge | 581 | |
1246 | serge | 582 | |
583 | mode->width, mode->height, mode->freq); |
||
584 | |||
585 | |||
586 | (mode->height != 0) && |
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587 | (mode->freq != 0 ) && |
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588 | ( (mode->width != rdisplay->width) || |
||
589 | (mode->height != rdisplay->height) || |
||
590 | (mode->freq != rdisplay->vrefresh) ) ) |
||
591 | { |
||
592 | if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) ) |
||
593 | err = 0; |
||
594 | }; |
||
595 | |||
596 | |||
2997 | Serge | 597 | return err; |
1246 | serge | 598 | }; |
599 | |||
600 | |||
1986 | serge | 601 | |
2997 | Serge | 602 | struct drm_mode_fb_cmd2 *mode_cmd, |
603 | struct drm_gem_object **gobj_p) |
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1986 | serge | 604 | { |
1404 | serge | 605 | struct radeon_device *rdev = rfbdev->rdev; |
1986 | serge | 606 | struct drm_gem_object *gobj = NULL; |
607 | struct radeon_bo *rbo = NULL; |
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608 | bool fb_tiled = false; /* useful for testing */ |
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609 | u32 tiling_flags = 0; |
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610 | int ret; |
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611 | int aligned_size, size; |
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612 | int height = mode_cmd->height; |
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613 | u32 bpp, depth; |
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2997 | Serge | 614 | |
1404 | serge | 615 | |
1986 | serge | 616 | static struct drm_mm_node vm_node; |
617 | |||
618 | |||
2997 | Serge | 619 | |
620 | |||
621 | |||
1986 | serge | 622 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, |
2997 | Serge | 623 | fb_tiled) * ((bpp + 1) / 8); |
624 | |||
1986 | serge | 625 | |
626 | height = ALIGN(mode_cmd->height, 8); |
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627 | size = mode_cmd->pitches[0] * height; |
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2997 | Serge | 628 | aligned_size = ALIGN(size, PAGE_SIZE); |
1986 | serge | 629 | |
630 | |||
2997 | Serge | 631 | |
1986 | serge | 632 | if (unlikely(ret)) { |
633 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
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2997 | Serge | 634 | aligned_size); |
635 | return -ENOMEM; |
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636 | } |
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1404 | serge | 637 | |
638 | |||
1986 | serge | 639 | kos_bo.gem_base.driver_private = NULL; |
640 | kos_bo.surface_reg = -1; |
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641 | kos_bo.domain = RADEON_GEM_DOMAIN_VRAM; |
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642 | |||
643 | |||
644 | |||
645 | |||
646 | rbo = gem_to_radeon_bo(gobj); |
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647 | |||
648 | |||
649 | tiling_flags = RADEON_TILING_MACRO; |
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650 | |||
651 | |||
2997 | Serge | 652 | // ret = radeon_bo_set_tiling_flags(rbo, |
653 | // tiling_flags | RADEON_TILING_SURFACE, |
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654 | // mode_cmd->pitches[0]); |
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655 | // if (ret) |
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656 | // dev_err(rdev->dev, "FB failed to set tiling flags\n"); |
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657 | // } |
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658 | |||
1404 | serge | 659 | |
1986 | serge | 660 | vm_node.start = 0; |
661 | vm_node.mm = NULL; |
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662 | |||
663 | |||
664 | rbo->tbo.offset = rbo->tbo.vm_node->start << PAGE_SHIFT; |
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665 | rbo->tbo.offset += (u64)rbo->rdev->mc.vram_start; |
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666 | rbo->kptr = (void*)0xFE000000; |
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667 | rbo->pin_count = 1; |
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668 | |||
669 | |||
670 | |||
671 | return 0; |
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672 | }><>>=><=>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><> |
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1404 | serge | 673 |