Rev 1963 | Rev 2175 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1221 | serge | 1 | |
| 2 | #include |
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| 3 | #include |
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| 4 | #include "radeon_drm.h" |
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| 5 | #include "radeon.h" |
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| 6 | #include "radeon_object.h" |
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| 7 | #include "display.h" |
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| 1246 | serge | 8 | |
| 1221 | serge | 9 | |
| 1428 | serge | 10 | |
| 11 | |||
| 12 | |||
| 1246 | serge | 13 | |
| 1221 | serge | 14 | |
| 1246 | serge | 15 | static void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
| 16 | |||
| 1221 | serge | 17 | |
| 1963 | serge | 18 | |
| 1313 | serge | 19 | |
| 20 | {}; |
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| 21 | |||
| 22 | |||
| 1221 | serge | 23 | { |
| 24 | struct radeon_device *rdev; |
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| 25 | |||
| 26 | |||
| 27 | uint32_t *src; |
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| 28 | |||
| 29 | |||
| 30 | int r; |
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| 31 | |||
| 32 | |||
| 33 | |||
| 34 | |||
| 1963 | serge | 35 | PAGE_SIZE, false, RADEON_GEM_DOMAIN_VRAM, &cursor->robj); |
| 36 | |||
| 1221 | serge | 37 | |
| 38 | return r; |
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| 39 | |||
| 40 | |||
| 1404 | serge | 41 | if (unlikely(r != 0)) |
| 42 | return r; |
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| 43 | |||
| 1221 | serge | 44 | |
| 1404 | serge | 45 | if (unlikely(r != 0)) |
| 46 | return r; |
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| 47 | |||
| 48 | |||
| 49 | if (r) { |
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| 1221 | serge | 50 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
| 51 | return r; |
||
| 52 | }; |
||
| 53 | |||
| 54 | |||
| 55 | |||
| 56 | |||
| 57 | { |
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| 58 | for(j = 0; j < 32; j++) |
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| 59 | *bits++ = *src++; |
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| 60 | for(j = 32; j < CURSOR_WIDTH; j++) |
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| 1230 | serge | 61 | *bits++ = 0; |
| 1221 | serge | 62 | } |
| 63 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
||
| 64 | *bits++ = 0; |
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| 65 | |||
| 66 | |||
| 1404 | serge | 67 | |
| 1221 | serge | 68 | |
| 1963 | serge | 69 | |
| 1313 | serge | 70 | |
| 1221 | serge | 71 | }; |
| 72 | |||
| 73 | |||
| 1963 | serge | 74 | { |
| 1313 | serge | 75 | list_del(&cursor->list); |
| 76 | radeon_bo_unpin(cursor->robj); |
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| 1404 | serge | 77 | KernelFree(cursor->data); |
| 1313 | serge | 78 | __DestroyObject(cursor); |
| 79 | }; |
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| 80 | |||
| 81 | |||
| 1246 | serge | 82 | { |
| 1221 | serge | 83 | struct radeon_device *rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 1246 | serge | 84 | |
| 1230 | serge | 85 | |
| 2004 | serge | 86 | |
| 87 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL); |
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| 88 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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| 89 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); |
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| 90 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 91 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL); |
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| 1246 | serge | 92 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
| 1230 | serge | 93 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
| 94 | } else { |
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| 95 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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| 1275 | serge | 96 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
| 1230 | serge | 97 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
| 98 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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| 99 | } |
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| 100 | } |
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| 101 | |||
| 102 | |||
| 103 | { |
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| 1221 | serge | 104 | struct radeon_device *rdev; |
| 105 | cursor_t *old; |
||
| 106 | uint32_t gpu_addr; |
||
| 107 | |||
| 108 | |||
| 109 | |||
| 110 | |||
| 1230 | serge | 111 | |
| 1221 | serge | 112 | |
| 1230 | serge | 113 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
| 1404 | serge | 114 | |
| 1221 | serge | 115 | |
| 2004 | serge | 116 | { |
| 117 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH, 0); |
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| 118 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS, gpu_addr); |
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| 119 | } |
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| 120 | else if (ASIC_IS_AVIVO(rdev)) |
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| 121 | { |
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| 122 | if (rdev->family >= CHIP_RV770) |
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| 123 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); |
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| 124 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr); |
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| 1246 | serge | 125 | } |
| 2004 | serge | 126 | else { |
| 1221 | serge | 127 | WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_start); |
| 1430 | serge | 128 | } |
| 1221 | serge | 129 | |
| 1230 | serge | 130 | |
| 1221 | serge | 131 | }; |
| 132 | |||
| 133 | |||
| 1246 | serge | 134 | { |
| 135 | struct radeon_device *rdev; |
||
| 136 | |||
| 1221 | serge | 137 | |
| 1246 | serge | 138 | |
| 139 | |||
| 140 | |||
| 141 | |||
| 2004 | serge | 142 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE); |
| 143 | if (lock) |
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| 144 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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| 145 | else |
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| 146 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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| 147 | WREG32(EVERGREEN_CUR_UPDATE, cur_lock); |
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| 148 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 149 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE); |
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| 1246 | serge | 150 | if (lock) |
| 151 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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| 152 | else |
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| 153 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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| 154 | WREG32(AVIVO_D1CUR_UPDATE, cur_lock); |
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| 155 | } else { |
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| 156 | cur_lock = RREG32(RADEON_CUR_OFFSET); |
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| 157 | if (lock) |
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| 158 | cur_lock |= RADEON_CUR_LOCK; |
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| 159 | else |
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| 160 | cur_lock &= ~RADEON_CUR_LOCK; |
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| 161 | WREG32(RADEON_CUR_OFFSET, cur_lock); |
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| 162 | } |
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| 163 | } |
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| 164 | |||
| 165 | |||
| 166 | |||
| 1230 | serge | 167 | { |
| 1221 | serge | 168 | struct radeon_device *rdev; |
| 1230 | serge | 169 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
| 170 | |||
| 1221 | serge | 171 | |
| 1230 | serge | 172 | int hot_y = cursor->hot_y; |
| 173 | int w = 32; |
||
| 2004 | serge | 174 | |
| 1221 | serge | 175 | |
| 1246 | serge | 176 | |
| 1221 | serge | 177 | |
| 2004 | serge | 178 | WREG32(EVERGREEN_CUR_POSITION,(x << 16) | y); |
| 179 | WREG32(EVERGREEN_CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
||
| 180 | WREG32(EVERGREEN_CUR_SIZE, ((w - 1) << 16) | 31); |
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| 181 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
| 182 | WREG32(AVIVO_D1CUR_POSITION, (x << 16) | y); |
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| 1246 | serge | 183 | WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
| 184 | WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31); |
||
| 185 | } else { |
||
| 1275 | serge | 186 | |
| 1404 | serge | 187 | |
| 1246 | serge | 188 | int xorg =0, yorg=0; |
| 1404 | serge | 189 | |
| 1221 | serge | 190 | |
| 1404 | serge | 191 | y = y - hot_y; |
| 192 | |||
| 193 | |||
| 194 | { |
||
| 195 | xorg = -x + 1; |
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| 196 | x = 0; |
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| 197 | } |
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| 198 | |||
| 199 | |||
| 200 | { |
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| 201 | yorg = -hot_y + 1; |
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| 202 | y = 0; |
||
| 203 | }; |
||
| 204 | |||
| 205 | |||
| 1246 | serge | 206 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
| 1404 | serge | 207 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
| 1246 | serge | 208 | (RADEON_CUR_LOCK | (x << 16) | y)); |
| 1221 | serge | 209 | |
| 210 | |||
| 1404 | serge | 211 | |
| 1246 | serge | 212 | |
| 1221 | serge | 213 | WREG32(RADEON_CUR_OFFSET, |
| 1246 | serge | 214 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
| 1430 | serge | 215 | } |
| 1221 | serge | 216 | radeon_lock_cursor(false); |
| 1246 | serge | 217 | } |
| 1221 | serge | 218 | |
| 219 | |||
| 1230 | serge | 220 | { |
| 221 | }; |
||
| 222 | |||
| 1221 | serge | 223 | |
| 1233 | serge | 224 | |
| 1404 | serge | 225 | { |
| 1233 | serge | 226 | struct drm_device *dev; |
| 1275 | serge | 227 | |
| 1246 | serge | 228 | |
| 1275 | serge | 229 | bool retval = true; |
| 1268 | serge | 230 | u32_t ifl; |
| 1246 | serge | 231 | |
| 1233 | serge | 232 | |
| 233 | |||
| 234 | |||
| 235 | |||
| 236 | |||
| 1239 | serge | 237 | |
| 1233 | serge | 238 | |
| 1246 | serge | 239 | { |
| 240 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
||
| 1275 | serge | 241 | { |
| 242 | init_cursor(cursor); |
||
| 243 | }; |
||
| 244 | |||
| 1233 | serge | 245 | |
| 1275 | serge | 246 | rdisplay->init_cursor = init_cursor; |
| 247 | rdisplay->select_cursor = select_cursor; |
||
| 248 | rdisplay->show_cursor = NULL; |
||
| 249 | rdisplay->move_cursor = move_cursor; |
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| 250 | rdisplay->restore_cursor = restore_cursor; |
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| 251 | rdisplay->disable_mouse = disable_mouse; |
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| 1313 | serge | 252 | |
| 1233 | serge | 253 | |
| 1246 | serge | 254 | radeon_show_cursor(); |
| 255 | }; |
||
| 256 | safe_sti(ifl); |
||
| 257 | |||
| 258 | |||
| 1233 | serge | 259 | |
| 260 | |||
| 1239 | serge | 261 | }; |
| 1233 | serge | 262 | |
| 263 | |||
| 264 | |||
| 1404 | serge | 265 | { |
| 266 | #define BYTES_PER_LONG (BITS_PER_LONG/8) |
||
| 267 | #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) |
||
| 268 | int fb_info_size = sizeof(struct fb_info); |
||
| 269 | struct fb_info *info; |
||
| 270 | char *p; |
||
| 271 | |||
| 1233 | serge | 272 | |
| 1404 | serge | 273 | fb_info_size += PADDING; |
| 274 | |||
| 275 | |||
| 276 | |||
| 277 | |||
| 278 | return NULL; |
||
| 279 | |||
| 280 | |||
| 281 | |||
| 282 | |||
| 283 | info->par = p + fb_info_size; |
||
| 284 | |||
| 285 | |||
| 286 | #undef PADDING |
||
| 287 | #undef BYTES_PER_LONG |
||
| 288 | } |
||
| 289 | |||
| 290 | |||
| 291 | { |
||
| 292 | kfree(info); |
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| 293 | } |
||
| 294 | |||
| 295 | |||
| 1963 | serge | 296 | |
| 297 | |||
| 1428 | serge | 298 | # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| 299 | # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
||
| 300 | # define R5XX_ROP3_P 0x00f00000 |
||
| 301 | |||
| 302 | |||
| 303 | #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
||
| 304 | # define R5XX_SC_SIGN_MASK_LO 0x8000 |
||
| 305 | # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
||
| 306 | |||
| 307 | |||
| 308 | # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
||
| 309 | # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
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| 310 | |||
| 311 | |||
| 312 | |||
| 313 | { |
||
| 314 | |||
| 315 | |||
| 316 | uint32_t offset; |
||
| 317 | |||
| 318 | |||
| 319 | |||
| 320 | |||
| 321 | |||
| 322 | |||
| 323 | offset = rdev->mc.vram_start; |
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| 1430 | serge | 324 | |
| 1428 | serge | 325 | |
| 326 | if (r) { |
||
| 327 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
| 328 | return r; |
||
| 329 | } |
||
| 330 | radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0)); |
||
| 331 | radeon_ring_write(rdev, 0); |
||
| 332 | |||
| 333 | |||
| 334 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
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| 335 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
||
| 336 | |||
| 337 | |||
| 338 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
||
| 339 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
||
| 340 | |||
| 341 | |||
| 342 | radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
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| 343 | RADEON_GMC_BRUSH_SOLID_COLOR | |
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| 344 | RADEON_GMC_DST_32BPP | |
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| 345 | RADEON_GMC_SRC_DATATYPE_COLOR | |
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| 346 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
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| 347 | R5XX_GMC_WR_MSK_DIS | |
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| 348 | R5XX_ROP3_P); |
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| 349 | |||
| 350 | |||
| 351 | radeon_ring_write(rdev, 0x0000FF00); |
||
| 352 | radeon_ring_write(rdev, (64<<16)|64); |
||
| 353 | radeon_ring_write(rdev, (128<<16)|128); |
||
| 354 | |||
| 355 | |||
| 356 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
||
| 357 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
||
| 358 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | |
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| 359 | RADEON_WAIT_HOST_IDLECLEAN | |
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| 360 | RADEON_WAIT_DMA_GUI_IDLE); |
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| 361 | |||
| 362 | |||
| 363 | |||
| 364 | |||
| 365 | return r; |
||
| 366 | } |
||
| 367 | |||
| 368 | |||
| 369 | |||
| 370 | #include "r600_reg_r6xx.h" |
||
| 371 | #include "r600d.h" |
||
| 372 | |||
| 373 | |||
| 374 | { |
||
| 375 | 0xc0002400, |
||
| 376 | 0x00000000, |
||
| 377 | 0xc0012800, |
||
| 378 | 0x80000000, |
||
| 379 | 0x80000000, |
||
| 380 | 0xc0004600, |
||
| 381 | 0x00000016, |
||
| 382 | 0xc0016800, |
||
| 383 | 0x00000010, |
||
| 384 | 0x00028000, |
||
| 385 | 0xc0016800, |
||
| 386 | 0x00000010, |
||
| 387 | 0x00008000, |
||
| 388 | 0xc0016800, |
||
| 389 | 0x00000542, |
||
| 390 | 0x07000003, |
||
| 391 | 0xc0016800, |
||
| 392 | 0x000005c5, |
||
| 393 | 0x00000000, |
||
| 394 | 0xc0016800, |
||
| 395 | 0x00000363, |
||
| 396 | 0x00000000, |
||
| 397 | 0xc0016800, |
||
| 398 | 0x0000060c, |
||
| 399 | 0x82000000, |
||
| 400 | 0xc0016800, |
||
| 401 | 0x0000060e, |
||
| 402 | 0x01020204, |
||
| 403 | 0xc0016f00, |
||
| 404 | 0x00000000, |
||
| 405 | 0x00000000, |
||
| 406 | 0xc0016f00, |
||
| 407 | 0x00000001, |
||
| 408 | 0x00000000, |
||
| 409 | 0xc0096900, |
||
| 410 | 0x0000022a, |
||
| 411 | 0x00000000, |
||
| 412 | 0x00000000, |
||
| 413 | 0x00000000, |
||
| 414 | 0x00000000, |
||
| 415 | 0x00000000, |
||
| 416 | 0x00000000, |
||
| 417 | 0x00000000, |
||
| 418 | 0x00000000, |
||
| 419 | 0x00000000, |
||
| 420 | 0xc0016900, |
||
| 421 | 0x00000004, |
||
| 422 | 0x00000000, |
||
| 423 | 0xc0016900, |
||
| 424 | 0x0000000a, |
||
| 425 | 0x00000000, |
||
| 426 | 0xc0016900, |
||
| 427 | 0x0000000b, |
||
| 428 | 0x00000000, |
||
| 429 | 0xc0016900, |
||
| 430 | 0x0000010c, |
||
| 431 | 0x00000000, |
||
| 432 | 0xc0016900, |
||
| 433 | 0x0000010d, |
||
| 434 | 0x00000000, |
||
| 435 | 0xc0016900, |
||
| 436 | 0x00000200, |
||
| 437 | 0x00000000, |
||
| 438 | 0xc0016900, |
||
| 439 | 0x00000343, |
||
| 440 | 0x00000060, |
||
| 441 | 0xc0016900, |
||
| 442 | 0x00000344, |
||
| 443 | 0x00000040, |
||
| 444 | 0xc0016900, |
||
| 445 | 0x00000351, |
||
| 446 | 0x0000aa00, |
||
| 447 | 0xc0016900, |
||
| 448 | 0x00000104, |
||
| 449 | 0x00000000, |
||
| 450 | 0xc0016900, |
||
| 451 | 0x0000010e, |
||
| 452 | 0x00000000, |
||
| 453 | 0xc0046900, |
||
| 454 | 0x00000105, |
||
| 455 | 0x00000000, |
||
| 456 | 0x00000000, |
||
| 457 | 0x00000000, |
||
| 458 | 0x00000000, |
||
| 459 | 0xc0036900, |
||
| 460 | 0x00000109, |
||
| 461 | 0x00000000, |
||
| 462 | 0x00000000, |
||
| 463 | 0x00000000, |
||
| 464 | 0xc0046900, |
||
| 465 | 0x0000030c, |
||
| 466 | 0x01000000, |
||
| 467 | 0x00000000, |
||
| 468 | 0x00000000, |
||
| 469 | 0x00000000, |
||
| 470 | 0xc0046900, |
||
| 471 | 0x00000048, |
||
| 472 | 0x3f800000, |
||
| 473 | 0x00000000, |
||
| 474 | 0x3f800000, |
||
| 475 | 0x3f800000, |
||
| 476 | 0xc0016900, |
||
| 477 | 0x0000008e, |
||
| 478 | 0x0000000f, |
||
| 479 | 0xc0016900, |
||
| 480 | 0x00000080, |
||
| 481 | 0x00000000, |
||
| 482 | 0xc0016900, |
||
| 483 | 0x00000083, |
||
| 484 | 0x0000ffff, |
||
| 485 | 0xc0016900, |
||
| 486 | 0x00000084, |
||
| 487 | 0x00000000, |
||
| 488 | 0xc0016900, |
||
| 489 | 0x00000085, |
||
| 490 | 0x20002000, |
||
| 491 | 0xc0016900, |
||
| 492 | 0x00000086, |
||
| 493 | 0x00000000, |
||
| 494 | 0xc0016900, |
||
| 495 | 0x00000087, |
||
| 496 | 0x20002000, |
||
| 497 | 0xc0016900, |
||
| 498 | 0x00000088, |
||
| 499 | 0x00000000, |
||
| 500 | 0xc0016900, |
||
| 501 | 0x00000089, |
||
| 502 | 0x20002000, |
||
| 503 | 0xc0016900, |
||
| 504 | 0x0000008a, |
||
| 505 | 0x00000000, |
||
| 506 | 0xc0016900, |
||
| 507 | 0x0000008b, |
||
| 508 | 0x20002000, |
||
| 509 | 0xc0016900, |
||
| 510 | 0x0000008c, |
||
| 511 | 0x00000000, |
||
| 512 | 0xc0016900, |
||
| 513 | 0x00000094, |
||
| 514 | 0x80000000, |
||
| 515 | 0xc0016900, |
||
| 516 | 0x00000095, |
||
| 517 | 0x20002000, |
||
| 518 | 0xc0026900, |
||
| 519 | 0x000000b4, |
||
| 520 | 0x00000000, |
||
| 521 | 0x3f800000, |
||
| 522 | 0xc0016900, |
||
| 523 | 0x00000096, |
||
| 524 | 0x80000000, |
||
| 525 | 0xc0016900, |
||
| 526 | 0x00000097, |
||
| 527 | 0x20002000, |
||
| 528 | 0xc0026900, |
||
| 529 | 0x000000b6, |
||
| 530 | 0x00000000, |
||
| 531 | 0x3f800000, |
||
| 532 | 0xc0016900, |
||
| 533 | 0x00000098, |
||
| 534 | 0x80000000, |
||
| 535 | 0xc0016900, |
||
| 536 | 0x00000099, |
||
| 537 | 0x20002000, |
||
| 538 | 0xc0026900, |
||
| 539 | 0x000000b8, |
||
| 540 | 0x00000000, |
||
| 541 | 0x3f800000, |
||
| 542 | 0xc0016900, |
||
| 543 | 0x0000009a, |
||
| 544 | 0x80000000, |
||
| 545 | 0xc0016900, |
||
| 546 | 0x0000009b, |
||
| 547 | 0x20002000, |
||
| 548 | 0xc0026900, |
||
| 549 | 0x000000ba, |
||
| 550 | 0x00000000, |
||
| 551 | 0x3f800000, |
||
| 552 | 0xc0016900, |
||
| 553 | 0x0000009c, |
||
| 554 | 0x80000000, |
||
| 555 | 0xc0016900, |
||
| 556 | 0x0000009d, |
||
| 557 | 0x20002000, |
||
| 558 | 0xc0026900, |
||
| 559 | 0x000000bc, |
||
| 560 | 0x00000000, |
||
| 561 | 0x3f800000, |
||
| 562 | 0xc0016900, |
||
| 563 | 0x0000009e, |
||
| 564 | 0x80000000, |
||
| 565 | 0xc0016900, |
||
| 566 | 0x0000009f, |
||
| 567 | 0x20002000, |
||
| 568 | 0xc0026900, |
||
| 569 | 0x000000be, |
||
| 570 | 0x00000000, |
||
| 571 | 0x3f800000, |
||
| 572 | 0xc0016900, |
||
| 573 | 0x000000a0, |
||
| 574 | 0x80000000, |
||
| 575 | 0xc0016900, |
||
| 576 | 0x000000a1, |
||
| 577 | 0x20002000, |
||
| 578 | 0xc0026900, |
||
| 579 | 0x000000c0, |
||
| 580 | 0x00000000, |
||
| 581 | 0x3f800000, |
||
| 582 | 0xc0016900, |
||
| 583 | 0x000000a2, |
||
| 584 | 0x80000000, |
||
| 585 | 0xc0016900, |
||
| 586 | 0x000000a3, |
||
| 587 | 0x20002000, |
||
| 588 | 0xc0026900, |
||
| 589 | 0x000000c2, |
||
| 590 | 0x00000000, |
||
| 591 | 0x3f800000, |
||
| 592 | 0xc0016900, |
||
| 593 | 0x000000a4, |
||
| 594 | 0x80000000, |
||
| 595 | 0xc0016900, |
||
| 596 | 0x000000a5, |
||
| 597 | 0x20002000, |
||
| 598 | 0xc0026900, |
||
| 599 | 0x000000c4, |
||
| 600 | 0x00000000, |
||
| 601 | 0x3f800000, |
||
| 602 | 0xc0016900, |
||
| 603 | 0x000000a6, |
||
| 604 | 0x80000000, |
||
| 605 | 0xc0016900, |
||
| 606 | 0x000000a7, |
||
| 607 | 0x20002000, |
||
| 608 | 0xc0026900, |
||
| 609 | 0x000000c6, |
||
| 610 | 0x00000000, |
||
| 611 | 0x3f800000, |
||
| 612 | 0xc0016900, |
||
| 613 | 0x000000a8, |
||
| 614 | 0x80000000, |
||
| 615 | 0xc0016900, |
||
| 616 | 0x000000a9, |
||
| 617 | 0x20002000, |
||
| 618 | 0xc0026900, |
||
| 619 | 0x000000c8, |
||
| 620 | 0x00000000, |
||
| 621 | 0x3f800000, |
||
| 622 | 0xc0016900, |
||
| 623 | 0x000000aa, |
||
| 624 | 0x80000000, |
||
| 625 | 0xc0016900, |
||
| 626 | 0x000000ab, |
||
| 627 | 0x20002000, |
||
| 628 | 0xc0026900, |
||
| 629 | 0x000000ca, |
||
| 630 | 0x00000000, |
||
| 631 | 0x3f800000, |
||
| 632 | 0xc0016900, |
||
| 633 | 0x000000ac, |
||
| 634 | 0x80000000, |
||
| 635 | 0xc0016900, |
||
| 636 | 0x000000ad, |
||
| 637 | 0x20002000, |
||
| 638 | 0xc0026900, |
||
| 639 | 0x000000cc, |
||
| 640 | 0x00000000, |
||
| 641 | 0x3f800000, |
||
| 642 | 0xc0016900, |
||
| 643 | 0x000000ae, |
||
| 644 | 0x80000000, |
||
| 645 | 0xc0016900, |
||
| 646 | 0x000000af, |
||
| 647 | 0x20002000, |
||
| 648 | 0xc0026900, |
||
| 649 | 0x000000ce, |
||
| 650 | 0x00000000, |
||
| 651 | 0x3f800000, |
||
| 652 | 0xc0016900, |
||
| 653 | 0x000000b0, |
||
| 654 | 0x80000000, |
||
| 655 | 0xc0016900, |
||
| 656 | 0x000000b1, |
||
| 657 | 0x20002000, |
||
| 658 | 0xc0026900, |
||
| 659 | 0x000000d0, |
||
| 660 | 0x00000000, |
||
| 661 | 0x3f800000, |
||
| 662 | 0xc0016900, |
||
| 663 | 0x000000b2, |
||
| 664 | 0x80000000, |
||
| 665 | 0xc0016900, |
||
| 666 | 0x000000b3, |
||
| 667 | 0x20002000, |
||
| 668 | 0xc0026900, |
||
| 669 | 0x000000d2, |
||
| 670 | 0x00000000, |
||
| 671 | 0x3f800000, |
||
| 672 | 0xc0016900, |
||
| 673 | 0x00000293, |
||
| 674 | 0x00004010, |
||
| 675 | 0xc0016900, |
||
| 676 | 0x00000300, |
||
| 677 | 0x00000000, |
||
| 678 | 0xc0016900, |
||
| 679 | 0x00000301, |
||
| 680 | 0x00000000, |
||
| 681 | 0xc0016900, |
||
| 682 | 0x00000312, |
||
| 683 | 0xffffffff, |
||
| 684 | 0xc0016900, |
||
| 685 | 0x00000307, |
||
| 686 | 0x00000000, |
||
| 687 | 0xc0016900, |
||
| 688 | 0x00000308, |
||
| 689 | 0x00000000, |
||
| 690 | 0xc0016900, |
||
| 691 | 0x00000283, |
||
| 692 | 0x00000000, |
||
| 693 | 0xc0016900, |
||
| 694 | 0x00000292, |
||
| 695 | 0x00000000, |
||
| 696 | 0xc0066900, |
||
| 697 | 0x0000010f, |
||
| 698 | 0x00000000, |
||
| 699 | 0x00000000, |
||
| 700 | 0x00000000, |
||
| 701 | 0x00000000, |
||
| 702 | 0x00000000, |
||
| 703 | 0x00000000, |
||
| 704 | 0xc0016900, |
||
| 705 | 0x00000206, |
||
| 706 | 0x00000000, |
||
| 707 | 0xc0016900, |
||
| 708 | 0x00000207, |
||
| 709 | 0x00000000, |
||
| 710 | 0xc0016900, |
||
| 711 | 0x00000208, |
||
| 712 | 0x00000000, |
||
| 713 | 0xc0046900, |
||
| 714 | 0x00000303, |
||
| 715 | 0x3f800000, |
||
| 716 | 0x3f800000, |
||
| 717 | 0x3f800000, |
||
| 718 | 0x3f800000, |
||
| 719 | 0xc0016900, |
||
| 720 | 0x00000205, |
||
| 721 | 0x00000004, |
||
| 722 | 0xc0016900, |
||
| 723 | 0x00000280, |
||
| 724 | 0x00000000, |
||
| 725 | 0xc0016900, |
||
| 726 | 0x00000281, |
||
| 727 | 0x00000000, |
||
| 728 | 0xc0016900, |
||
| 729 | 0x0000037e, |
||
| 730 | 0x00000000, |
||
| 731 | 0xc0016900, |
||
| 732 | 0x00000382, |
||
| 733 | 0x00000000, |
||
| 734 | 0xc0016900, |
||
| 735 | 0x00000380, |
||
| 736 | 0x00000000, |
||
| 737 | 0xc0016900, |
||
| 738 | 0x00000383, |
||
| 739 | 0x00000000, |
||
| 740 | 0xc0016900, |
||
| 741 | 0x00000381, |
||
| 742 | 0x00000000, |
||
| 743 | 0xc0016900, |
||
| 744 | 0x00000282, |
||
| 745 | 0x00000008, |
||
| 746 | 0xc0016900, |
||
| 747 | 0x00000302, |
||
| 748 | 0x0000002d, |
||
| 749 | 0xc0016900, |
||
| 750 | 0x0000037f, |
||
| 751 | 0x00000000, |
||
| 752 | 0xc0016900, |
||
| 753 | 0x000001b2, |
||
| 754 | 0x00000000, |
||
| 755 | 0xc0016900, |
||
| 756 | 0x000001b6, |
||
| 757 | 0x00000000, |
||
| 758 | 0xc0016900, |
||
| 759 | 0x000001b7, |
||
| 760 | 0x00000000, |
||
| 761 | 0xc0016900, |
||
| 762 | 0x000001b8, |
||
| 763 | 0x00000000, |
||
| 764 | 0xc0016900, |
||
| 765 | 0x000001b9, |
||
| 766 | 0x00000000, |
||
| 767 | 0xc0016900, |
||
| 768 | 0x00000225, |
||
| 769 | 0x00000000, |
||
| 770 | 0xc0016900, |
||
| 771 | 0x00000229, |
||
| 772 | 0x00000000, |
||
| 773 | 0xc0016900, |
||
| 774 | 0x00000237, |
||
| 775 | 0x00000000, |
||
| 776 | 0xc0016900, |
||
| 777 | 0x00000100, |
||
| 778 | 0x00000800, |
||
| 779 | 0xc0016900, |
||
| 780 | 0x00000101, |
||
| 781 | 0x00000000, |
||
| 782 | 0xc0016900, |
||
| 783 | 0x00000102, |
||
| 784 | 0x00000000, |
||
| 785 | 0xc0016900, |
||
| 786 | 0x000002a8, |
||
| 787 | 0x00000000, |
||
| 788 | 0xc0016900, |
||
| 789 | 0x000002a9, |
||
| 790 | 0x00000000, |
||
| 791 | 0xc0016900, |
||
| 792 | 0x00000103, |
||
| 793 | 0x00000000, |
||
| 794 | 0xc0016900, |
||
| 795 | 0x00000284, |
||
| 796 | 0x00000000, |
||
| 797 | 0xc0016900, |
||
| 798 | 0x00000290, |
||
| 799 | 0x00000000, |
||
| 800 | 0xc0016900, |
||
| 801 | 0x00000285, |
||
| 802 | 0x00000000, |
||
| 803 | 0xc0016900, |
||
| 804 | 0x00000286, |
||
| 805 | 0x00000000, |
||
| 806 | 0xc0016900, |
||
| 807 | 0x00000287, |
||
| 808 | 0x00000000, |
||
| 809 | 0xc0016900, |
||
| 810 | 0x00000288, |
||
| 811 | 0x00000000, |
||
| 812 | 0xc0016900, |
||
| 813 | 0x00000289, |
||
| 814 | 0x00000000, |
||
| 815 | 0xc0016900, |
||
| 816 | 0x0000028a, |
||
| 817 | 0x00000000, |
||
| 818 | 0xc0016900, |
||
| 819 | 0x0000028b, |
||
| 820 | 0x00000000, |
||
| 821 | 0xc0016900, |
||
| 822 | 0x0000028c, |
||
| 823 | 0x00000000, |
||
| 824 | 0xc0016900, |
||
| 825 | 0x0000028d, |
||
| 826 | 0x00000000, |
||
| 827 | 0xc0016900, |
||
| 828 | 0x0000028e, |
||
| 829 | 0x00000000, |
||
| 830 | 0xc0016900, |
||
| 831 | 0x0000028f, |
||
| 832 | 0x00000000, |
||
| 833 | 0xc0016900, |
||
| 834 | 0x000002a1, |
||
| 835 | 0x00000000, |
||
| 836 | 0xc0016900, |
||
| 837 | 0x000002a5, |
||
| 838 | 0x00000000, |
||
| 839 | 0xc0016900, |
||
| 840 | 0x000002ac, |
||
| 841 | 0x00000000, |
||
| 842 | 0xc0016900, |
||
| 843 | 0x000002ad, |
||
| 844 | 0x00000000, |
||
| 845 | 0xc0016900, |
||
| 846 | 0x000002ae, |
||
| 847 | 0x00000000, |
||
| 848 | 0xc0016900, |
||
| 849 | 0x000002c8, |
||
| 850 | 0x00000000, |
||
| 851 | 0xc0016900, |
||
| 852 | 0x00000206, |
||
| 853 | 0x00000100, |
||
| 854 | 0xc0016900, |
||
| 855 | 0x00000204, |
||
| 856 | 0x00010000, |
||
| 857 | 0xc0036e00, |
||
| 858 | 0x00000000, |
||
| 859 | 0x00000012, |
||
| 860 | 0x00000000, |
||
| 861 | 0x00000000, |
||
| 862 | 0xc0016900, |
||
| 863 | 0x0000008f, |
||
| 864 | 0x0000000f, |
||
| 865 | 0xc0016900, |
||
| 866 | 0x000001e8, |
||
| 867 | 0x00000001, |
||
| 868 | 0xc0016900, |
||
| 869 | 0x00000202, |
||
| 870 | 0x00cc0000, |
||
| 871 | 0xc0016900, |
||
| 872 | 0x00000205, |
||
| 873 | 0x00000244, |
||
| 874 | 0xc0016900, |
||
| 875 | 0x00000203, |
||
| 876 | 0x00000210, |
||
| 877 | 0xc0016900, |
||
| 878 | 0x000001b1, |
||
| 879 | 0x00000000, |
||
| 880 | 0xc0016900, |
||
| 881 | 0x00000185, |
||
| 882 | 0x00000000, |
||
| 883 | 0xc0016900, |
||
| 884 | 0x000001b3, |
||
| 885 | 0x00000001, |
||
| 886 | 0xc0016900, |
||
| 887 | 0x000001b4, |
||
| 888 | 0x00000000, |
||
| 889 | 0xc0016900, |
||
| 890 | 0x00000191, |
||
| 891 | 0x00000b00, |
||
| 892 | 0xc0016900, |
||
| 893 | 0x000001b5, |
||
| 894 | 0x00000000, |
||
| 895 | }; |
||
| 896 | |||
| 897 | |||
| 898 | |||
| 899 | |||
| 900 | { |
||
| 901 | 0xc0012800, |
||
| 902 | 0x80000000, |
||
| 903 | 0x80000000, |
||
| 904 | 0xc0004600, |
||
| 905 | 0x00000016, |
||
| 906 | 0xc0016800, |
||
| 907 | 0x00000010, |
||
| 908 | 0x00028000, |
||
| 909 | 0xc0016800, |
||
| 910 | 0x00000010, |
||
| 911 | 0x00008000, |
||
| 912 | 0xc0016800, |
||
| 913 | 0x00000542, |
||
| 914 | 0x07000002, |
||
| 915 | 0xc0016800, |
||
| 916 | 0x000005c5, |
||
| 917 | 0x00000000, |
||
| 918 | 0xc0016800, |
||
| 919 | 0x00000363, |
||
| 920 | 0x00004000, |
||
| 921 | 0xc0016800, |
||
| 922 | 0x0000060c, |
||
| 923 | 0x00000000, |
||
| 924 | 0xc0016800, |
||
| 925 | 0x0000060e, |
||
| 926 | 0x00420204, |
||
| 927 | 0xc0016f00, |
||
| 928 | 0x00000000, |
||
| 929 | 0x00000000, |
||
| 930 | 0xc0016f00, |
||
| 931 | 0x00000001, |
||
| 932 | 0x00000000, |
||
| 933 | 0xc0096900, |
||
| 934 | 0x0000022a, |
||
| 935 | 0x00000000, |
||
| 936 | 0x00000000, |
||
| 937 | 0x00000000, |
||
| 938 | 0x00000000, |
||
| 939 | 0x00000000, |
||
| 940 | 0x00000000, |
||
| 941 | 0x00000000, |
||
| 942 | 0x00000000, |
||
| 943 | 0x00000000, |
||
| 944 | 0xc0016900, |
||
| 945 | 0x00000004, |
||
| 946 | 0x00000000, |
||
| 947 | 0xc0016900, |
||
| 948 | 0x0000000a, |
||
| 949 | 0x00000000, |
||
| 950 | 0xc0016900, |
||
| 951 | 0x0000000b, |
||
| 952 | 0x00000000, |
||
| 953 | 0xc0016900, |
||
| 954 | 0x0000010c, |
||
| 955 | 0x00000000, |
||
| 956 | 0xc0016900, |
||
| 957 | 0x0000010d, |
||
| 958 | 0x00000000, |
||
| 959 | 0xc0016900, |
||
| 960 | 0x00000200, |
||
| 961 | 0x00000000, |
||
| 962 | 0xc0016900, |
||
| 963 | 0x00000343, |
||
| 964 | 0x00000060, |
||
| 965 | 0xc0016900, |
||
| 966 | 0x00000344, |
||
| 967 | 0x00000000, |
||
| 968 | 0xc0016900, |
||
| 969 | 0x00000351, |
||
| 970 | 0x0000aa00, |
||
| 971 | 0xc0016900, |
||
| 972 | 0x00000104, |
||
| 973 | 0x00000000, |
||
| 974 | 0xc0016900, |
||
| 975 | 0x0000010e, |
||
| 976 | 0x00000000, |
||
| 977 | 0xc0046900, |
||
| 978 | 0x00000105, |
||
| 979 | 0x00000000, |
||
| 980 | 0x00000000, |
||
| 981 | 0x00000000, |
||
| 982 | 0x00000000, |
||
| 983 | 0xc0046900, |
||
| 984 | 0x0000030c, |
||
| 985 | 0x01000000, |
||
| 986 | 0x00000000, |
||
| 987 | 0x00000000, |
||
| 988 | 0x00000000, |
||
| 989 | 0xc0016900, |
||
| 990 | 0x0000008e, |
||
| 991 | 0x0000000f, |
||
| 992 | 0xc0016900, |
||
| 993 | 0x00000080, |
||
| 994 | 0x00000000, |
||
| 995 | 0xc0016900, |
||
| 996 | 0x00000083, |
||
| 997 | 0x0000ffff, |
||
| 998 | 0xc0016900, |
||
| 999 | 0x00000084, |
||
| 1000 | 0x00000000, |
||
| 1001 | 0xc0016900, |
||
| 1002 | 0x00000085, |
||
| 1003 | 0x20002000, |
||
| 1004 | 0xc0016900, |
||
| 1005 | 0x00000086, |
||
| 1006 | 0x00000000, |
||
| 1007 | 0xc0016900, |
||
| 1008 | 0x00000087, |
||
| 1009 | 0x20002000, |
||
| 1010 | 0xc0016900, |
||
| 1011 | 0x00000088, |
||
| 1012 | 0x00000000, |
||
| 1013 | 0xc0016900, |
||
| 1014 | 0x00000089, |
||
| 1015 | 0x20002000, |
||
| 1016 | 0xc0016900, |
||
| 1017 | 0x0000008a, |
||
| 1018 | 0x00000000, |
||
| 1019 | 0xc0016900, |
||
| 1020 | 0x0000008b, |
||
| 1021 | 0x20002000, |
||
| 1022 | 0xc0016900, |
||
| 1023 | 0x0000008c, |
||
| 1024 | 0xaaaaaaaa, |
||
| 1025 | 0xc0016900, |
||
| 1026 | 0x00000094, |
||
| 1027 | 0x80000000, |
||
| 1028 | 0xc0016900, |
||
| 1029 | 0x00000095, |
||
| 1030 | 0x20002000, |
||
| 1031 | 0xc0026900, |
||
| 1032 | 0x000000b4, |
||
| 1033 | 0x00000000, |
||
| 1034 | 0x3f800000, |
||
| 1035 | 0xc0016900, |
||
| 1036 | 0x00000096, |
||
| 1037 | 0x80000000, |
||
| 1038 | 0xc0016900, |
||
| 1039 | 0x00000097, |
||
| 1040 | 0x20002000, |
||
| 1041 | 0xc0026900, |
||
| 1042 | 0x000000b6, |
||
| 1043 | 0x00000000, |
||
| 1044 | 0x3f800000, |
||
| 1045 | 0xc0016900, |
||
| 1046 | 0x00000098, |
||
| 1047 | 0x80000000, |
||
| 1048 | 0xc0016900, |
||
| 1049 | 0x00000099, |
||
| 1050 | 0x20002000, |
||
| 1051 | 0xc0026900, |
||
| 1052 | 0x000000b8, |
||
| 1053 | 0x00000000, |
||
| 1054 | 0x3f800000, |
||
| 1055 | 0xc0016900, |
||
| 1056 | 0x0000009a, |
||
| 1057 | 0x80000000, |
||
| 1058 | 0xc0016900, |
||
| 1059 | 0x0000009b, |
||
| 1060 | 0x20002000, |
||
| 1061 | 0xc0026900, |
||
| 1062 | 0x000000ba, |
||
| 1063 | 0x00000000, |
||
| 1064 | 0x3f800000, |
||
| 1065 | 0xc0016900, |
||
| 1066 | 0x0000009c, |
||
| 1067 | 0x80000000, |
||
| 1068 | 0xc0016900, |
||
| 1069 | 0x0000009d, |
||
| 1070 | 0x20002000, |
||
| 1071 | 0xc0026900, |
||
| 1072 | 0x000000bc, |
||
| 1073 | 0x00000000, |
||
| 1074 | 0x3f800000, |
||
| 1075 | 0xc0016900, |
||
| 1076 | 0x0000009e, |
||
| 1077 | 0x80000000, |
||
| 1078 | 0xc0016900, |
||
| 1079 | 0x0000009f, |
||
| 1080 | 0x20002000, |
||
| 1081 | 0xc0026900, |
||
| 1082 | 0x000000be, |
||
| 1083 | 0x00000000, |
||
| 1084 | 0x3f800000, |
||
| 1085 | 0xc0016900, |
||
| 1086 | 0x000000a0, |
||
| 1087 | 0x80000000, |
||
| 1088 | 0xc0016900, |
||
| 1089 | 0x000000a1, |
||
| 1090 | 0x20002000, |
||
| 1091 | 0xc0026900, |
||
| 1092 | 0x000000c0, |
||
| 1093 | 0x00000000, |
||
| 1094 | 0x3f800000, |
||
| 1095 | 0xc0016900, |
||
| 1096 | 0x000000a2, |
||
| 1097 | 0x80000000, |
||
| 1098 | 0xc0016900, |
||
| 1099 | 0x000000a3, |
||
| 1100 | 0x20002000, |
||
| 1101 | 0xc0026900, |
||
| 1102 | 0x000000c2, |
||
| 1103 | 0x00000000, |
||
| 1104 | 0x3f800000, |
||
| 1105 | 0xc0016900, |
||
| 1106 | 0x000000a4, |
||
| 1107 | 0x80000000, |
||
| 1108 | 0xc0016900, |
||
| 1109 | 0x000000a5, |
||
| 1110 | 0x20002000, |
||
| 1111 | 0xc0026900, |
||
| 1112 | 0x000000c4, |
||
| 1113 | 0x00000000, |
||
| 1114 | 0x3f800000, |
||
| 1115 | 0xc0016900, |
||
| 1116 | 0x000000a6, |
||
| 1117 | 0x80000000, |
||
| 1118 | 0xc0016900, |
||
| 1119 | 0x000000a7, |
||
| 1120 | 0x20002000, |
||
| 1121 | 0xc0026900, |
||
| 1122 | 0x000000c6, |
||
| 1123 | 0x00000000, |
||
| 1124 | 0x3f800000, |
||
| 1125 | 0xc0016900, |
||
| 1126 | 0x000000a8, |
||
| 1127 | 0x80000000, |
||
| 1128 | 0xc0016900, |
||
| 1129 | 0x000000a9, |
||
| 1130 | 0x20002000, |
||
| 1131 | 0xc0026900, |
||
| 1132 | 0x000000c8, |
||
| 1133 | 0x00000000, |
||
| 1134 | 0x3f800000, |
||
| 1135 | 0xc0016900, |
||
| 1136 | 0x000000aa, |
||
| 1137 | 0x80000000, |
||
| 1138 | 0xc0016900, |
||
| 1139 | 0x000000ab, |
||
| 1140 | 0x20002000, |
||
| 1141 | 0xc0026900, |
||
| 1142 | 0x000000ca, |
||
| 1143 | 0x00000000, |
||
| 1144 | 0x3f800000, |
||
| 1145 | 0xc0016900, |
||
| 1146 | 0x000000ac, |
||
| 1147 | 0x80000000, |
||
| 1148 | 0xc0016900, |
||
| 1149 | 0x000000ad, |
||
| 1150 | 0x20002000, |
||
| 1151 | 0xc0026900, |
||
| 1152 | 0x000000cc, |
||
| 1153 | 0x00000000, |
||
| 1154 | 0x3f800000, |
||
| 1155 | 0xc0016900, |
||
| 1156 | 0x000000ae, |
||
| 1157 | 0x80000000, |
||
| 1158 | 0xc0016900, |
||
| 1159 | 0x000000af, |
||
| 1160 | 0x20002000, |
||
| 1161 | 0xc0026900, |
||
| 1162 | 0x000000ce, |
||
| 1163 | 0x00000000, |
||
| 1164 | 0x3f800000, |
||
| 1165 | 0xc0016900, |
||
| 1166 | 0x000000b0, |
||
| 1167 | 0x80000000, |
||
| 1168 | 0xc0016900, |
||
| 1169 | 0x000000b1, |
||
| 1170 | 0x20002000, |
||
| 1171 | 0xc0026900, |
||
| 1172 | 0x000000d0, |
||
| 1173 | 0x00000000, |
||
| 1174 | 0x3f800000, |
||
| 1175 | 0xc0016900, |
||
| 1176 | 0x000000b2, |
||
| 1177 | 0x80000000, |
||
| 1178 | 0xc0016900, |
||
| 1179 | 0x000000b3, |
||
| 1180 | 0x20002000, |
||
| 1181 | 0xc0026900, |
||
| 1182 | 0x000000d2, |
||
| 1183 | 0x00000000, |
||
| 1184 | 0x3f800000, |
||
| 1185 | 0xc0016900, |
||
| 1186 | 0x00000293, |
||
| 1187 | 0x00514000, |
||
| 1188 | 0xc0016900, |
||
| 1189 | 0x00000300, |
||
| 1190 | 0x00000000, |
||
| 1191 | 0xc0016900, |
||
| 1192 | 0x00000301, |
||
| 1193 | 0x00000000, |
||
| 1194 | 0xc0016900, |
||
| 1195 | 0x00000312, |
||
| 1196 | 0xffffffff, |
||
| 1197 | 0xc0016900, |
||
| 1198 | 0x00000307, |
||
| 1199 | 0x00000000, |
||
| 1200 | 0xc0016900, |
||
| 1201 | 0x00000308, |
||
| 1202 | 0x00000000, |
||
| 1203 | 0xc0016900, |
||
| 1204 | 0x00000283, |
||
| 1205 | 0x00000000, |
||
| 1206 | 0xc0016900, |
||
| 1207 | 0x00000292, |
||
| 1208 | 0x00000000, |
||
| 1209 | 0xc0066900, |
||
| 1210 | 0x0000010f, |
||
| 1211 | 0x00000000, |
||
| 1212 | 0x00000000, |
||
| 1213 | 0x00000000, |
||
| 1214 | 0x00000000, |
||
| 1215 | 0x00000000, |
||
| 1216 | 0x00000000, |
||
| 1217 | 0xc0016900, |
||
| 1218 | 0x00000206, |
||
| 1219 | 0x00000000, |
||
| 1220 | 0xc0016900, |
||
| 1221 | 0x00000207, |
||
| 1222 | 0x00000000, |
||
| 1223 | 0xc0016900, |
||
| 1224 | 0x00000208, |
||
| 1225 | 0x00000000, |
||
| 1226 | 0xc0046900, |
||
| 1227 | 0x00000303, |
||
| 1228 | 0x3f800000, |
||
| 1229 | 0x3f800000, |
||
| 1230 | 0x3f800000, |
||
| 1231 | 0x3f800000, |
||
| 1232 | 0xc0016900, |
||
| 1233 | 0x00000205, |
||
| 1234 | 0x00000004, |
||
| 1235 | 0xc0016900, |
||
| 1236 | 0x00000280, |
||
| 1237 | 0x00000000, |
||
| 1238 | 0xc0016900, |
||
| 1239 | 0x00000281, |
||
| 1240 | 0x00000000, |
||
| 1241 | 0xc0016900, |
||
| 1242 | 0x0000037e, |
||
| 1243 | 0x00000000, |
||
| 1244 | 0xc0016900, |
||
| 1245 | 0x00000382, |
||
| 1246 | 0x00000000, |
||
| 1247 | 0xc0016900, |
||
| 1248 | 0x00000380, |
||
| 1249 | 0x00000000, |
||
| 1250 | 0xc0016900, |
||
| 1251 | 0x00000383, |
||
| 1252 | 0x00000000, |
||
| 1253 | 0xc0016900, |
||
| 1254 | 0x00000381, |
||
| 1255 | 0x00000000, |
||
| 1256 | 0xc0016900, |
||
| 1257 | 0x00000282, |
||
| 1258 | 0x00000008, |
||
| 1259 | 0xc0016900, |
||
| 1260 | 0x00000302, |
||
| 1261 | 0x0000002d, |
||
| 1262 | 0xc0016900, |
||
| 1263 | 0x0000037f, |
||
| 1264 | 0x00000000, |
||
| 1265 | 0xc0016900, |
||
| 1266 | 0x000001b2, |
||
| 1267 | 0x00000001, |
||
| 1268 | 0xc0016900, |
||
| 1269 | 0x000001b6, |
||
| 1270 | 0x00000000, |
||
| 1271 | 0xc0016900, |
||
| 1272 | 0x000001b7, |
||
| 1273 | 0x00000000, |
||
| 1274 | 0xc0016900, |
||
| 1275 | 0x000001b8, |
||
| 1276 | 0x00000000, |
||
| 1277 | 0xc0016900, |
||
| 1278 | 0x000001b9, |
||
| 1279 | 0x00000000, |
||
| 1280 | 0xc0016900, |
||
| 1281 | 0x00000225, |
||
| 1282 | 0x00000000, |
||
| 1283 | 0xc0016900, |
||
| 1284 | 0x00000229, |
||
| 1285 | 0x00000000, |
||
| 1286 | 0xc0016900, |
||
| 1287 | 0x00000237, |
||
| 1288 | 0x00000000, |
||
| 1289 | 0xc0016900, |
||
| 1290 | 0x00000100, |
||
| 1291 | 0x00000800, |
||
| 1292 | 0xc0016900, |
||
| 1293 | 0x00000101, |
||
| 1294 | 0x00000000, |
||
| 1295 | 0xc0016900, |
||
| 1296 | 0x00000102, |
||
| 1297 | 0x00000000, |
||
| 1298 | 0xc0016900, |
||
| 1299 | 0x000002a8, |
||
| 1300 | 0x00000000, |
||
| 1301 | 0xc0016900, |
||
| 1302 | 0x000002a9, |
||
| 1303 | 0x00000000, |
||
| 1304 | 0xc0016900, |
||
| 1305 | 0x00000103, |
||
| 1306 | 0x00000000, |
||
| 1307 | 0xc0016900, |
||
| 1308 | 0x00000284, |
||
| 1309 | 0x00000000, |
||
| 1310 | 0xc0016900, |
||
| 1311 | 0x00000290, |
||
| 1312 | 0x00000000, |
||
| 1313 | 0xc0016900, |
||
| 1314 | 0x00000285, |
||
| 1315 | 0x00000000, |
||
| 1316 | 0xc0016900, |
||
| 1317 | 0x00000286, |
||
| 1318 | 0x00000000, |
||
| 1319 | 0xc0016900, |
||
| 1320 | 0x00000287, |
||
| 1321 | 0x00000000, |
||
| 1322 | 0xc0016900, |
||
| 1323 | 0x00000288, |
||
| 1324 | 0x00000000, |
||
| 1325 | 0xc0016900, |
||
| 1326 | 0x00000289, |
||
| 1327 | 0x00000000, |
||
| 1328 | 0xc0016900, |
||
| 1329 | 0x0000028a, |
||
| 1330 | 0x00000000, |
||
| 1331 | 0xc0016900, |
||
| 1332 | 0x0000028b, |
||
| 1333 | 0x00000000, |
||
| 1334 | 0xc0016900, |
||
| 1335 | 0x0000028c, |
||
| 1336 | 0x00000000, |
||
| 1337 | 0xc0016900, |
||
| 1338 | 0x0000028d, |
||
| 1339 | 0x00000000, |
||
| 1340 | 0xc0016900, |
||
| 1341 | 0x0000028e, |
||
| 1342 | 0x00000000, |
||
| 1343 | 0xc0016900, |
||
| 1344 | 0x0000028f, |
||
| 1345 | 0x00000000, |
||
| 1346 | 0xc0016900, |
||
| 1347 | 0x000002a1, |
||
| 1348 | 0x00000000, |
||
| 1349 | 0xc0016900, |
||
| 1350 | 0x000002a5, |
||
| 1351 | 0x00000000, |
||
| 1352 | 0xc0016900, |
||
| 1353 | 0x000002ac, |
||
| 1354 | 0x00000000, |
||
| 1355 | 0xc0016900, |
||
| 1356 | 0x000002ad, |
||
| 1357 | 0x00000000, |
||
| 1358 | 0xc0016900, |
||
| 1359 | 0x000002ae, |
||
| 1360 | 0x00000000, |
||
| 1361 | 0xc0016900, |
||
| 1362 | 0x000002c8, |
||
| 1363 | 0x00000000, |
||
| 1364 | 0xc0016900, |
||
| 1365 | 0x00000206, |
||
| 1366 | 0x00000100, |
||
| 1367 | 0xc0016900, |
||
| 1368 | 0x00000204, |
||
| 1369 | 0x00010000, |
||
| 1370 | 0xc0036e00, |
||
| 1371 | 0x00000000, |
||
| 1372 | 0x00000012, |
||
| 1373 | 0x00000000, |
||
| 1374 | 0x00000000, |
||
| 1375 | 0xc0016900, |
||
| 1376 | 0x0000008f, |
||
| 1377 | 0x0000000f, |
||
| 1378 | 0xc0016900, |
||
| 1379 | 0x000001e8, |
||
| 1380 | 0x00000001, |
||
| 1381 | 0xc0016900, |
||
| 1382 | 0x00000202, |
||
| 1383 | 0x00cc0000, |
||
| 1384 | 0xc0016900, |
||
| 1385 | 0x00000205, |
||
| 1386 | 0x00000244, |
||
| 1387 | 0xc0016900, |
||
| 1388 | 0x00000203, |
||
| 1389 | 0x00000210, |
||
| 1390 | 0xc0016900, |
||
| 1391 | 0x000001b1, |
||
| 1392 | 0x00000000, |
||
| 1393 | 0xc0016900, |
||
| 1394 | 0x00000185, |
||
| 1395 | 0x00000000, |
||
| 1396 | 0xc0016900, |
||
| 1397 | 0x000001b3, |
||
| 1398 | 0x00000001, |
||
| 1399 | 0xc0016900, |
||
| 1400 | 0x000001b4, |
||
| 1401 | 0x00000000, |
||
| 1402 | 0xc0016900, |
||
| 1403 | 0x00000191, |
||
| 1404 | 0x00000b00, |
||
| 1405 | 0xc0016900, |
||
| 1406 | 0x000001b5, |
||
| 1407 | 0x00000000, |
||
| 1408 | }; |
||
| 1409 | |||
| 1410 | |||
| 1411 | const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); |
||
| 1412 | |||
| 1413 | |||
| 1414 | |||
| 1415 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader); |
||
| 1416 | |||
| 1417 | |||
| 1418 | |||
| 1419 | |||
| 1420 | static void |
||
| 1421 | set_render_target(struct radeon_device *rdev, int format, |
||
| 1422 | int w, int h, u64 gpu_addr) |
||
| 1423 | { |
||
| 1424 | u32 cb_color_info; |
||
| 1425 | int pitch, slice; |
||
| 1426 | |||
| 1427 | |||
| 1428 | if (h < 8) |
||
| 1429 | h = 8; |
||
| 1430 | |||
| 1431 | |||
| 1432 | pitch = (w / 8) - 1; |
||
| 1433 | slice = ((w * h) / 64) - 1; |
||
| 1434 | |||
| 1435 | |||
| 1436 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1437 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
| 1438 | |||
| 1439 | |||
| 1440 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
||
| 1441 | radeon_ring_write(rdev, 2 << 0); |
||
| 1442 | } |
||
| 1443 | |||
| 1444 | |||
| 1445 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1446 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
||
| 1447 | |||
| 1448 | |||
| 1449 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1450 | radeon_ring_write(rdev, 0); |
||
| 1451 | |||
| 1452 | |||
| 1453 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1454 | radeon_ring_write(rdev, cb_color_info); |
||
| 1455 | |||
| 1456 | |||
| 1457 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1458 | radeon_ring_write(rdev, 0); |
||
| 1459 | |||
| 1460 | |||
| 1461 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1462 | radeon_ring_write(rdev, 0); |
||
| 1463 | |||
| 1464 | |||
| 1465 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1466 | radeon_ring_write(rdev, 0); |
||
| 1467 | } |
||
| 1468 | |||
| 1469 | |||
| 1470 | |||
| 1471 | static void |
||
| 1472 | cp_set_surface_sync(struct radeon_device *rdev, |
||
| 1473 | u32 sync_type, u32 size, |
||
| 1474 | u64 mc_addr) |
||
| 1475 | { |
||
| 1476 | u32 cp_coher_size; |
||
| 1477 | |||
| 1478 | |||
| 1479 | cp_coher_size = 0xffffffff; |
||
| 1480 | else |
||
| 1481 | cp_coher_size = ((size + 255) >> 8); |
||
| 1482 | |||
| 1483 | |||
| 1484 | radeon_ring_write(rdev, sync_type); |
||
| 1485 | radeon_ring_write(rdev, cp_coher_size); |
||
| 1486 | radeon_ring_write(rdev, mc_addr >> 8); |
||
| 1487 | radeon_ring_write(rdev, 10); /* poll interval */ |
||
| 1488 | } |
||
| 1489 | |||
| 1490 | |||
| 1491 | static void |
||
| 1492 | set_default_state(struct radeon_device *rdev, |
||
| 1493 | u64 state_gpu_addr, u32 state_len) |
||
| 1494 | { |
||
| 1495 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
||
| 1496 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
||
| 1497 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
||
| 1498 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
||
| 1499 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
||
| 1500 | u64 gpu_addr; |
||
| 1501 | int dwords; |
||
| 1502 | |||
| 1503 | |||
| 1504 | case CHIP_R600: |
||
| 1505 | num_ps_gprs = 192; |
||
| 1506 | num_vs_gprs = 56; |
||
| 1507 | num_temp_gprs = 4; |
||
| 1508 | num_gs_gprs = 0; |
||
| 1509 | num_es_gprs = 0; |
||
| 1510 | num_ps_threads = 136; |
||
| 1511 | num_vs_threads = 48; |
||
| 1512 | num_gs_threads = 4; |
||
| 1513 | num_es_threads = 4; |
||
| 1514 | num_ps_stack_entries = 128; |
||
| 1515 | num_vs_stack_entries = 128; |
||
| 1516 | num_gs_stack_entries = 0; |
||
| 1517 | num_es_stack_entries = 0; |
||
| 1518 | break; |
||
| 1519 | case CHIP_RV630: |
||
| 1520 | case CHIP_RV635: |
||
| 1521 | num_ps_gprs = 84; |
||
| 1522 | num_vs_gprs = 36; |
||
| 1523 | num_temp_gprs = 4; |
||
| 1524 | num_gs_gprs = 0; |
||
| 1525 | num_es_gprs = 0; |
||
| 1526 | num_ps_threads = 144; |
||
| 1527 | num_vs_threads = 40; |
||
| 1528 | num_gs_threads = 4; |
||
| 1529 | num_es_threads = 4; |
||
| 1530 | num_ps_stack_entries = 40; |
||
| 1531 | num_vs_stack_entries = 40; |
||
| 1532 | num_gs_stack_entries = 32; |
||
| 1533 | num_es_stack_entries = 16; |
||
| 1534 | break; |
||
| 1535 | case CHIP_RV610: |
||
| 1536 | case CHIP_RV620: |
||
| 1537 | case CHIP_RS780: |
||
| 1538 | case CHIP_RS880: |
||
| 1539 | default: |
||
| 1540 | num_ps_gprs = 84; |
||
| 1541 | num_vs_gprs = 36; |
||
| 1542 | num_temp_gprs = 4; |
||
| 1543 | num_gs_gprs = 0; |
||
| 1544 | num_es_gprs = 0; |
||
| 1545 | num_ps_threads = 136; |
||
| 1546 | num_vs_threads = 48; |
||
| 1547 | num_gs_threads = 4; |
||
| 1548 | num_es_threads = 4; |
||
| 1549 | num_ps_stack_entries = 40; |
||
| 1550 | num_vs_stack_entries = 40; |
||
| 1551 | num_gs_stack_entries = 32; |
||
| 1552 | num_es_stack_entries = 16; |
||
| 1553 | break; |
||
| 1554 | case CHIP_RV670: |
||
| 1555 | num_ps_gprs = 144; |
||
| 1556 | num_vs_gprs = 40; |
||
| 1557 | num_temp_gprs = 4; |
||
| 1558 | num_gs_gprs = 0; |
||
| 1559 | num_es_gprs = 0; |
||
| 1560 | num_ps_threads = 136; |
||
| 1561 | num_vs_threads = 48; |
||
| 1562 | num_gs_threads = 4; |
||
| 1563 | num_es_threads = 4; |
||
| 1564 | num_ps_stack_entries = 40; |
||
| 1565 | num_vs_stack_entries = 40; |
||
| 1566 | num_gs_stack_entries = 32; |
||
| 1567 | num_es_stack_entries = 16; |
||
| 1568 | break; |
||
| 1569 | case CHIP_RV770: |
||
| 1570 | num_ps_gprs = 192; |
||
| 1571 | num_vs_gprs = 56; |
||
| 1572 | num_temp_gprs = 4; |
||
| 1573 | num_gs_gprs = 0; |
||
| 1574 | num_es_gprs = 0; |
||
| 1575 | num_ps_threads = 188; |
||
| 1576 | num_vs_threads = 60; |
||
| 1577 | num_gs_threads = 0; |
||
| 1578 | num_es_threads = 0; |
||
| 1579 | num_ps_stack_entries = 256; |
||
| 1580 | num_vs_stack_entries = 256; |
||
| 1581 | num_gs_stack_entries = 0; |
||
| 1582 | num_es_stack_entries = 0; |
||
| 1583 | break; |
||
| 1584 | case CHIP_RV730: |
||
| 1585 | case CHIP_RV740: |
||
| 1586 | num_ps_gprs = 84; |
||
| 1587 | num_vs_gprs = 36; |
||
| 1588 | num_temp_gprs = 4; |
||
| 1589 | num_gs_gprs = 0; |
||
| 1590 | num_es_gprs = 0; |
||
| 1591 | num_ps_threads = 188; |
||
| 1592 | num_vs_threads = 60; |
||
| 1593 | num_gs_threads = 0; |
||
| 1594 | num_es_threads = 0; |
||
| 1595 | num_ps_stack_entries = 128; |
||
| 1596 | num_vs_stack_entries = 128; |
||
| 1597 | num_gs_stack_entries = 0; |
||
| 1598 | num_es_stack_entries = 0; |
||
| 1599 | break; |
||
| 1600 | case CHIP_RV710: |
||
| 1601 | num_ps_gprs = 192; |
||
| 1602 | num_vs_gprs = 56; |
||
| 1603 | num_temp_gprs = 4; |
||
| 1604 | num_gs_gprs = 0; |
||
| 1605 | num_es_gprs = 0; |
||
| 1606 | num_ps_threads = 144; |
||
| 1607 | num_vs_threads = 48; |
||
| 1608 | num_gs_threads = 0; |
||
| 1609 | num_es_threads = 0; |
||
| 1610 | num_ps_stack_entries = 128; |
||
| 1611 | num_vs_stack_entries = 128; |
||
| 1612 | num_gs_stack_entries = 0; |
||
| 1613 | num_es_stack_entries = 0; |
||
| 1614 | break; |
||
| 1615 | } |
||
| 1616 | |||
| 1617 | |||
| 1618 | (rdev->family == CHIP_RV620) || |
||
| 1619 | (rdev->family == CHIP_RS780) || |
||
| 1620 | (rdev->family == CHIP_RS880) || |
||
| 1621 | (rdev->family == CHIP_RV710)) |
||
| 1622 | sq_config = 0; |
||
| 1623 | else |
||
| 1624 | sq_config = VC_ENABLE; |
||
| 1625 | |||
| 1626 | |||
| 1627 | ALU_INST_PREFER_VECTOR | |
||
| 1628 | PS_PRIO(0) | |
||
| 1629 | VS_PRIO(1) | |
||
| 1630 | GS_PRIO(2) | |
||
| 1631 | ES_PRIO(3)); |
||
| 1632 | |||
| 1633 | |||
| 1634 | NUM_VS_GPRS(num_vs_gprs) | |
||
| 1635 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
||
| 1636 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
||
| 1637 | NUM_ES_GPRS(num_es_gprs)); |
||
| 1638 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
||
| 1639 | NUM_VS_THREADS(num_vs_threads) | |
||
| 1640 | NUM_GS_THREADS(num_gs_threads) | |
||
| 1641 | NUM_ES_THREADS(num_es_threads)); |
||
| 1642 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
||
| 1643 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
||
| 1644 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
||
| 1645 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
||
| 1646 | |||
| 1647 | |||
| 1648 | dwords = (state_len + 0xf) & ~0xf; |
||
| 1649 | gpu_addr = state_gpu_addr; |
||
| 1650 | |||
| 1651 | |||
| 1652 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
||
| 1653 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
||
| 1654 | radeon_ring_write(rdev, dwords); |
||
| 1655 | |||
| 1656 | |||
| 1657 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
||
| 1658 | /* SQ config */ |
||
| 1659 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
||
| 1660 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
| 1661 | radeon_ring_write(rdev, sq_config); |
||
| 1662 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
||
| 1663 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
||
| 1664 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
||
| 1665 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
||
| 1666 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
||
| 1667 | } |
||
| 1668 | |||
| 1669 | |||
| 1670 | static void |
||
| 1671 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
||
| 1672 | int x2, int y2) |
||
| 1673 | { |
||
| 1674 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
||
| 1675 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1676 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
||
| 1677 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
| 1678 | |||
| 1679 | |||
| 1680 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1681 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
||
| 1682 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
| 1683 | |||
| 1684 | |||
| 1685 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 1686 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
||
| 1687 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
| 1688 | } |
||
| 1689 | |||
| 1690 | |||
| 1691 | draw_auto(struct radeon_device *rdev) |
||
| 1692 | { |
||
| 1693 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
| 1694 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
| 1695 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
||
| 1696 | |||
| 1697 | |||
| 1698 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); |
||
| 1699 | |||
| 1700 | |||
| 1701 | radeon_ring_write(rdev, 1); |
||
| 1702 | |||
| 1703 | |||
| 1704 | radeon_ring_write(rdev, 3); |
||
| 1705 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
||
| 1706 | |||
| 1707 | |||
| 1708 | |||
| 1709 | |||
| 1710 | #define SRC0_SEL(x) (x) |
||
| 1711 | #define SRC1_SEL(x) (x) |
||
| 1712 | #define SRC2_SEL(x) (x) |
||
| 1713 | /* src[0-2]_sel */ |
||
| 1714 | /* 0-127 GPR */ |
||
| 1715 | /* 128-159 kcache constants bank 0 */ |
||
| 1716 | /* 160-191 kcache constants bank 1 */ |
||
| 1717 | /* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */ |
||
| 1718 | |||
| 1719 | |||
| 1720 | #define SRC1_REL(x) (x) |
||
| 1721 | #define SRC2_REL(x) (x) |
||
| 1722 | /* elem */ |
||
| 1723 | #define SRC0_ELEM(x) (x) |
||
| 1724 | #define SRC1_ELEM(x) (x) |
||
| 1725 | #define SRC2_ELEM(x) (x) |
||
| 1726 | #define ELEM_X 0 |
||
| 1727 | #define ELEM_Y 1 |
||
| 1728 | #define ELEM_Z 2 |
||
| 1729 | #define ELEM_W 3 |
||
| 1730 | /* neg */ |
||
| 1731 | #define SRC0_NEG(x) (x) |
||
| 1732 | #define SRC1_NEG(x) (x) |
||
| 1733 | #define SRC2_NEG(x) (x) |
||
| 1734 | /* im */ |
||
| 1735 | #define INDEX_MODE(x) (x) /* SQ_INDEX_* */ |
||
| 1736 | /* ps */ |
||
| 1737 | #define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */ |
||
| 1738 | /* last */ |
||
| 1739 | #define LAST(x) (x) |
||
| 1740 | /* abs */ |
||
| 1741 | #define SRC0_ABS(x) (x) |
||
| 1742 | #define SRC1_ABS(x) (x) |
||
| 1743 | /* uem */ |
||
| 1744 | #define UPDATE_EXECUTE_MASK(x) (x) |
||
| 1745 | /* up */ |
||
| 1746 | #define UPDATE_PRED(x) (x) |
||
| 1747 | /* wm */ |
||
| 1748 | #define WRITE_MASK(x) (x) |
||
| 1749 | /* fm */ |
||
| 1750 | #define FOG_MERGE(x) (x) |
||
| 1751 | /* omod */ |
||
| 1752 | #define OMOD(x) (x) /* SQ_ALU_OMOD_* */ |
||
| 1753 | /* alu inst */ |
||
| 1754 | #define ALU_INST(x) (x) /* SQ_ALU_INST_* */ |
||
| 1755 | /*bs */ |
||
| 1756 | #define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */ |
||
| 1757 | #define DST_GPR(x) (x) |
||
| 1758 | #define DST_REL(x) (x) |
||
| 1759 | #define DST_ELEM(x) (x) |
||
| 1760 | #define CLAMP(x) (x) |
||
| 1761 | |||
| 1762 | |||
| 1763 | (((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ |
||
| 1764 | ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ |
||
| 1765 | ((im) << 26) | ((ps) << 29) | ((last) << 31)) |
||
| 1766 | |||
| 1767 | |||
| 1768 | #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
||
| 1769 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
||
| 1770 | ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
||
| 1771 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
||
| 1772 | |||
| 1773 | |||
| 1774 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
||
| 1775 | ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
||
| 1776 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
||
| 1777 | |||
| 1778 | |||
| 1779 | /* Fog is NOT USED on R7xx, even if specified. */ |
||
| 1780 | #define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
||
| 1781 | ((chipid) < CHIP_RV770 ? \ |
||
| 1782 | R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ |
||
| 1783 | R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) |
||
| 1784 | |||
| 1785 | |||
| 1786 | (((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ |
||
| 1787 | ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ |
||
| 1788 | ((de) << 29) | ((clamp) << 31)) |
||
| 1789 | |||
| 1790 | |||
| 1791 | /* addr */ |
||
| 1792 | #define ADDR(x) (x) |
||
| 1793 | /* pc */ |
||
| 1794 | #define POP_COUNT(x) (x) |
||
| 1795 | /* const */ |
||
| 1796 | #define CF_CONST(x) (x) |
||
| 1797 | /* cond */ |
||
| 1798 | #define COND(x) (x) /* SQ_COND_* */ |
||
| 1799 | /* count */ |
||
| 1800 | #define I_COUNT(x) ((x) ? ((x) - 1) : 0) |
||
| 1801 | /*r7xx */ |
||
| 1802 | #define COUNT_3(x) (x) |
||
| 1803 | /* call count */ |
||
| 1804 | #define CALL_COUNT(x) (x) |
||
| 1805 | /* eop */ |
||
| 1806 | #define END_OF_PROGRAM(x) (x) |
||
| 1807 | /* vpm */ |
||
| 1808 | #define VALID_PIXEL_MODE(x) (x) |
||
| 1809 | /* cf inst */ |
||
| 1810 | #define CF_INST(x) (x) /* SQ_CF_INST_* */ |
||
| 1811 | |||
| 1812 | |||
| 1813 | #define WHOLE_QUAD_MODE(x) (x) |
||
| 1814 | /* barrier */ |
||
| 1815 | #define BARRIER(x) (x) |
||
| 1816 | /*kb0 */ |
||
| 1817 | #define KCACHE_BANK0(x) (x) |
||
| 1818 | /*kb1 */ |
||
| 1819 | #define KCACHE_BANK1(x) (x) |
||
| 1820 | /* km0/1 */ |
||
| 1821 | #define KCACHE_MODE0(x) (x) |
||
| 1822 | #define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */ |
||
| 1823 | /* */ |
||
| 1824 | #define KCACHE_ADDR0(x) (x) |
||
| 1825 | #define KCACHE_ADDR1(x) (x) |
||
| 1826 | /* uw */ |
||
| 1827 | #define USES_WATERFALL(x) (x) |
||
| 1828 | |||
| 1829 | |||
| 1830 | /* export pixel */ |
||
| 1831 | #define CF_PIXEL_MRT0 0 |
||
| 1832 | #define CF_PIXEL_MRT1 1 |
||
| 1833 | #define CF_PIXEL_MRT2 2 |
||
| 1834 | #define CF_PIXEL_MRT3 3 |
||
| 1835 | #define CF_PIXEL_MRT4 4 |
||
| 1836 | #define CF_PIXEL_MRT5 5 |
||
| 1837 | #define CF_PIXEL_MRT6 6 |
||
| 1838 | #define CF_PIXEL_MRT7 7 |
||
| 1839 | /* *_FOG: r6xx only */ |
||
| 1840 | #define CF_PIXEL_MRT0_FOG 16 |
||
| 1841 | #define CF_PIXEL_MRT1_FOG 17 |
||
| 1842 | #define CF_PIXEL_MRT2_FOG 18 |
||
| 1843 | #define CF_PIXEL_MRT3_FOG 19 |
||
| 1844 | #define CF_PIXEL_MRT4_FOG 20 |
||
| 1845 | #define CF_PIXEL_MRT5_FOG 21 |
||
| 1846 | #define CF_PIXEL_MRT6_FOG 22 |
||
| 1847 | #define CF_PIXEL_MRT7_FOG 23 |
||
| 1848 | #define CF_PIXEL_Z 61 |
||
| 1849 | /* export pos */ |
||
| 1850 | #define CF_POS0 60 |
||
| 1851 | #define CF_POS1 61 |
||
| 1852 | #define CF_POS2 62 |
||
| 1853 | #define CF_POS3 63 |
||
| 1854 | /* export param */ |
||
| 1855 | /* 0...31 */ |
||
| 1856 | #define TYPE(x) (x) /* SQ_EXPORT_* */ |
||
| 1857 | #if 0 |
||
| 1858 | /* type export */ |
||
| 1859 | #define SQ_EXPORT_PIXEL 0 |
||
| 1860 | #define SQ_EXPORT_POS 1 |
||
| 1861 | #define SQ_EXPORT_PARAM 2 |
||
| 1862 | /* reserved 3 */ |
||
| 1863 | /* type mem */ |
||
| 1864 | #define SQ_EXPORT_WRITE 0 |
||
| 1865 | #define SQ_EXPORT_WRITE_IND 1 |
||
| 1866 | #define SQ_EXPORT_WRITE_ACK 2 |
||
| 1867 | #define SQ_EXPORT_WRITE_IND_ACK 3 |
||
| 1868 | #endif |
||
| 1869 | |||
| 1870 | |||
| 1871 | #define RW_REL(x) (x) |
||
| 1872 | #define ABSOLUTE 0 |
||
| 1873 | #define RELATIVE 1 |
||
| 1874 | #define INDEX_GPR(x) (x) |
||
| 1875 | #define ELEM_SIZE(x) (x ? (x - 1) : 0) |
||
| 1876 | #define COMP_MASK(x) (x) |
||
| 1877 | #define R6xx_ELEM_LOOP(x) (x) |
||
| 1878 | #define BURST_COUNT(x) (x ? (x - 1) : 0) |
||
| 1879 | |||
| 1880 | |||
| 1881 | #define SRC_SEL_X(x) (x) /* SQ_SEL_* each */ |
||
| 1882 | #define SRC_SEL_Y(x) (x) |
||
| 1883 | #define SRC_SEL_Z(x) (x) |
||
| 1884 | #define SRC_SEL_W(x) (x) |
||
| 1885 | |||
| 1886 | |||
| 1887 | /* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */ |
||
| 1888 | /* We allow one more bit for count in the argument of the macro on R7xx instead. */ |
||
| 1889 | /* R6xx: [0,7] R7xx: [1,16] */ |
||
| 1890 | #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ |
||
| 1891 | (((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ |
||
| 1892 | ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
||
| 1893 | |||
| 1894 | |||
| 1895 | #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ |
||
| 1896 | (((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ |
||
| 1897 | ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)) |
||
| 1898 | |||
| 1899 | |||
| 1900 | (((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ |
||
| 1901 | ((es) << 30)) |
||
| 1902 | /* R7xx apparently doesn't have the ELEM_LOOP entry any more */ |
||
| 1903 | /* We still expose it, but ELEM_LOOP is explicitely R6xx now. */ |
||
| 1904 | /* TODO: is this just forgotten in the docs, or really not available any more? */ |
||
| 1905 | #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ |
||
| 1906 | (((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ |
||
| 1907 | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
||
| 1908 | #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ |
||
| 1909 | (((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ |
||
| 1910 | ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ |
||
| 1911 | ((wqm) << 30) | ((b) << 31)) |
||
| 1912 | |||
| 1913 | |||
| 1914 | /* vxt insts */ |
||
| 1915 | #define VTX_INST(x) (x) /* SQ_VTX_INST_* */ |
||
| 1916 | |||
| 1917 | |||
| 1918 | #define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */ |
||
| 1919 | |||
| 1920 | |||
| 1921 | #define BUFFER_ID(x) (x) |
||
| 1922 | #define SRC_GPR(x) (x) |
||
| 1923 | #define SRC_REL(x) (x) |
||
| 1924 | #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) |
||
| 1925 | |||
| 1926 | |||
| 1927 | #define DST_SEL_X(x) (x) |
||
| 1928 | #define DST_SEL_Y(x) (x) |
||
| 1929 | #define DST_SEL_Z(x) (x) |
||
| 1930 | #define DST_SEL_W(x) (x) |
||
| 1931 | #define USE_CONST_FIELDS(x) (x) |
||
| 1932 | #define DATA_FORMAT(x) (x) |
||
| 1933 | /* num format */ |
||
| 1934 | #define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */ |
||
| 1935 | /* format comp */ |
||
| 1936 | #define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */ |
||
| 1937 | /* sma */ |
||
| 1938 | #define SRF_MODE_ALL(x) (x) |
||
| 1939 | #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 |
||
| 1940 | #define SRF_MODE_NO_ZERO 1 |
||
| 1941 | #define OFFSET(x) (x) |
||
| 1942 | /* endian swap */ |
||
| 1943 | #define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */ |
||
| 1944 | #define CONST_BUF_NO_STRIDE(x) (x) |
||
| 1945 | /* mf */ |
||
| 1946 | #define MEGA_FETCH(x) (x) |
||
| 1947 | |||
| 1948 | |||
| 1949 | (((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ |
||
| 1950 | ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)) |
||
| 1951 | #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
||
| 1952 | (((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
||
| 1953 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
||
| 1954 | #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
||
| 1955 | (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
||
| 1956 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
||
| 1957 | #define VTX_DWORD2(offset, es, cbns, mf) \ |
||
| 1958 | (((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)) |
||
| 1959 | #define VTX_DWORD_PAD 0x00000000 |
||
| 1960 | |||
| 1961 | |||
| 1962 | |||
| 1963 | { |
||
| 1964 | int i=0; |
||
| 1965 | |||
| 1966 | |||
| 1967 | shader[i++] = CF_DWORD0(ADDR(4)); |
||
| 1968 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
||
| 1969 | CF_CONST(0), |
||
| 1970 | COND(SQ_CF_COND_ACTIVE), |
||
| 1971 | I_COUNT(1), |
||
| 1972 | CALL_COUNT(0), |
||
| 1973 | END_OF_PROGRAM(0), |
||
| 1974 | VALID_PIXEL_MODE(0), |
||
| 1975 | CF_INST(SQ_CF_INST_VTX), |
||
| 1976 | WHOLE_QUAD_MODE(0), |
||
| 1977 | BARRIER(1)); |
||
| 1978 | /* 1 */ |
||
| 1979 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), |
||
| 1980 | TYPE(SQ_EXPORT_POS), |
||
| 1981 | RW_GPR(1), |
||
| 1982 | RW_REL(ABSOLUTE), |
||
| 1983 | INDEX_GPR(0), |
||
| 1984 | ELEM_SIZE(0)); |
||
| 1985 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
| 1986 | SRC_SEL_Y(SQ_SEL_Y), |
||
| 1987 | SRC_SEL_Z(SQ_SEL_Z), |
||
| 1988 | SRC_SEL_W(SQ_SEL_W), |
||
| 1989 | R6xx_ELEM_LOOP(0), |
||
| 1990 | BURST_COUNT(1), |
||
| 1991 | END_OF_PROGRAM(0), |
||
| 1992 | VALID_PIXEL_MODE(0), |
||
| 1993 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
| 1994 | WHOLE_QUAD_MODE(0), |
||
| 1995 | BARRIER(1)); |
||
| 1996 | /* 2 - always export a param whether it's used or not */ |
||
| 1997 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), |
||
| 1998 | TYPE(SQ_EXPORT_PARAM), |
||
| 1999 | RW_GPR(0), |
||
| 2000 | RW_REL(ABSOLUTE), |
||
| 2001 | INDEX_GPR(0), |
||
| 2002 | ELEM_SIZE(0)); |
||
| 2003 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
| 2004 | SRC_SEL_Y(SQ_SEL_Y), |
||
| 2005 | SRC_SEL_Z(SQ_SEL_Z), |
||
| 2006 | SRC_SEL_W(SQ_SEL_W), |
||
| 2007 | R6xx_ELEM_LOOP(0), |
||
| 2008 | BURST_COUNT(0), |
||
| 2009 | END_OF_PROGRAM(1), |
||
| 2010 | VALID_PIXEL_MODE(0), |
||
| 2011 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
| 2012 | WHOLE_QUAD_MODE(0), |
||
| 2013 | BARRIER(0)); |
||
| 2014 | /* 3 - padding */ |
||
| 2015 | shader[i++] = 0x00000000; |
||
| 2016 | shader[i++] = 0x00000000; |
||
| 2017 | /* 4/5 */ |
||
| 2018 | shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), |
||
| 2019 | FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), |
||
| 2020 | FETCH_WHOLE_QUAD(0), |
||
| 2021 | BUFFER_ID(0), |
||
| 2022 | SRC_GPR(0), |
||
| 2023 | SRC_REL(ABSOLUTE), |
||
| 2024 | SRC_SEL_X(SQ_SEL_X), |
||
| 2025 | MEGA_FETCH_COUNT(8)); |
||
| 2026 | shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), |
||
| 2027 | DST_REL(0), |
||
| 2028 | DST_SEL_X(SQ_SEL_X), |
||
| 2029 | DST_SEL_Y(SQ_SEL_Y), |
||
| 2030 | DST_SEL_Z(SQ_SEL_0), |
||
| 2031 | DST_SEL_W(SQ_SEL_1), |
||
| 2032 | USE_CONST_FIELDS(0), |
||
| 2033 | DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ |
||
| 2034 | NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ |
||
| 2035 | FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ |
||
| 2036 | SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); |
||
| 2037 | shader[i++] = VTX_DWORD2(OFFSET(0), |
||
| 2038 | ENDIAN_SWAP(ENDIAN_NONE), |
||
| 2039 | CONST_BUF_NO_STRIDE(0), |
||
| 2040 | MEGA_FETCH(1)); |
||
| 2041 | shader[i++] = VTX_DWORD_PAD; |
||
| 2042 | |||
| 2043 | |||
| 2044 | } |
||
| 2045 | |||
| 2046 | |||
| 2047 | { |
||
| 2048 | int i=0; |
||
| 2049 | |||
| 2050 | |||
| 2051 | shader[i++] = CF_ALU_DWORD0(ADDR(2), |
||
| 2052 | KCACHE_BANK0(0), |
||
| 2053 | KCACHE_BANK1(0), |
||
| 2054 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); |
||
| 2055 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), |
||
| 2056 | KCACHE_ADDR0(0), |
||
| 2057 | KCACHE_ADDR1(0), |
||
| 2058 | I_COUNT(4), |
||
| 2059 | USES_WATERFALL(0), |
||
| 2060 | CF_INST(SQ_CF_INST_ALU), |
||
| 2061 | WHOLE_QUAD_MODE(0), |
||
| 2062 | BARRIER(1)); |
||
| 2063 | /* 1 */ |
||
| 2064 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
||
| 2065 | TYPE(SQ_EXPORT_PIXEL), |
||
| 2066 | RW_GPR(0), |
||
| 2067 | RW_REL(ABSOLUTE), |
||
| 2068 | INDEX_GPR(0), |
||
| 2069 | ELEM_SIZE(1)); |
||
| 2070 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
| 2071 | SRC_SEL_Y(SQ_SEL_Y), |
||
| 2072 | SRC_SEL_Z(SQ_SEL_Z), |
||
| 2073 | SRC_SEL_W(SQ_SEL_W), |
||
| 2074 | R6xx_ELEM_LOOP(0), |
||
| 2075 | BURST_COUNT(1), |
||
| 2076 | END_OF_PROGRAM(1), |
||
| 2077 | VALID_PIXEL_MODE(0), |
||
| 2078 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
| 2079 | WHOLE_QUAD_MODE(0), |
||
| 2080 | BARRIER(1)); |
||
| 2081 | |||
| 2082 | |||
| 2083 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
| 2084 | SRC0_REL(ABSOLUTE), |
||
| 2085 | SRC0_ELEM(ELEM_X), |
||
| 2086 | SRC0_NEG(0), |
||
| 2087 | SRC1_SEL(0), |
||
| 2088 | SRC1_REL(ABSOLUTE), |
||
| 2089 | SRC1_ELEM(ELEM_X), |
||
| 2090 | SRC1_NEG(0), |
||
| 2091 | INDEX_MODE(SQ_INDEX_AR_X), |
||
| 2092 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
| 2093 | LAST(0)); |
||
| 2094 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
| 2095 | SRC0_ABS(0), |
||
| 2096 | SRC1_ABS(0), |
||
| 2097 | UPDATE_EXECUTE_MASK(0), |
||
| 2098 | UPDATE_PRED(0), |
||
| 2099 | WRITE_MASK(1), |
||
| 2100 | FOG_MERGE(0), |
||
| 2101 | OMOD(SQ_ALU_OMOD_OFF), |
||
| 2102 | ALU_INST(SQ_OP2_INST_MOV), |
||
| 2103 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
| 2104 | DST_GPR(0), |
||
| 2105 | DST_REL(ABSOLUTE), |
||
| 2106 | DST_ELEM(ELEM_X), |
||
| 2107 | CLAMP(1)); |
||
| 2108 | /* 3 */ |
||
| 2109 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
| 2110 | SRC0_REL(ABSOLUTE), |
||
| 2111 | SRC0_ELEM(ELEM_Y), |
||
| 2112 | SRC0_NEG(0), |
||
| 2113 | SRC1_SEL(0), |
||
| 2114 | SRC1_REL(ABSOLUTE), |
||
| 2115 | SRC1_ELEM(ELEM_Y), |
||
| 2116 | SRC1_NEG(0), |
||
| 2117 | INDEX_MODE(SQ_INDEX_AR_X), |
||
| 2118 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
| 2119 | LAST(0)); |
||
| 2120 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
| 2121 | SRC0_ABS(0), |
||
| 2122 | SRC1_ABS(0), |
||
| 2123 | UPDATE_EXECUTE_MASK(0), |
||
| 2124 | UPDATE_PRED(0), |
||
| 2125 | WRITE_MASK(1), |
||
| 2126 | FOG_MERGE(0), |
||
| 2127 | OMOD(SQ_ALU_OMOD_OFF), |
||
| 2128 | ALU_INST(SQ_OP2_INST_MOV), |
||
| 2129 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
| 2130 | DST_GPR(0), |
||
| 2131 | DST_REL(ABSOLUTE), |
||
| 2132 | DST_ELEM(ELEM_Y), |
||
| 2133 | CLAMP(1)); |
||
| 2134 | /* 4 */ |
||
| 2135 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
| 2136 | SRC0_REL(ABSOLUTE), |
||
| 2137 | SRC0_ELEM(ELEM_Z), |
||
| 2138 | SRC0_NEG(0), |
||
| 2139 | SRC1_SEL(0), |
||
| 2140 | SRC1_REL(ABSOLUTE), |
||
| 2141 | SRC1_ELEM(ELEM_Z), |
||
| 2142 | SRC1_NEG(0), |
||
| 2143 | INDEX_MODE(SQ_INDEX_AR_X), |
||
| 2144 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
| 2145 | LAST(0)); |
||
| 2146 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
| 2147 | SRC0_ABS(0), |
||
| 2148 | SRC1_ABS(0), |
||
| 2149 | UPDATE_EXECUTE_MASK(0), |
||
| 2150 | UPDATE_PRED(0), |
||
| 2151 | WRITE_MASK(1), |
||
| 2152 | FOG_MERGE(0), |
||
| 2153 | OMOD(SQ_ALU_OMOD_OFF), |
||
| 2154 | ALU_INST(SQ_OP2_INST_MOV), |
||
| 2155 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
| 2156 | DST_GPR(0), |
||
| 2157 | DST_REL(ABSOLUTE), |
||
| 2158 | DST_ELEM(ELEM_Z), |
||
| 2159 | CLAMP(1)); |
||
| 2160 | /* 5 */ |
||
| 2161 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
| 2162 | SRC0_REL(ABSOLUTE), |
||
| 2163 | SRC0_ELEM(ELEM_W), |
||
| 2164 | SRC0_NEG(0), |
||
| 2165 | SRC1_SEL(0), |
||
| 2166 | SRC1_REL(ABSOLUTE), |
||
| 2167 | SRC1_ELEM(ELEM_W), |
||
| 2168 | SRC1_NEG(0), |
||
| 2169 | INDEX_MODE(SQ_INDEX_AR_X), |
||
| 2170 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
| 2171 | LAST(1)); |
||
| 2172 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
| 2173 | SRC0_ABS(0), |
||
| 2174 | SRC1_ABS(0), |
||
| 2175 | UPDATE_EXECUTE_MASK(0), |
||
| 2176 | UPDATE_PRED(0), |
||
| 2177 | WRITE_MASK(1), |
||
| 2178 | FOG_MERGE(0), |
||
| 2179 | OMOD(SQ_ALU_OMOD_OFF), |
||
| 2180 | ALU_INST(SQ_OP2_INST_MOV), |
||
| 2181 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
| 2182 | DST_GPR(0), |
||
| 2183 | DST_REL(ABSOLUTE), |
||
| 2184 | DST_ELEM(ELEM_W), |
||
| 2185 | CLAMP(1)); |
||
| 2186 | |||
| 2187 | |||
| 2188 | } |
||
| 2189 | |||
| 2190 | |||
| 2191 | memcpy_toio(volatile void __iomem *dst, const void *src, int count) |
||
| 2192 | { |
||
| 2193 | __memcpy((void __force *)dst, src, count); |
||
| 2194 | } |
||
| 2195 | |||
| 2196 | |||
| 2197 | do { \ |
||
| 2198 | union { float f; uint32_t d; } a; \ |
||
| 2199 | a.f = (val); \ |
||
| 2200 | radeon_ring_write(rdev, a.d); \ |
||
| 2201 | } while (0) |
||
| 2202 | |||
| 2203 | |||
| 2204 | { |
||
| 2205 | uint32_t ps_shader[16]; |
||
| 2206 | uint32_t vs_shader[16]; |
||
| 2207 | |||
| 2208 | |||
| 2209 | int num_packet2s = 0; |
||
| 2210 | |||
| 2211 | |||
| 2212 | uint32_t offset; |
||
| 2213 | |||
| 2214 | |||
| 2215 | int dwords; |
||
| 2216 | u32 obj_size; |
||
| 2217 | |||
| 2218 | |||
| 2219 | u64 state_gpu_addr = 0; |
||
| 2220 | |||
| 2221 | |||
| 2222 | u32 ps_offset; |
||
| 2223 | u32 vb_offset; |
||
| 2224 | |||
| 2225 | |||
| 2226 | int ps_size; |
||
| 2227 | |||
| 2228 | |||
| 2229 | void *ptr; |
||
| 2230 | |||
| 2231 | |||
| 2232 | |||
| 2233 | |||
| 2234 | |||
| 2235 | |||
| 2236 | |||
| 2237 | |||
| 2238 | offset = rdev->mc.vram_start; |
||
| 1430 | serge | 2239 | ps_size = R600_solid_ps(rdev, ps_shader); |
| 1428 | serge | 2240 | vs_size = R600_solid_vs(rdev, vs_shader); |
| 2241 | |||
| 2242 | |||
| 2243 | state_len = r7xx_default_size; |
||
| 2244 | else |
||
| 2245 | state_len = r6xx_default_size; |
||
| 2246 | |||
| 2247 | |||
| 2248 | |||
| 2249 | |||
| 2250 | packet2s[num_packet2s++] = PACKET2(0); |
||
| 2251 | dwords++; |
||
| 2252 | } |
||
| 2253 | |||
| 2254 | |||
| 2255 | obj_size = ALIGN(obj_size, 256); |
||
| 2256 | |||
| 2257 | |||
| 2258 | obj_size += vs_size * 4; |
||
| 2259 | obj_size = ALIGN(obj_size, 256); |
||
| 2260 | |||
| 2261 | |||
| 2262 | obj_size += ps_size * 4; |
||
| 2263 | obj_size = ALIGN(obj_size, 256); |
||
| 2264 | |||
| 2265 | |||
| 2266 | obj_size += 32*4; |
||
| 2267 | obj_size = ALIGN(obj_size, 256); |
||
| 2268 | |||
| 2269 | |||
| 1963 | serge | 2270 | RADEON_GEM_DOMAIN_VRAM, &state_obj); |
| 2271 | if (r) { |
||
| 1428 | serge | 2272 | DRM_ERROR("r600 failed to allocate state buffer\n"); |
| 2273 | return r; |
||
| 2274 | } |
||
| 2275 | |||
| 2276 | |||
| 2277 | obj_size, vs_offset, ps_offset); |
||
| 2278 | |||
| 2279 | |||
| 2280 | &state_gpu_addr); |
||
| 2281 | if (r) { |
||
| 2282 | DRM_ERROR("failed to pin state object %d\n", r); |
||
| 2283 | return r; |
||
| 2284 | }; |
||
| 2285 | |||
| 2286 | |||
| 2287 | if (r) { |
||
| 2288 | DRM_ERROR("failed to map state object %d\n", r); |
||
| 2289 | return r; |
||
| 2290 | }; |
||
| 2291 | |||
| 2292 | |||
| 2293 | memcpy_toio(ptr + state_offset, |
||
| 2294 | r7xx_default_state, state_len * 4); |
||
| 2295 | else |
||
| 2296 | memcpy_toio(ptr + state_offset, |
||
| 2297 | r6xx_default_state, state_len * 4); |
||
| 2298 | |||
| 2299 | |||
| 2300 | memcpy_toio(ptr + state_offset + (state_len * 4), |
||
| 2301 | packet2s, num_packet2s * 4); |
||
| 2302 | |||
| 2303 | |||
| 2304 | memcpy(ptr + ps_offset, ps_shader, ps_size * 4); |
||
| 2305 | |||
| 2306 | |||
| 2307 | |||
| 2308 | |||
| 2309 | |||
| 2310 | vb[1] = (float)64; |
||
| 2311 | |||
| 2312 | |||
| 2313 | vb[3] = (float)(64+128); |
||
| 2314 | |||
| 2315 | |||
| 2316 | vb[5] = (float)(64+128); |
||
| 2317 | |||
| 2318 | |||
| 2319 | int vb_size = vb_index * 8; |
||
| 2320 | int vtx_num_entries = vb_size / 4; |
||
| 2321 | |||
| 2322 | |||
| 2323 | |||
| 2324 | |||
| 2325 | if (r) { |
||
| 2326 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
| 2327 | return r; |
||
| 2328 | } |
||
| 2329 | |||
| 2330 | |||
| 2331 | |||
| 2332 | |||
| 2333 | |||
| 2334 | u32 sq_pgm_resources; |
||
| 2335 | |||
| 2336 | |||
| 2337 | |||
| 2338 | |||
| 2339 | |||
| 2340 | |||
| 2341 | gpu_addr = state_gpu_addr + vs_offset; |
||
| 2342 | |||
| 2343 | |||
| 2344 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2345 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
| 2346 | |||
| 2347 | |||
| 2348 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2349 | radeon_ring_write(rdev, sq_pgm_resources); |
||
| 2350 | |||
| 2351 | |||
| 2352 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2353 | radeon_ring_write(rdev, 0); |
||
| 2354 | |||
| 2355 | |||
| 2356 | |||
| 2357 | |||
| 2358 | gpu_addr = state_gpu_addr + ps_offset; |
||
| 2359 | |||
| 2360 | |||
| 2361 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2362 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
| 2363 | |||
| 2364 | |||
| 2365 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2366 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
||
| 2367 | |||
| 2368 | |||
| 2369 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2370 | radeon_ring_write(rdev, 2); |
||
| 2371 | |||
| 2372 | |||
| 2373 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
| 2374 | radeon_ring_write(rdev, 0); |
||
| 2375 | |||
| 2376 | |||
| 2377 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
||
| 2378 | |||
| 2379 | |||
| 2380 | |||
| 2381 | rdev->mc.vram_start); |
||
| 1430 | serge | 2382 | |
| 1428 | serge | 2383 | |
| 2384 | |||
| 2385 | |||
| 2386 | |||
| 2387 | radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2); |
||
| 2388 | EFLOAT(0.0f); /* r */ |
||
| 2389 | EFLOAT(1.0f); /* g */ |
||
| 2390 | EFLOAT(0.0f); /* b */ |
||
| 2391 | EFLOAT(1.0f); /* a */ |
||
| 2392 | |||
| 2393 | |||
| 2394 | |||
| 2395 | |||
| 2396 | |||
| 2397 | |||
| 2398 | |||
| 2399 | |||
| 2400 | radeon_ring_write(rdev, 0x460); |
||
| 2401 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */ |
||
| 2402 | radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */ |
||
| 2403 | radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */ |
||
| 2404 | radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */ |
||
| 2405 | radeon_ring_write(rdev, 0); |
||
| 2406 | radeon_ring_write(rdev, 0); |
||
| 2407 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
||
| 2408 | |||
| 2409 | |||
| 2410 | (rdev->family == CHIP_RV620) || |
||
| 2411 | (rdev->family == CHIP_RS780) || |
||
| 2412 | (rdev->family == CHIP_RS880) || |
||
| 2413 | (rdev->family == CHIP_RV710)) |
||
| 2414 | cp_set_surface_sync(rdev, |
||
| 2415 | PACKET3_TC_ACTION_ENA, 24, gpu_addr); |
||
| 2416 | else |
||
| 2417 | cp_set_surface_sync(rdev, |
||
| 2418 | PACKET3_VC_ACTION_ENA, 24, gpu_addr); |
||
| 2419 | |||
| 2420 | |||
| 2421 | |||
| 2422 | |||
| 2423 | 1024*4*512, offset); |
||
| 2424 | |||
| 2425 | |||
| 2426 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
||
| 2427 | /* wait for 3D idle clean */ |
||
| 2428 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
| 2429 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
| 2430 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
||
| 2431 | |||
| 2432 | |||
| 2433 | |||
| 2434 | |||
| 2435 | |||
| 2436 | |||
| 2437 | return r; |
||
| 2438 | } |
||
| 2439 | |||
| 1963 | serge | 2440 | |
| 2441 |