Rev 1877 | Rev 2004 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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1221 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include "radeon_drm.h" |
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5 | #include "radeon.h" |
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6 | #include "radeon_object.h" |
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7 | #include "display.h" |
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1246 | serge | 8 | |
1221 | serge | 9 | |
1428 | serge | 10 | |
11 | |||
12 | |||
1246 | serge | 13 | |
1221 | serge | 14 | |
1246 | serge | 15 | static void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
16 | |||
1221 | serge | 17 | |
1963 | serge | 18 | |
1313 | serge | 19 | |
20 | {}; |
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21 | |||
22 | |||
1221 | serge | 23 | { |
24 | struct radeon_device *rdev; |
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25 | |||
26 | |||
27 | uint32_t *src; |
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28 | |||
29 | |||
30 | int r; |
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31 | |||
32 | |||
33 | |||
34 | |||
1963 | serge | 35 | PAGE_SIZE, false, RADEON_GEM_DOMAIN_VRAM, &cursor->robj); |
36 | |||
1221 | serge | 37 | |
38 | return r; |
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39 | |||
40 | |||
1404 | serge | 41 | if (unlikely(r != 0)) |
42 | return r; |
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43 | |||
1221 | serge | 44 | |
1404 | serge | 45 | if (unlikely(r != 0)) |
46 | return r; |
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47 | |||
48 | |||
49 | if (r) { |
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1221 | serge | 50 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
51 | return r; |
||
52 | }; |
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53 | |||
54 | |||
55 | |||
56 | |||
57 | { |
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58 | for(j = 0; j < 32; j++) |
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59 | *bits++ = *src++; |
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60 | for(j = 32; j < CURSOR_WIDTH; j++) |
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1230 | serge | 61 | *bits++ = 0; |
1221 | serge | 62 | } |
63 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
||
64 | *bits++ = 0; |
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65 | |||
66 | |||
1404 | serge | 67 | |
1221 | serge | 68 | |
1963 | serge | 69 | |
1313 | serge | 70 | |
1221 | serge | 71 | }; |
72 | |||
73 | |||
1963 | serge | 74 | { |
1313 | serge | 75 | list_del(&cursor->list); |
76 | radeon_bo_unpin(cursor->robj); |
||
1404 | serge | 77 | KernelFree(cursor->data); |
1313 | serge | 78 | __DestroyObject(cursor); |
79 | }; |
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80 | |||
81 | |||
82 | |||
1246 | serge | 83 | { |
1221 | serge | 84 | struct radeon_device *rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
1246 | serge | 85 | |
1230 | serge | 86 | |
87 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL); |
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1246 | serge | 88 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
1230 | serge | 89 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
90 | } else { |
||
91 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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1275 | serge | 92 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
1230 | serge | 93 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
94 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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95 | } |
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96 | } |
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97 | |||
98 | |||
99 | { |
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1221 | serge | 100 | struct radeon_device *rdev; |
101 | cursor_t *old; |
||
102 | uint32_t gpu_addr; |
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103 | |||
104 | |||
105 | |||
106 | |||
1230 | serge | 107 | |
1221 | serge | 108 | |
1230 | serge | 109 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
1404 | serge | 110 | |
1221 | serge | 111 | |
112 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr); |
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1246 | serge | 113 | else { |
1221 | serge | 114 | WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_start); |
1430 | serge | 115 | } |
1221 | serge | 116 | |
1230 | serge | 117 | |
1221 | serge | 118 | }; |
119 | |||
120 | |||
1246 | serge | 121 | { |
122 | struct radeon_device *rdev; |
||
123 | |||
1221 | serge | 124 | |
1246 | serge | 125 | |
126 | |||
127 | |||
128 | |||
129 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE); |
||
130 | if (lock) |
||
131 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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132 | else |
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133 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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134 | WREG32(AVIVO_D1CUR_UPDATE, cur_lock); |
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135 | } else { |
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136 | cur_lock = RREG32(RADEON_CUR_OFFSET); |
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137 | if (lock) |
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138 | cur_lock |= RADEON_CUR_LOCK; |
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139 | else |
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140 | cur_lock &= ~RADEON_CUR_LOCK; |
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141 | WREG32(RADEON_CUR_OFFSET, cur_lock); |
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142 | } |
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143 | } |
||
144 | |||
145 | |||
146 | |||
1230 | serge | 147 | { |
1221 | serge | 148 | struct radeon_device *rdev; |
1230 | serge | 149 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
150 | |||
1221 | serge | 151 | |
1230 | serge | 152 | int hot_y = cursor->hot_y; |
153 | |||
1221 | serge | 154 | |
1246 | serge | 155 | if (ASIC_IS_AVIVO(rdev)) |
1221 | serge | 156 | { |
157 | int w = 32; |
||
158 | |||
159 | |||
1246 | serge | 160 | WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y); |
161 | WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31); |
||
162 | } else { |
||
1275 | serge | 163 | |
1404 | serge | 164 | |
1246 | serge | 165 | int xorg =0, yorg=0; |
1404 | serge | 166 | |
1221 | serge | 167 | |
1404 | serge | 168 | y = y - hot_y; |
169 | |||
170 | |||
171 | { |
||
172 | xorg = -x + 1; |
||
173 | x = 0; |
||
174 | } |
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175 | |||
176 | |||
177 | { |
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178 | yorg = -hot_y + 1; |
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179 | y = 0; |
||
180 | }; |
||
181 | |||
182 | |||
1246 | serge | 183 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
1404 | serge | 184 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
1246 | serge | 185 | (RADEON_CUR_LOCK | (x << 16) | y)); |
1221 | serge | 186 | |
187 | |||
1404 | serge | 188 | |
1246 | serge | 189 | |
1221 | serge | 190 | WREG32(RADEON_CUR_OFFSET, |
1246 | serge | 191 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 192 | } |
1221 | serge | 193 | radeon_lock_cursor(false); |
1246 | serge | 194 | } |
1221 | serge | 195 | |
196 | |||
1230 | serge | 197 | { |
198 | }; |
||
199 | |||
1221 | serge | 200 | |
1233 | serge | 201 | |
1404 | serge | 202 | { |
1233 | serge | 203 | struct drm_device *dev; |
1275 | serge | 204 | |
1246 | serge | 205 | |
1275 | serge | 206 | bool retval = true; |
1268 | serge | 207 | u32_t ifl; |
1246 | serge | 208 | |
1233 | serge | 209 | |
210 | |||
211 | |||
212 | |||
213 | |||
1239 | serge | 214 | |
1233 | serge | 215 | |
1246 | serge | 216 | { |
217 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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1275 | serge | 218 | { |
219 | init_cursor(cursor); |
||
220 | }; |
||
221 | |||
1233 | serge | 222 | |
1275 | serge | 223 | rdisplay->init_cursor = init_cursor; |
224 | rdisplay->select_cursor = select_cursor; |
||
225 | rdisplay->show_cursor = NULL; |
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226 | rdisplay->move_cursor = move_cursor; |
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227 | rdisplay->restore_cursor = restore_cursor; |
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228 | rdisplay->disable_mouse = disable_mouse; |
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1313 | serge | 229 | |
1233 | serge | 230 | |
1246 | serge | 231 | radeon_show_cursor(); |
232 | }; |
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233 | safe_sti(ifl); |
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234 | |||
235 | |||
1233 | serge | 236 | |
237 | |||
1239 | serge | 238 | }; |
1233 | serge | 239 | |
240 | |||
241 | |||
1404 | serge | 242 | { |
243 | #define BYTES_PER_LONG (BITS_PER_LONG/8) |
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244 | #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) |
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245 | int fb_info_size = sizeof(struct fb_info); |
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246 | struct fb_info *info; |
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247 | char *p; |
||
248 | |||
1233 | serge | 249 | |
1404 | serge | 250 | fb_info_size += PADDING; |
251 | |||
252 | |||
253 | |||
254 | |||
255 | return NULL; |
||
256 | |||
257 | |||
258 | |||
259 | |||
260 | info->par = p + fb_info_size; |
||
261 | |||
262 | |||
263 | #undef PADDING |
||
264 | #undef BYTES_PER_LONG |
||
265 | } |
||
266 | |||
267 | |||
268 | { |
||
269 | kfree(info); |
||
270 | } |
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271 | |||
272 | |||
1963 | serge | 273 | |
274 | |||
1428 | serge | 275 | # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
276 | # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
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277 | # define R5XX_ROP3_P 0x00f00000 |
||
278 | |||
279 | |||
280 | #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
||
281 | # define R5XX_SC_SIGN_MASK_LO 0x8000 |
||
282 | # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
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283 | |||
284 | |||
285 | # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
||
286 | # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
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287 | |||
288 | |||
289 | |||
290 | { |
||
291 | |||
292 | |||
293 | uint32_t offset; |
||
294 | |||
295 | |||
296 | |||
297 | |||
298 | |||
299 | |||
300 | offset = rdev->mc.vram_start; |
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1430 | serge | 301 | |
1428 | serge | 302 | |
303 | if (r) { |
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304 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
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305 | return r; |
||
306 | } |
||
307 | radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0)); |
||
308 | radeon_ring_write(rdev, 0); |
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309 | |||
310 | |||
311 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
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312 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
||
313 | |||
314 | |||
315 | radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX | |
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316 | RADEON_DEFAULT_SC_BOTTOM_MAX); |
||
317 | |||
318 | |||
319 | radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
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320 | RADEON_GMC_BRUSH_SOLID_COLOR | |
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321 | RADEON_GMC_DST_32BPP | |
||
322 | RADEON_GMC_SRC_DATATYPE_COLOR | |
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323 | R5XX_GMC_CLR_CMP_CNTL_DIS | |
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324 | R5XX_GMC_WR_MSK_DIS | |
||
325 | R5XX_ROP3_P); |
||
326 | |||
327 | |||
328 | radeon_ring_write(rdev, 0x0000FF00); |
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329 | radeon_ring_write(rdev, (64<<16)|64); |
||
330 | radeon_ring_write(rdev, (128<<16)|128); |
||
331 | |||
332 | |||
333 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
||
334 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
||
335 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | |
||
336 | RADEON_WAIT_HOST_IDLECLEAN | |
||
337 | RADEON_WAIT_DMA_GUI_IDLE); |
||
338 | |||
339 | |||
340 | |||
341 | |||
342 | return r; |
||
343 | } |
||
344 | |||
345 | |||
346 | |||
347 | #include "r600_reg_r6xx.h" |
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348 | #include "r600d.h" |
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349 | |||
350 | |||
351 | { |
||
352 | 0xc0002400, |
||
353 | 0x00000000, |
||
354 | 0xc0012800, |
||
355 | 0x80000000, |
||
356 | 0x80000000, |
||
357 | 0xc0004600, |
||
358 | 0x00000016, |
||
359 | 0xc0016800, |
||
360 | 0x00000010, |
||
361 | 0x00028000, |
||
362 | 0xc0016800, |
||
363 | 0x00000010, |
||
364 | 0x00008000, |
||
365 | 0xc0016800, |
||
366 | 0x00000542, |
||
367 | 0x07000003, |
||
368 | 0xc0016800, |
||
369 | 0x000005c5, |
||
370 | 0x00000000, |
||
371 | 0xc0016800, |
||
372 | 0x00000363, |
||
373 | 0x00000000, |
||
374 | 0xc0016800, |
||
375 | 0x0000060c, |
||
376 | 0x82000000, |
||
377 | 0xc0016800, |
||
378 | 0x0000060e, |
||
379 | 0x01020204, |
||
380 | 0xc0016f00, |
||
381 | 0x00000000, |
||
382 | 0x00000000, |
||
383 | 0xc0016f00, |
||
384 | 0x00000001, |
||
385 | 0x00000000, |
||
386 | 0xc0096900, |
||
387 | 0x0000022a, |
||
388 | 0x00000000, |
||
389 | 0x00000000, |
||
390 | 0x00000000, |
||
391 | 0x00000000, |
||
392 | 0x00000000, |
||
393 | 0x00000000, |
||
394 | 0x00000000, |
||
395 | 0x00000000, |
||
396 | 0x00000000, |
||
397 | 0xc0016900, |
||
398 | 0x00000004, |
||
399 | 0x00000000, |
||
400 | 0xc0016900, |
||
401 | 0x0000000a, |
||
402 | 0x00000000, |
||
403 | 0xc0016900, |
||
404 | 0x0000000b, |
||
405 | 0x00000000, |
||
406 | 0xc0016900, |
||
407 | 0x0000010c, |
||
408 | 0x00000000, |
||
409 | 0xc0016900, |
||
410 | 0x0000010d, |
||
411 | 0x00000000, |
||
412 | 0xc0016900, |
||
413 | 0x00000200, |
||
414 | 0x00000000, |
||
415 | 0xc0016900, |
||
416 | 0x00000343, |
||
417 | 0x00000060, |
||
418 | 0xc0016900, |
||
419 | 0x00000344, |
||
420 | 0x00000040, |
||
421 | 0xc0016900, |
||
422 | 0x00000351, |
||
423 | 0x0000aa00, |
||
424 | 0xc0016900, |
||
425 | 0x00000104, |
||
426 | 0x00000000, |
||
427 | 0xc0016900, |
||
428 | 0x0000010e, |
||
429 | 0x00000000, |
||
430 | 0xc0046900, |
||
431 | 0x00000105, |
||
432 | 0x00000000, |
||
433 | 0x00000000, |
||
434 | 0x00000000, |
||
435 | 0x00000000, |
||
436 | 0xc0036900, |
||
437 | 0x00000109, |
||
438 | 0x00000000, |
||
439 | 0x00000000, |
||
440 | 0x00000000, |
||
441 | 0xc0046900, |
||
442 | 0x0000030c, |
||
443 | 0x01000000, |
||
444 | 0x00000000, |
||
445 | 0x00000000, |
||
446 | 0x00000000, |
||
447 | 0xc0046900, |
||
448 | 0x00000048, |
||
449 | 0x3f800000, |
||
450 | 0x00000000, |
||
451 | 0x3f800000, |
||
452 | 0x3f800000, |
||
453 | 0xc0016900, |
||
454 | 0x0000008e, |
||
455 | 0x0000000f, |
||
456 | 0xc0016900, |
||
457 | 0x00000080, |
||
458 | 0x00000000, |
||
459 | 0xc0016900, |
||
460 | 0x00000083, |
||
461 | 0x0000ffff, |
||
462 | 0xc0016900, |
||
463 | 0x00000084, |
||
464 | 0x00000000, |
||
465 | 0xc0016900, |
||
466 | 0x00000085, |
||
467 | 0x20002000, |
||
468 | 0xc0016900, |
||
469 | 0x00000086, |
||
470 | 0x00000000, |
||
471 | 0xc0016900, |
||
472 | 0x00000087, |
||
473 | 0x20002000, |
||
474 | 0xc0016900, |
||
475 | 0x00000088, |
||
476 | 0x00000000, |
||
477 | 0xc0016900, |
||
478 | 0x00000089, |
||
479 | 0x20002000, |
||
480 | 0xc0016900, |
||
481 | 0x0000008a, |
||
482 | 0x00000000, |
||
483 | 0xc0016900, |
||
484 | 0x0000008b, |
||
485 | 0x20002000, |
||
486 | 0xc0016900, |
||
487 | 0x0000008c, |
||
488 | 0x00000000, |
||
489 | 0xc0016900, |
||
490 | 0x00000094, |
||
491 | 0x80000000, |
||
492 | 0xc0016900, |
||
493 | 0x00000095, |
||
494 | 0x20002000, |
||
495 | 0xc0026900, |
||
496 | 0x000000b4, |
||
497 | 0x00000000, |
||
498 | 0x3f800000, |
||
499 | 0xc0016900, |
||
500 | 0x00000096, |
||
501 | 0x80000000, |
||
502 | 0xc0016900, |
||
503 | 0x00000097, |
||
504 | 0x20002000, |
||
505 | 0xc0026900, |
||
506 | 0x000000b6, |
||
507 | 0x00000000, |
||
508 | 0x3f800000, |
||
509 | 0xc0016900, |
||
510 | 0x00000098, |
||
511 | 0x80000000, |
||
512 | 0xc0016900, |
||
513 | 0x00000099, |
||
514 | 0x20002000, |
||
515 | 0xc0026900, |
||
516 | 0x000000b8, |
||
517 | 0x00000000, |
||
518 | 0x3f800000, |
||
519 | 0xc0016900, |
||
520 | 0x0000009a, |
||
521 | 0x80000000, |
||
522 | 0xc0016900, |
||
523 | 0x0000009b, |
||
524 | 0x20002000, |
||
525 | 0xc0026900, |
||
526 | 0x000000ba, |
||
527 | 0x00000000, |
||
528 | 0x3f800000, |
||
529 | 0xc0016900, |
||
530 | 0x0000009c, |
||
531 | 0x80000000, |
||
532 | 0xc0016900, |
||
533 | 0x0000009d, |
||
534 | 0x20002000, |
||
535 | 0xc0026900, |
||
536 | 0x000000bc, |
||
537 | 0x00000000, |
||
538 | 0x3f800000, |
||
539 | 0xc0016900, |
||
540 | 0x0000009e, |
||
541 | 0x80000000, |
||
542 | 0xc0016900, |
||
543 | 0x0000009f, |
||
544 | 0x20002000, |
||
545 | 0xc0026900, |
||
546 | 0x000000be, |
||
547 | 0x00000000, |
||
548 | 0x3f800000, |
||
549 | 0xc0016900, |
||
550 | 0x000000a0, |
||
551 | 0x80000000, |
||
552 | 0xc0016900, |
||
553 | 0x000000a1, |
||
554 | 0x20002000, |
||
555 | 0xc0026900, |
||
556 | 0x000000c0, |
||
557 | 0x00000000, |
||
558 | 0x3f800000, |
||
559 | 0xc0016900, |
||
560 | 0x000000a2, |
||
561 | 0x80000000, |
||
562 | 0xc0016900, |
||
563 | 0x000000a3, |
||
564 | 0x20002000, |
||
565 | 0xc0026900, |
||
566 | 0x000000c2, |
||
567 | 0x00000000, |
||
568 | 0x3f800000, |
||
569 | 0xc0016900, |
||
570 | 0x000000a4, |
||
571 | 0x80000000, |
||
572 | 0xc0016900, |
||
573 | 0x000000a5, |
||
574 | 0x20002000, |
||
575 | 0xc0026900, |
||
576 | 0x000000c4, |
||
577 | 0x00000000, |
||
578 | 0x3f800000, |
||
579 | 0xc0016900, |
||
580 | 0x000000a6, |
||
581 | 0x80000000, |
||
582 | 0xc0016900, |
||
583 | 0x000000a7, |
||
584 | 0x20002000, |
||
585 | 0xc0026900, |
||
586 | 0x000000c6, |
||
587 | 0x00000000, |
||
588 | 0x3f800000, |
||
589 | 0xc0016900, |
||
590 | 0x000000a8, |
||
591 | 0x80000000, |
||
592 | 0xc0016900, |
||
593 | 0x000000a9, |
||
594 | 0x20002000, |
||
595 | 0xc0026900, |
||
596 | 0x000000c8, |
||
597 | 0x00000000, |
||
598 | 0x3f800000, |
||
599 | 0xc0016900, |
||
600 | 0x000000aa, |
||
601 | 0x80000000, |
||
602 | 0xc0016900, |
||
603 | 0x000000ab, |
||
604 | 0x20002000, |
||
605 | 0xc0026900, |
||
606 | 0x000000ca, |
||
607 | 0x00000000, |
||
608 | 0x3f800000, |
||
609 | 0xc0016900, |
||
610 | 0x000000ac, |
||
611 | 0x80000000, |
||
612 | 0xc0016900, |
||
613 | 0x000000ad, |
||
614 | 0x20002000, |
||
615 | 0xc0026900, |
||
616 | 0x000000cc, |
||
617 | 0x00000000, |
||
618 | 0x3f800000, |
||
619 | 0xc0016900, |
||
620 | 0x000000ae, |
||
621 | 0x80000000, |
||
622 | 0xc0016900, |
||
623 | 0x000000af, |
||
624 | 0x20002000, |
||
625 | 0xc0026900, |
||
626 | 0x000000ce, |
||
627 | 0x00000000, |
||
628 | 0x3f800000, |
||
629 | 0xc0016900, |
||
630 | 0x000000b0, |
||
631 | 0x80000000, |
||
632 | 0xc0016900, |
||
633 | 0x000000b1, |
||
634 | 0x20002000, |
||
635 | 0xc0026900, |
||
636 | 0x000000d0, |
||
637 | 0x00000000, |
||
638 | 0x3f800000, |
||
639 | 0xc0016900, |
||
640 | 0x000000b2, |
||
641 | 0x80000000, |
||
642 | 0xc0016900, |
||
643 | 0x000000b3, |
||
644 | 0x20002000, |
||
645 | 0xc0026900, |
||
646 | 0x000000d2, |
||
647 | 0x00000000, |
||
648 | 0x3f800000, |
||
649 | 0xc0016900, |
||
650 | 0x00000293, |
||
651 | 0x00004010, |
||
652 | 0xc0016900, |
||
653 | 0x00000300, |
||
654 | 0x00000000, |
||
655 | 0xc0016900, |
||
656 | 0x00000301, |
||
657 | 0x00000000, |
||
658 | 0xc0016900, |
||
659 | 0x00000312, |
||
660 | 0xffffffff, |
||
661 | 0xc0016900, |
||
662 | 0x00000307, |
||
663 | 0x00000000, |
||
664 | 0xc0016900, |
||
665 | 0x00000308, |
||
666 | 0x00000000, |
||
667 | 0xc0016900, |
||
668 | 0x00000283, |
||
669 | 0x00000000, |
||
670 | 0xc0016900, |
||
671 | 0x00000292, |
||
672 | 0x00000000, |
||
673 | 0xc0066900, |
||
674 | 0x0000010f, |
||
675 | 0x00000000, |
||
676 | 0x00000000, |
||
677 | 0x00000000, |
||
678 | 0x00000000, |
||
679 | 0x00000000, |
||
680 | 0x00000000, |
||
681 | 0xc0016900, |
||
682 | 0x00000206, |
||
683 | 0x00000000, |
||
684 | 0xc0016900, |
||
685 | 0x00000207, |
||
686 | 0x00000000, |
||
687 | 0xc0016900, |
||
688 | 0x00000208, |
||
689 | 0x00000000, |
||
690 | 0xc0046900, |
||
691 | 0x00000303, |
||
692 | 0x3f800000, |
||
693 | 0x3f800000, |
||
694 | 0x3f800000, |
||
695 | 0x3f800000, |
||
696 | 0xc0016900, |
||
697 | 0x00000205, |
||
698 | 0x00000004, |
||
699 | 0xc0016900, |
||
700 | 0x00000280, |
||
701 | 0x00000000, |
||
702 | 0xc0016900, |
||
703 | 0x00000281, |
||
704 | 0x00000000, |
||
705 | 0xc0016900, |
||
706 | 0x0000037e, |
||
707 | 0x00000000, |
||
708 | 0xc0016900, |
||
709 | 0x00000382, |
||
710 | 0x00000000, |
||
711 | 0xc0016900, |
||
712 | 0x00000380, |
||
713 | 0x00000000, |
||
714 | 0xc0016900, |
||
715 | 0x00000383, |
||
716 | 0x00000000, |
||
717 | 0xc0016900, |
||
718 | 0x00000381, |
||
719 | 0x00000000, |
||
720 | 0xc0016900, |
||
721 | 0x00000282, |
||
722 | 0x00000008, |
||
723 | 0xc0016900, |
||
724 | 0x00000302, |
||
725 | 0x0000002d, |
||
726 | 0xc0016900, |
||
727 | 0x0000037f, |
||
728 | 0x00000000, |
||
729 | 0xc0016900, |
||
730 | 0x000001b2, |
||
731 | 0x00000000, |
||
732 | 0xc0016900, |
||
733 | 0x000001b6, |
||
734 | 0x00000000, |
||
735 | 0xc0016900, |
||
736 | 0x000001b7, |
||
737 | 0x00000000, |
||
738 | 0xc0016900, |
||
739 | 0x000001b8, |
||
740 | 0x00000000, |
||
741 | 0xc0016900, |
||
742 | 0x000001b9, |
||
743 | 0x00000000, |
||
744 | 0xc0016900, |
||
745 | 0x00000225, |
||
746 | 0x00000000, |
||
747 | 0xc0016900, |
||
748 | 0x00000229, |
||
749 | 0x00000000, |
||
750 | 0xc0016900, |
||
751 | 0x00000237, |
||
752 | 0x00000000, |
||
753 | 0xc0016900, |
||
754 | 0x00000100, |
||
755 | 0x00000800, |
||
756 | 0xc0016900, |
||
757 | 0x00000101, |
||
758 | 0x00000000, |
||
759 | 0xc0016900, |
||
760 | 0x00000102, |
||
761 | 0x00000000, |
||
762 | 0xc0016900, |
||
763 | 0x000002a8, |
||
764 | 0x00000000, |
||
765 | 0xc0016900, |
||
766 | 0x000002a9, |
||
767 | 0x00000000, |
||
768 | 0xc0016900, |
||
769 | 0x00000103, |
||
770 | 0x00000000, |
||
771 | 0xc0016900, |
||
772 | 0x00000284, |
||
773 | 0x00000000, |
||
774 | 0xc0016900, |
||
775 | 0x00000290, |
||
776 | 0x00000000, |
||
777 | 0xc0016900, |
||
778 | 0x00000285, |
||
779 | 0x00000000, |
||
780 | 0xc0016900, |
||
781 | 0x00000286, |
||
782 | 0x00000000, |
||
783 | 0xc0016900, |
||
784 | 0x00000287, |
||
785 | 0x00000000, |
||
786 | 0xc0016900, |
||
787 | 0x00000288, |
||
788 | 0x00000000, |
||
789 | 0xc0016900, |
||
790 | 0x00000289, |
||
791 | 0x00000000, |
||
792 | 0xc0016900, |
||
793 | 0x0000028a, |
||
794 | 0x00000000, |
||
795 | 0xc0016900, |
||
796 | 0x0000028b, |
||
797 | 0x00000000, |
||
798 | 0xc0016900, |
||
799 | 0x0000028c, |
||
800 | 0x00000000, |
||
801 | 0xc0016900, |
||
802 | 0x0000028d, |
||
803 | 0x00000000, |
||
804 | 0xc0016900, |
||
805 | 0x0000028e, |
||
806 | 0x00000000, |
||
807 | 0xc0016900, |
||
808 | 0x0000028f, |
||
809 | 0x00000000, |
||
810 | 0xc0016900, |
||
811 | 0x000002a1, |
||
812 | 0x00000000, |
||
813 | 0xc0016900, |
||
814 | 0x000002a5, |
||
815 | 0x00000000, |
||
816 | 0xc0016900, |
||
817 | 0x000002ac, |
||
818 | 0x00000000, |
||
819 | 0xc0016900, |
||
820 | 0x000002ad, |
||
821 | 0x00000000, |
||
822 | 0xc0016900, |
||
823 | 0x000002ae, |
||
824 | 0x00000000, |
||
825 | 0xc0016900, |
||
826 | 0x000002c8, |
||
827 | 0x00000000, |
||
828 | 0xc0016900, |
||
829 | 0x00000206, |
||
830 | 0x00000100, |
||
831 | 0xc0016900, |
||
832 | 0x00000204, |
||
833 | 0x00010000, |
||
834 | 0xc0036e00, |
||
835 | 0x00000000, |
||
836 | 0x00000012, |
||
837 | 0x00000000, |
||
838 | 0x00000000, |
||
839 | 0xc0016900, |
||
840 | 0x0000008f, |
||
841 | 0x0000000f, |
||
842 | 0xc0016900, |
||
843 | 0x000001e8, |
||
844 | 0x00000001, |
||
845 | 0xc0016900, |
||
846 | 0x00000202, |
||
847 | 0x00cc0000, |
||
848 | 0xc0016900, |
||
849 | 0x00000205, |
||
850 | 0x00000244, |
||
851 | 0xc0016900, |
||
852 | 0x00000203, |
||
853 | 0x00000210, |
||
854 | 0xc0016900, |
||
855 | 0x000001b1, |
||
856 | 0x00000000, |
||
857 | 0xc0016900, |
||
858 | 0x00000185, |
||
859 | 0x00000000, |
||
860 | 0xc0016900, |
||
861 | 0x000001b3, |
||
862 | 0x00000001, |
||
863 | 0xc0016900, |
||
864 | 0x000001b4, |
||
865 | 0x00000000, |
||
866 | 0xc0016900, |
||
867 | 0x00000191, |
||
868 | 0x00000b00, |
||
869 | 0xc0016900, |
||
870 | 0x000001b5, |
||
871 | 0x00000000, |
||
872 | }; |
||
873 | |||
874 | |||
875 | |||
876 | |||
877 | { |
||
878 | 0xc0012800, |
||
879 | 0x80000000, |
||
880 | 0x80000000, |
||
881 | 0xc0004600, |
||
882 | 0x00000016, |
||
883 | 0xc0016800, |
||
884 | 0x00000010, |
||
885 | 0x00028000, |
||
886 | 0xc0016800, |
||
887 | 0x00000010, |
||
888 | 0x00008000, |
||
889 | 0xc0016800, |
||
890 | 0x00000542, |
||
891 | 0x07000002, |
||
892 | 0xc0016800, |
||
893 | 0x000005c5, |
||
894 | 0x00000000, |
||
895 | 0xc0016800, |
||
896 | 0x00000363, |
||
897 | 0x00004000, |
||
898 | 0xc0016800, |
||
899 | 0x0000060c, |
||
900 | 0x00000000, |
||
901 | 0xc0016800, |
||
902 | 0x0000060e, |
||
903 | 0x00420204, |
||
904 | 0xc0016f00, |
||
905 | 0x00000000, |
||
906 | 0x00000000, |
||
907 | 0xc0016f00, |
||
908 | 0x00000001, |
||
909 | 0x00000000, |
||
910 | 0xc0096900, |
||
911 | 0x0000022a, |
||
912 | 0x00000000, |
||
913 | 0x00000000, |
||
914 | 0x00000000, |
||
915 | 0x00000000, |
||
916 | 0x00000000, |
||
917 | 0x00000000, |
||
918 | 0x00000000, |
||
919 | 0x00000000, |
||
920 | 0x00000000, |
||
921 | 0xc0016900, |
||
922 | 0x00000004, |
||
923 | 0x00000000, |
||
924 | 0xc0016900, |
||
925 | 0x0000000a, |
||
926 | 0x00000000, |
||
927 | 0xc0016900, |
||
928 | 0x0000000b, |
||
929 | 0x00000000, |
||
930 | 0xc0016900, |
||
931 | 0x0000010c, |
||
932 | 0x00000000, |
||
933 | 0xc0016900, |
||
934 | 0x0000010d, |
||
935 | 0x00000000, |
||
936 | 0xc0016900, |
||
937 | 0x00000200, |
||
938 | 0x00000000, |
||
939 | 0xc0016900, |
||
940 | 0x00000343, |
||
941 | 0x00000060, |
||
942 | 0xc0016900, |
||
943 | 0x00000344, |
||
944 | 0x00000000, |
||
945 | 0xc0016900, |
||
946 | 0x00000351, |
||
947 | 0x0000aa00, |
||
948 | 0xc0016900, |
||
949 | 0x00000104, |
||
950 | 0x00000000, |
||
951 | 0xc0016900, |
||
952 | 0x0000010e, |
||
953 | 0x00000000, |
||
954 | 0xc0046900, |
||
955 | 0x00000105, |
||
956 | 0x00000000, |
||
957 | 0x00000000, |
||
958 | 0x00000000, |
||
959 | 0x00000000, |
||
960 | 0xc0046900, |
||
961 | 0x0000030c, |
||
962 | 0x01000000, |
||
963 | 0x00000000, |
||
964 | 0x00000000, |
||
965 | 0x00000000, |
||
966 | 0xc0016900, |
||
967 | 0x0000008e, |
||
968 | 0x0000000f, |
||
969 | 0xc0016900, |
||
970 | 0x00000080, |
||
971 | 0x00000000, |
||
972 | 0xc0016900, |
||
973 | 0x00000083, |
||
974 | 0x0000ffff, |
||
975 | 0xc0016900, |
||
976 | 0x00000084, |
||
977 | 0x00000000, |
||
978 | 0xc0016900, |
||
979 | 0x00000085, |
||
980 | 0x20002000, |
||
981 | 0xc0016900, |
||
982 | 0x00000086, |
||
983 | 0x00000000, |
||
984 | 0xc0016900, |
||
985 | 0x00000087, |
||
986 | 0x20002000, |
||
987 | 0xc0016900, |
||
988 | 0x00000088, |
||
989 | 0x00000000, |
||
990 | 0xc0016900, |
||
991 | 0x00000089, |
||
992 | 0x20002000, |
||
993 | 0xc0016900, |
||
994 | 0x0000008a, |
||
995 | 0x00000000, |
||
996 | 0xc0016900, |
||
997 | 0x0000008b, |
||
998 | 0x20002000, |
||
999 | 0xc0016900, |
||
1000 | 0x0000008c, |
||
1001 | 0xaaaaaaaa, |
||
1002 | 0xc0016900, |
||
1003 | 0x00000094, |
||
1004 | 0x80000000, |
||
1005 | 0xc0016900, |
||
1006 | 0x00000095, |
||
1007 | 0x20002000, |
||
1008 | 0xc0026900, |
||
1009 | 0x000000b4, |
||
1010 | 0x00000000, |
||
1011 | 0x3f800000, |
||
1012 | 0xc0016900, |
||
1013 | 0x00000096, |
||
1014 | 0x80000000, |
||
1015 | 0xc0016900, |
||
1016 | 0x00000097, |
||
1017 | 0x20002000, |
||
1018 | 0xc0026900, |
||
1019 | 0x000000b6, |
||
1020 | 0x00000000, |
||
1021 | 0x3f800000, |
||
1022 | 0xc0016900, |
||
1023 | 0x00000098, |
||
1024 | 0x80000000, |
||
1025 | 0xc0016900, |
||
1026 | 0x00000099, |
||
1027 | 0x20002000, |
||
1028 | 0xc0026900, |
||
1029 | 0x000000b8, |
||
1030 | 0x00000000, |
||
1031 | 0x3f800000, |
||
1032 | 0xc0016900, |
||
1033 | 0x0000009a, |
||
1034 | 0x80000000, |
||
1035 | 0xc0016900, |
||
1036 | 0x0000009b, |
||
1037 | 0x20002000, |
||
1038 | 0xc0026900, |
||
1039 | 0x000000ba, |
||
1040 | 0x00000000, |
||
1041 | 0x3f800000, |
||
1042 | 0xc0016900, |
||
1043 | 0x0000009c, |
||
1044 | 0x80000000, |
||
1045 | 0xc0016900, |
||
1046 | 0x0000009d, |
||
1047 | 0x20002000, |
||
1048 | 0xc0026900, |
||
1049 | 0x000000bc, |
||
1050 | 0x00000000, |
||
1051 | 0x3f800000, |
||
1052 | 0xc0016900, |
||
1053 | 0x0000009e, |
||
1054 | 0x80000000, |
||
1055 | 0xc0016900, |
||
1056 | 0x0000009f, |
||
1057 | 0x20002000, |
||
1058 | 0xc0026900, |
||
1059 | 0x000000be, |
||
1060 | 0x00000000, |
||
1061 | 0x3f800000, |
||
1062 | 0xc0016900, |
||
1063 | 0x000000a0, |
||
1064 | 0x80000000, |
||
1065 | 0xc0016900, |
||
1066 | 0x000000a1, |
||
1067 | 0x20002000, |
||
1068 | 0xc0026900, |
||
1069 | 0x000000c0, |
||
1070 | 0x00000000, |
||
1071 | 0x3f800000, |
||
1072 | 0xc0016900, |
||
1073 | 0x000000a2, |
||
1074 | 0x80000000, |
||
1075 | 0xc0016900, |
||
1076 | 0x000000a3, |
||
1077 | 0x20002000, |
||
1078 | 0xc0026900, |
||
1079 | 0x000000c2, |
||
1080 | 0x00000000, |
||
1081 | 0x3f800000, |
||
1082 | 0xc0016900, |
||
1083 | 0x000000a4, |
||
1084 | 0x80000000, |
||
1085 | 0xc0016900, |
||
1086 | 0x000000a5, |
||
1087 | 0x20002000, |
||
1088 | 0xc0026900, |
||
1089 | 0x000000c4, |
||
1090 | 0x00000000, |
||
1091 | 0x3f800000, |
||
1092 | 0xc0016900, |
||
1093 | 0x000000a6, |
||
1094 | 0x80000000, |
||
1095 | 0xc0016900, |
||
1096 | 0x000000a7, |
||
1097 | 0x20002000, |
||
1098 | 0xc0026900, |
||
1099 | 0x000000c6, |
||
1100 | 0x00000000, |
||
1101 | 0x3f800000, |
||
1102 | 0xc0016900, |
||
1103 | 0x000000a8, |
||
1104 | 0x80000000, |
||
1105 | 0xc0016900, |
||
1106 | 0x000000a9, |
||
1107 | 0x20002000, |
||
1108 | 0xc0026900, |
||
1109 | 0x000000c8, |
||
1110 | 0x00000000, |
||
1111 | 0x3f800000, |
||
1112 | 0xc0016900, |
||
1113 | 0x000000aa, |
||
1114 | 0x80000000, |
||
1115 | 0xc0016900, |
||
1116 | 0x000000ab, |
||
1117 | 0x20002000, |
||
1118 | 0xc0026900, |
||
1119 | 0x000000ca, |
||
1120 | 0x00000000, |
||
1121 | 0x3f800000, |
||
1122 | 0xc0016900, |
||
1123 | 0x000000ac, |
||
1124 | 0x80000000, |
||
1125 | 0xc0016900, |
||
1126 | 0x000000ad, |
||
1127 | 0x20002000, |
||
1128 | 0xc0026900, |
||
1129 | 0x000000cc, |
||
1130 | 0x00000000, |
||
1131 | 0x3f800000, |
||
1132 | 0xc0016900, |
||
1133 | 0x000000ae, |
||
1134 | 0x80000000, |
||
1135 | 0xc0016900, |
||
1136 | 0x000000af, |
||
1137 | 0x20002000, |
||
1138 | 0xc0026900, |
||
1139 | 0x000000ce, |
||
1140 | 0x00000000, |
||
1141 | 0x3f800000, |
||
1142 | 0xc0016900, |
||
1143 | 0x000000b0, |
||
1144 | 0x80000000, |
||
1145 | 0xc0016900, |
||
1146 | 0x000000b1, |
||
1147 | 0x20002000, |
||
1148 | 0xc0026900, |
||
1149 | 0x000000d0, |
||
1150 | 0x00000000, |
||
1151 | 0x3f800000, |
||
1152 | 0xc0016900, |
||
1153 | 0x000000b2, |
||
1154 | 0x80000000, |
||
1155 | 0xc0016900, |
||
1156 | 0x000000b3, |
||
1157 | 0x20002000, |
||
1158 | 0xc0026900, |
||
1159 | 0x000000d2, |
||
1160 | 0x00000000, |
||
1161 | 0x3f800000, |
||
1162 | 0xc0016900, |
||
1163 | 0x00000293, |
||
1164 | 0x00514000, |
||
1165 | 0xc0016900, |
||
1166 | 0x00000300, |
||
1167 | 0x00000000, |
||
1168 | 0xc0016900, |
||
1169 | 0x00000301, |
||
1170 | 0x00000000, |
||
1171 | 0xc0016900, |
||
1172 | 0x00000312, |
||
1173 | 0xffffffff, |
||
1174 | 0xc0016900, |
||
1175 | 0x00000307, |
||
1176 | 0x00000000, |
||
1177 | 0xc0016900, |
||
1178 | 0x00000308, |
||
1179 | 0x00000000, |
||
1180 | 0xc0016900, |
||
1181 | 0x00000283, |
||
1182 | 0x00000000, |
||
1183 | 0xc0016900, |
||
1184 | 0x00000292, |
||
1185 | 0x00000000, |
||
1186 | 0xc0066900, |
||
1187 | 0x0000010f, |
||
1188 | 0x00000000, |
||
1189 | 0x00000000, |
||
1190 | 0x00000000, |
||
1191 | 0x00000000, |
||
1192 | 0x00000000, |
||
1193 | 0x00000000, |
||
1194 | 0xc0016900, |
||
1195 | 0x00000206, |
||
1196 | 0x00000000, |
||
1197 | 0xc0016900, |
||
1198 | 0x00000207, |
||
1199 | 0x00000000, |
||
1200 | 0xc0016900, |
||
1201 | 0x00000208, |
||
1202 | 0x00000000, |
||
1203 | 0xc0046900, |
||
1204 | 0x00000303, |
||
1205 | 0x3f800000, |
||
1206 | 0x3f800000, |
||
1207 | 0x3f800000, |
||
1208 | 0x3f800000, |
||
1209 | 0xc0016900, |
||
1210 | 0x00000205, |
||
1211 | 0x00000004, |
||
1212 | 0xc0016900, |
||
1213 | 0x00000280, |
||
1214 | 0x00000000, |
||
1215 | 0xc0016900, |
||
1216 | 0x00000281, |
||
1217 | 0x00000000, |
||
1218 | 0xc0016900, |
||
1219 | 0x0000037e, |
||
1220 | 0x00000000, |
||
1221 | 0xc0016900, |
||
1222 | 0x00000382, |
||
1223 | 0x00000000, |
||
1224 | 0xc0016900, |
||
1225 | 0x00000380, |
||
1226 | 0x00000000, |
||
1227 | 0xc0016900, |
||
1228 | 0x00000383, |
||
1229 | 0x00000000, |
||
1230 | 0xc0016900, |
||
1231 | 0x00000381, |
||
1232 | 0x00000000, |
||
1233 | 0xc0016900, |
||
1234 | 0x00000282, |
||
1235 | 0x00000008, |
||
1236 | 0xc0016900, |
||
1237 | 0x00000302, |
||
1238 | 0x0000002d, |
||
1239 | 0xc0016900, |
||
1240 | 0x0000037f, |
||
1241 | 0x00000000, |
||
1242 | 0xc0016900, |
||
1243 | 0x000001b2, |
||
1244 | 0x00000001, |
||
1245 | 0xc0016900, |
||
1246 | 0x000001b6, |
||
1247 | 0x00000000, |
||
1248 | 0xc0016900, |
||
1249 | 0x000001b7, |
||
1250 | 0x00000000, |
||
1251 | 0xc0016900, |
||
1252 | 0x000001b8, |
||
1253 | 0x00000000, |
||
1254 | 0xc0016900, |
||
1255 | 0x000001b9, |
||
1256 | 0x00000000, |
||
1257 | 0xc0016900, |
||
1258 | 0x00000225, |
||
1259 | 0x00000000, |
||
1260 | 0xc0016900, |
||
1261 | 0x00000229, |
||
1262 | 0x00000000, |
||
1263 | 0xc0016900, |
||
1264 | 0x00000237, |
||
1265 | 0x00000000, |
||
1266 | 0xc0016900, |
||
1267 | 0x00000100, |
||
1268 | 0x00000800, |
||
1269 | 0xc0016900, |
||
1270 | 0x00000101, |
||
1271 | 0x00000000, |
||
1272 | 0xc0016900, |
||
1273 | 0x00000102, |
||
1274 | 0x00000000, |
||
1275 | 0xc0016900, |
||
1276 | 0x000002a8, |
||
1277 | 0x00000000, |
||
1278 | 0xc0016900, |
||
1279 | 0x000002a9, |
||
1280 | 0x00000000, |
||
1281 | 0xc0016900, |
||
1282 | 0x00000103, |
||
1283 | 0x00000000, |
||
1284 | 0xc0016900, |
||
1285 | 0x00000284, |
||
1286 | 0x00000000, |
||
1287 | 0xc0016900, |
||
1288 | 0x00000290, |
||
1289 | 0x00000000, |
||
1290 | 0xc0016900, |
||
1291 | 0x00000285, |
||
1292 | 0x00000000, |
||
1293 | 0xc0016900, |
||
1294 | 0x00000286, |
||
1295 | 0x00000000, |
||
1296 | 0xc0016900, |
||
1297 | 0x00000287, |
||
1298 | 0x00000000, |
||
1299 | 0xc0016900, |
||
1300 | 0x00000288, |
||
1301 | 0x00000000, |
||
1302 | 0xc0016900, |
||
1303 | 0x00000289, |
||
1304 | 0x00000000, |
||
1305 | 0xc0016900, |
||
1306 | 0x0000028a, |
||
1307 | 0x00000000, |
||
1308 | 0xc0016900, |
||
1309 | 0x0000028b, |
||
1310 | 0x00000000, |
||
1311 | 0xc0016900, |
||
1312 | 0x0000028c, |
||
1313 | 0x00000000, |
||
1314 | 0xc0016900, |
||
1315 | 0x0000028d, |
||
1316 | 0x00000000, |
||
1317 | 0xc0016900, |
||
1318 | 0x0000028e, |
||
1319 | 0x00000000, |
||
1320 | 0xc0016900, |
||
1321 | 0x0000028f, |
||
1322 | 0x00000000, |
||
1323 | 0xc0016900, |
||
1324 | 0x000002a1, |
||
1325 | 0x00000000, |
||
1326 | 0xc0016900, |
||
1327 | 0x000002a5, |
||
1328 | 0x00000000, |
||
1329 | 0xc0016900, |
||
1330 | 0x000002ac, |
||
1331 | 0x00000000, |
||
1332 | 0xc0016900, |
||
1333 | 0x000002ad, |
||
1334 | 0x00000000, |
||
1335 | 0xc0016900, |
||
1336 | 0x000002ae, |
||
1337 | 0x00000000, |
||
1338 | 0xc0016900, |
||
1339 | 0x000002c8, |
||
1340 | 0x00000000, |
||
1341 | 0xc0016900, |
||
1342 | 0x00000206, |
||
1343 | 0x00000100, |
||
1344 | 0xc0016900, |
||
1345 | 0x00000204, |
||
1346 | 0x00010000, |
||
1347 | 0xc0036e00, |
||
1348 | 0x00000000, |
||
1349 | 0x00000012, |
||
1350 | 0x00000000, |
||
1351 | 0x00000000, |
||
1352 | 0xc0016900, |
||
1353 | 0x0000008f, |
||
1354 | 0x0000000f, |
||
1355 | 0xc0016900, |
||
1356 | 0x000001e8, |
||
1357 | 0x00000001, |
||
1358 | 0xc0016900, |
||
1359 | 0x00000202, |
||
1360 | 0x00cc0000, |
||
1361 | 0xc0016900, |
||
1362 | 0x00000205, |
||
1363 | 0x00000244, |
||
1364 | 0xc0016900, |
||
1365 | 0x00000203, |
||
1366 | 0x00000210, |
||
1367 | 0xc0016900, |
||
1368 | 0x000001b1, |
||
1369 | 0x00000000, |
||
1370 | 0xc0016900, |
||
1371 | 0x00000185, |
||
1372 | 0x00000000, |
||
1373 | 0xc0016900, |
||
1374 | 0x000001b3, |
||
1375 | 0x00000001, |
||
1376 | 0xc0016900, |
||
1377 | 0x000001b4, |
||
1378 | 0x00000000, |
||
1379 | 0xc0016900, |
||
1380 | 0x00000191, |
||
1381 | 0x00000b00, |
||
1382 | 0xc0016900, |
||
1383 | 0x000001b5, |
||
1384 | 0x00000000, |
||
1385 | }; |
||
1386 | |||
1387 | |||
1388 | const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); |
||
1389 | |||
1390 | |||
1391 | |||
1392 | int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader); |
||
1393 | |||
1394 | |||
1395 | |||
1396 | |||
1397 | static void |
||
1398 | set_render_target(struct radeon_device *rdev, int format, |
||
1399 | int w, int h, u64 gpu_addr) |
||
1400 | { |
||
1401 | u32 cb_color_info; |
||
1402 | int pitch, slice; |
||
1403 | |||
1404 | |||
1405 | if (h < 8) |
||
1406 | h = 8; |
||
1407 | |||
1408 | |||
1409 | pitch = (w / 8) - 1; |
||
1410 | slice = ((w * h) / 64) - 1; |
||
1411 | |||
1412 | |||
1413 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1414 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
1415 | |||
1416 | |||
1417 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
||
1418 | radeon_ring_write(rdev, 2 << 0); |
||
1419 | } |
||
1420 | |||
1421 | |||
1422 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1423 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
||
1424 | |||
1425 | |||
1426 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1427 | radeon_ring_write(rdev, 0); |
||
1428 | |||
1429 | |||
1430 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1431 | radeon_ring_write(rdev, cb_color_info); |
||
1432 | |||
1433 | |||
1434 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1435 | radeon_ring_write(rdev, 0); |
||
1436 | |||
1437 | |||
1438 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1439 | radeon_ring_write(rdev, 0); |
||
1440 | |||
1441 | |||
1442 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1443 | radeon_ring_write(rdev, 0); |
||
1444 | } |
||
1445 | |||
1446 | |||
1447 | |||
1448 | static void |
||
1449 | cp_set_surface_sync(struct radeon_device *rdev, |
||
1450 | u32 sync_type, u32 size, |
||
1451 | u64 mc_addr) |
||
1452 | { |
||
1453 | u32 cp_coher_size; |
||
1454 | |||
1455 | |||
1456 | cp_coher_size = 0xffffffff; |
||
1457 | else |
||
1458 | cp_coher_size = ((size + 255) >> 8); |
||
1459 | |||
1460 | |||
1461 | radeon_ring_write(rdev, sync_type); |
||
1462 | radeon_ring_write(rdev, cp_coher_size); |
||
1463 | radeon_ring_write(rdev, mc_addr >> 8); |
||
1464 | radeon_ring_write(rdev, 10); /* poll interval */ |
||
1465 | } |
||
1466 | |||
1467 | |||
1468 | static void |
||
1469 | set_default_state(struct radeon_device *rdev, |
||
1470 | u64 state_gpu_addr, u32 state_len) |
||
1471 | { |
||
1472 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
||
1473 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
||
1474 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
||
1475 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
||
1476 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
||
1477 | u64 gpu_addr; |
||
1478 | int dwords; |
||
1479 | |||
1480 | |||
1481 | case CHIP_R600: |
||
1482 | num_ps_gprs = 192; |
||
1483 | num_vs_gprs = 56; |
||
1484 | num_temp_gprs = 4; |
||
1485 | num_gs_gprs = 0; |
||
1486 | num_es_gprs = 0; |
||
1487 | num_ps_threads = 136; |
||
1488 | num_vs_threads = 48; |
||
1489 | num_gs_threads = 4; |
||
1490 | num_es_threads = 4; |
||
1491 | num_ps_stack_entries = 128; |
||
1492 | num_vs_stack_entries = 128; |
||
1493 | num_gs_stack_entries = 0; |
||
1494 | num_es_stack_entries = 0; |
||
1495 | break; |
||
1496 | case CHIP_RV630: |
||
1497 | case CHIP_RV635: |
||
1498 | num_ps_gprs = 84; |
||
1499 | num_vs_gprs = 36; |
||
1500 | num_temp_gprs = 4; |
||
1501 | num_gs_gprs = 0; |
||
1502 | num_es_gprs = 0; |
||
1503 | num_ps_threads = 144; |
||
1504 | num_vs_threads = 40; |
||
1505 | num_gs_threads = 4; |
||
1506 | num_es_threads = 4; |
||
1507 | num_ps_stack_entries = 40; |
||
1508 | num_vs_stack_entries = 40; |
||
1509 | num_gs_stack_entries = 32; |
||
1510 | num_es_stack_entries = 16; |
||
1511 | break; |
||
1512 | case CHIP_RV610: |
||
1513 | case CHIP_RV620: |
||
1514 | case CHIP_RS780: |
||
1515 | case CHIP_RS880: |
||
1516 | default: |
||
1517 | num_ps_gprs = 84; |
||
1518 | num_vs_gprs = 36; |
||
1519 | num_temp_gprs = 4; |
||
1520 | num_gs_gprs = 0; |
||
1521 | num_es_gprs = 0; |
||
1522 | num_ps_threads = 136; |
||
1523 | num_vs_threads = 48; |
||
1524 | num_gs_threads = 4; |
||
1525 | num_es_threads = 4; |
||
1526 | num_ps_stack_entries = 40; |
||
1527 | num_vs_stack_entries = 40; |
||
1528 | num_gs_stack_entries = 32; |
||
1529 | num_es_stack_entries = 16; |
||
1530 | break; |
||
1531 | case CHIP_RV670: |
||
1532 | num_ps_gprs = 144; |
||
1533 | num_vs_gprs = 40; |
||
1534 | num_temp_gprs = 4; |
||
1535 | num_gs_gprs = 0; |
||
1536 | num_es_gprs = 0; |
||
1537 | num_ps_threads = 136; |
||
1538 | num_vs_threads = 48; |
||
1539 | num_gs_threads = 4; |
||
1540 | num_es_threads = 4; |
||
1541 | num_ps_stack_entries = 40; |
||
1542 | num_vs_stack_entries = 40; |
||
1543 | num_gs_stack_entries = 32; |
||
1544 | num_es_stack_entries = 16; |
||
1545 | break; |
||
1546 | case CHIP_RV770: |
||
1547 | num_ps_gprs = 192; |
||
1548 | num_vs_gprs = 56; |
||
1549 | num_temp_gprs = 4; |
||
1550 | num_gs_gprs = 0; |
||
1551 | num_es_gprs = 0; |
||
1552 | num_ps_threads = 188; |
||
1553 | num_vs_threads = 60; |
||
1554 | num_gs_threads = 0; |
||
1555 | num_es_threads = 0; |
||
1556 | num_ps_stack_entries = 256; |
||
1557 | num_vs_stack_entries = 256; |
||
1558 | num_gs_stack_entries = 0; |
||
1559 | num_es_stack_entries = 0; |
||
1560 | break; |
||
1561 | case CHIP_RV730: |
||
1562 | case CHIP_RV740: |
||
1563 | num_ps_gprs = 84; |
||
1564 | num_vs_gprs = 36; |
||
1565 | num_temp_gprs = 4; |
||
1566 | num_gs_gprs = 0; |
||
1567 | num_es_gprs = 0; |
||
1568 | num_ps_threads = 188; |
||
1569 | num_vs_threads = 60; |
||
1570 | num_gs_threads = 0; |
||
1571 | num_es_threads = 0; |
||
1572 | num_ps_stack_entries = 128; |
||
1573 | num_vs_stack_entries = 128; |
||
1574 | num_gs_stack_entries = 0; |
||
1575 | num_es_stack_entries = 0; |
||
1576 | break; |
||
1577 | case CHIP_RV710: |
||
1578 | num_ps_gprs = 192; |
||
1579 | num_vs_gprs = 56; |
||
1580 | num_temp_gprs = 4; |
||
1581 | num_gs_gprs = 0; |
||
1582 | num_es_gprs = 0; |
||
1583 | num_ps_threads = 144; |
||
1584 | num_vs_threads = 48; |
||
1585 | num_gs_threads = 0; |
||
1586 | num_es_threads = 0; |
||
1587 | num_ps_stack_entries = 128; |
||
1588 | num_vs_stack_entries = 128; |
||
1589 | num_gs_stack_entries = 0; |
||
1590 | num_es_stack_entries = 0; |
||
1591 | break; |
||
1592 | } |
||
1593 | |||
1594 | |||
1595 | (rdev->family == CHIP_RV620) || |
||
1596 | (rdev->family == CHIP_RS780) || |
||
1597 | (rdev->family == CHIP_RS880) || |
||
1598 | (rdev->family == CHIP_RV710)) |
||
1599 | sq_config = 0; |
||
1600 | else |
||
1601 | sq_config = VC_ENABLE; |
||
1602 | |||
1603 | |||
1604 | ALU_INST_PREFER_VECTOR | |
||
1605 | PS_PRIO(0) | |
||
1606 | VS_PRIO(1) | |
||
1607 | GS_PRIO(2) | |
||
1608 | ES_PRIO(3)); |
||
1609 | |||
1610 | |||
1611 | NUM_VS_GPRS(num_vs_gprs) | |
||
1612 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
||
1613 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
||
1614 | NUM_ES_GPRS(num_es_gprs)); |
||
1615 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
||
1616 | NUM_VS_THREADS(num_vs_threads) | |
||
1617 | NUM_GS_THREADS(num_gs_threads) | |
||
1618 | NUM_ES_THREADS(num_es_threads)); |
||
1619 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
||
1620 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
||
1621 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
||
1622 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
||
1623 | |||
1624 | |||
1625 | dwords = (state_len + 0xf) & ~0xf; |
||
1626 | gpu_addr = state_gpu_addr; |
||
1627 | |||
1628 | |||
1629 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
||
1630 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
||
1631 | radeon_ring_write(rdev, dwords); |
||
1632 | |||
1633 | |||
1634 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
||
1635 | /* SQ config */ |
||
1636 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
||
1637 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
1638 | radeon_ring_write(rdev, sq_config); |
||
1639 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
||
1640 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
||
1641 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
||
1642 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
||
1643 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
||
1644 | } |
||
1645 | |||
1646 | |||
1647 | static void |
||
1648 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
||
1649 | int x2, int y2) |
||
1650 | { |
||
1651 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
||
1652 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1653 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
||
1654 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
1655 | |||
1656 | |||
1657 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1658 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
||
1659 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
1660 | |||
1661 | |||
1662 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
1663 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
||
1664 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
||
1665 | } |
||
1666 | |||
1667 | |||
1668 | draw_auto(struct radeon_device *rdev) |
||
1669 | { |
||
1670 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
1671 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
1672 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
||
1673 | |||
1674 | |||
1675 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); |
||
1676 | |||
1677 | |||
1678 | radeon_ring_write(rdev, 1); |
||
1679 | |||
1680 | |||
1681 | radeon_ring_write(rdev, 3); |
||
1682 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
||
1683 | |||
1684 | |||
1685 | |||
1686 | |||
1687 | #define SRC0_SEL(x) (x) |
||
1688 | #define SRC1_SEL(x) (x) |
||
1689 | #define SRC2_SEL(x) (x) |
||
1690 | /* src[0-2]_sel */ |
||
1691 | /* 0-127 GPR */ |
||
1692 | /* 128-159 kcache constants bank 0 */ |
||
1693 | /* 160-191 kcache constants bank 1 */ |
||
1694 | /* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */ |
||
1695 | |||
1696 | |||
1697 | #define SRC1_REL(x) (x) |
||
1698 | #define SRC2_REL(x) (x) |
||
1699 | /* elem */ |
||
1700 | #define SRC0_ELEM(x) (x) |
||
1701 | #define SRC1_ELEM(x) (x) |
||
1702 | #define SRC2_ELEM(x) (x) |
||
1703 | #define ELEM_X 0 |
||
1704 | #define ELEM_Y 1 |
||
1705 | #define ELEM_Z 2 |
||
1706 | #define ELEM_W 3 |
||
1707 | /* neg */ |
||
1708 | #define SRC0_NEG(x) (x) |
||
1709 | #define SRC1_NEG(x) (x) |
||
1710 | #define SRC2_NEG(x) (x) |
||
1711 | /* im */ |
||
1712 | #define INDEX_MODE(x) (x) /* SQ_INDEX_* */ |
||
1713 | /* ps */ |
||
1714 | #define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */ |
||
1715 | /* last */ |
||
1716 | #define LAST(x) (x) |
||
1717 | /* abs */ |
||
1718 | #define SRC0_ABS(x) (x) |
||
1719 | #define SRC1_ABS(x) (x) |
||
1720 | /* uem */ |
||
1721 | #define UPDATE_EXECUTE_MASK(x) (x) |
||
1722 | /* up */ |
||
1723 | #define UPDATE_PRED(x) (x) |
||
1724 | /* wm */ |
||
1725 | #define WRITE_MASK(x) (x) |
||
1726 | /* fm */ |
||
1727 | #define FOG_MERGE(x) (x) |
||
1728 | /* omod */ |
||
1729 | #define OMOD(x) (x) /* SQ_ALU_OMOD_* */ |
||
1730 | /* alu inst */ |
||
1731 | #define ALU_INST(x) (x) /* SQ_ALU_INST_* */ |
||
1732 | /*bs */ |
||
1733 | #define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */ |
||
1734 | #define DST_GPR(x) (x) |
||
1735 | #define DST_REL(x) (x) |
||
1736 | #define DST_ELEM(x) (x) |
||
1737 | #define CLAMP(x) (x) |
||
1738 | |||
1739 | |||
1740 | (((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ |
||
1741 | ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ |
||
1742 | ((im) << 26) | ((ps) << 29) | ((last) << 31)) |
||
1743 | |||
1744 | |||
1745 | #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
||
1746 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
||
1747 | ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
||
1748 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
||
1749 | |||
1750 | |||
1751 | (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
||
1752 | ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
||
1753 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) |
||
1754 | |||
1755 | |||
1756 | /* Fog is NOT USED on R7xx, even if specified. */ |
||
1757 | #define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
||
1758 | ((chipid) < CHIP_RV770 ? \ |
||
1759 | R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ |
||
1760 | R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) |
||
1761 | |||
1762 | |||
1763 | (((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ |
||
1764 | ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ |
||
1765 | ((de) << 29) | ((clamp) << 31)) |
||
1766 | |||
1767 | |||
1768 | /* addr */ |
||
1769 | #define ADDR(x) (x) |
||
1770 | /* pc */ |
||
1771 | #define POP_COUNT(x) (x) |
||
1772 | /* const */ |
||
1773 | #define CF_CONST(x) (x) |
||
1774 | /* cond */ |
||
1775 | #define COND(x) (x) /* SQ_COND_* */ |
||
1776 | /* count */ |
||
1777 | #define I_COUNT(x) ((x) ? ((x) - 1) : 0) |
||
1778 | /*r7xx */ |
||
1779 | #define COUNT_3(x) (x) |
||
1780 | /* call count */ |
||
1781 | #define CALL_COUNT(x) (x) |
||
1782 | /* eop */ |
||
1783 | #define END_OF_PROGRAM(x) (x) |
||
1784 | /* vpm */ |
||
1785 | #define VALID_PIXEL_MODE(x) (x) |
||
1786 | /* cf inst */ |
||
1787 | #define CF_INST(x) (x) /* SQ_CF_INST_* */ |
||
1788 | |||
1789 | |||
1790 | #define WHOLE_QUAD_MODE(x) (x) |
||
1791 | /* barrier */ |
||
1792 | #define BARRIER(x) (x) |
||
1793 | /*kb0 */ |
||
1794 | #define KCACHE_BANK0(x) (x) |
||
1795 | /*kb1 */ |
||
1796 | #define KCACHE_BANK1(x) (x) |
||
1797 | /* km0/1 */ |
||
1798 | #define KCACHE_MODE0(x) (x) |
||
1799 | #define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */ |
||
1800 | /* */ |
||
1801 | #define KCACHE_ADDR0(x) (x) |
||
1802 | #define KCACHE_ADDR1(x) (x) |
||
1803 | /* uw */ |
||
1804 | #define USES_WATERFALL(x) (x) |
||
1805 | |||
1806 | |||
1807 | /* export pixel */ |
||
1808 | #define CF_PIXEL_MRT0 0 |
||
1809 | #define CF_PIXEL_MRT1 1 |
||
1810 | #define CF_PIXEL_MRT2 2 |
||
1811 | #define CF_PIXEL_MRT3 3 |
||
1812 | #define CF_PIXEL_MRT4 4 |
||
1813 | #define CF_PIXEL_MRT5 5 |
||
1814 | #define CF_PIXEL_MRT6 6 |
||
1815 | #define CF_PIXEL_MRT7 7 |
||
1816 | /* *_FOG: r6xx only */ |
||
1817 | #define CF_PIXEL_MRT0_FOG 16 |
||
1818 | #define CF_PIXEL_MRT1_FOG 17 |
||
1819 | #define CF_PIXEL_MRT2_FOG 18 |
||
1820 | #define CF_PIXEL_MRT3_FOG 19 |
||
1821 | #define CF_PIXEL_MRT4_FOG 20 |
||
1822 | #define CF_PIXEL_MRT5_FOG 21 |
||
1823 | #define CF_PIXEL_MRT6_FOG 22 |
||
1824 | #define CF_PIXEL_MRT7_FOG 23 |
||
1825 | #define CF_PIXEL_Z 61 |
||
1826 | /* export pos */ |
||
1827 | #define CF_POS0 60 |
||
1828 | #define CF_POS1 61 |
||
1829 | #define CF_POS2 62 |
||
1830 | #define CF_POS3 63 |
||
1831 | /* export param */ |
||
1832 | /* 0...31 */ |
||
1833 | #define TYPE(x) (x) /* SQ_EXPORT_* */ |
||
1834 | #if 0 |
||
1835 | /* type export */ |
||
1836 | #define SQ_EXPORT_PIXEL 0 |
||
1837 | #define SQ_EXPORT_POS 1 |
||
1838 | #define SQ_EXPORT_PARAM 2 |
||
1839 | /* reserved 3 */ |
||
1840 | /* type mem */ |
||
1841 | #define SQ_EXPORT_WRITE 0 |
||
1842 | #define SQ_EXPORT_WRITE_IND 1 |
||
1843 | #define SQ_EXPORT_WRITE_ACK 2 |
||
1844 | #define SQ_EXPORT_WRITE_IND_ACK 3 |
||
1845 | #endif |
||
1846 | |||
1847 | |||
1848 | #define RW_REL(x) (x) |
||
1849 | #define ABSOLUTE 0 |
||
1850 | #define RELATIVE 1 |
||
1851 | #define INDEX_GPR(x) (x) |
||
1852 | #define ELEM_SIZE(x) (x ? (x - 1) : 0) |
||
1853 | #define COMP_MASK(x) (x) |
||
1854 | #define R6xx_ELEM_LOOP(x) (x) |
||
1855 | #define BURST_COUNT(x) (x ? (x - 1) : 0) |
||
1856 | |||
1857 | |||
1858 | #define SRC_SEL_X(x) (x) /* SQ_SEL_* each */ |
||
1859 | #define SRC_SEL_Y(x) (x) |
||
1860 | #define SRC_SEL_Z(x) (x) |
||
1861 | #define SRC_SEL_W(x) (x) |
||
1862 | |||
1863 | |||
1864 | /* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */ |
||
1865 | /* We allow one more bit for count in the argument of the macro on R7xx instead. */ |
||
1866 | /* R6xx: [0,7] R7xx: [1,16] */ |
||
1867 | #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ |
||
1868 | (((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ |
||
1869 | ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
||
1870 | |||
1871 | |||
1872 | #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ |
||
1873 | (((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ |
||
1874 | ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)) |
||
1875 | |||
1876 | |||
1877 | (((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ |
||
1878 | ((es) << 30)) |
||
1879 | /* R7xx apparently doesn't have the ELEM_LOOP entry any more */ |
||
1880 | /* We still expose it, but ELEM_LOOP is explicitely R6xx now. */ |
||
1881 | /* TODO: is this just forgotten in the docs, or really not available any more? */ |
||
1882 | #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ |
||
1883 | (((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ |
||
1884 | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) |
||
1885 | #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ |
||
1886 | (((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ |
||
1887 | ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ |
||
1888 | ((wqm) << 30) | ((b) << 31)) |
||
1889 | |||
1890 | |||
1891 | /* vxt insts */ |
||
1892 | #define VTX_INST(x) (x) /* SQ_VTX_INST_* */ |
||
1893 | |||
1894 | |||
1895 | #define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */ |
||
1896 | |||
1897 | |||
1898 | #define BUFFER_ID(x) (x) |
||
1899 | #define SRC_GPR(x) (x) |
||
1900 | #define SRC_REL(x) (x) |
||
1901 | #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) |
||
1902 | |||
1903 | |||
1904 | #define DST_SEL_X(x) (x) |
||
1905 | #define DST_SEL_Y(x) (x) |
||
1906 | #define DST_SEL_Z(x) (x) |
||
1907 | #define DST_SEL_W(x) (x) |
||
1908 | #define USE_CONST_FIELDS(x) (x) |
||
1909 | #define DATA_FORMAT(x) (x) |
||
1910 | /* num format */ |
||
1911 | #define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */ |
||
1912 | /* format comp */ |
||
1913 | #define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */ |
||
1914 | /* sma */ |
||
1915 | #define SRF_MODE_ALL(x) (x) |
||
1916 | #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 |
||
1917 | #define SRF_MODE_NO_ZERO 1 |
||
1918 | #define OFFSET(x) (x) |
||
1919 | /* endian swap */ |
||
1920 | #define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */ |
||
1921 | #define CONST_BUF_NO_STRIDE(x) (x) |
||
1922 | /* mf */ |
||
1923 | #define MEGA_FETCH(x) (x) |
||
1924 | |||
1925 | |||
1926 | (((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ |
||
1927 | ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)) |
||
1928 | #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
||
1929 | (((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
||
1930 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
||
1931 | #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
||
1932 | (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
||
1933 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) |
||
1934 | #define VTX_DWORD2(offset, es, cbns, mf) \ |
||
1935 | (((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)) |
||
1936 | #define VTX_DWORD_PAD 0x00000000 |
||
1937 | |||
1938 | |||
1939 | |||
1940 | { |
||
1941 | int i=0; |
||
1942 | |||
1943 | |||
1944 | shader[i++] = CF_DWORD0(ADDR(4)); |
||
1945 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
||
1946 | CF_CONST(0), |
||
1947 | COND(SQ_CF_COND_ACTIVE), |
||
1948 | I_COUNT(1), |
||
1949 | CALL_COUNT(0), |
||
1950 | END_OF_PROGRAM(0), |
||
1951 | VALID_PIXEL_MODE(0), |
||
1952 | CF_INST(SQ_CF_INST_VTX), |
||
1953 | WHOLE_QUAD_MODE(0), |
||
1954 | BARRIER(1)); |
||
1955 | /* 1 */ |
||
1956 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), |
||
1957 | TYPE(SQ_EXPORT_POS), |
||
1958 | RW_GPR(1), |
||
1959 | RW_REL(ABSOLUTE), |
||
1960 | INDEX_GPR(0), |
||
1961 | ELEM_SIZE(0)); |
||
1962 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
1963 | SRC_SEL_Y(SQ_SEL_Y), |
||
1964 | SRC_SEL_Z(SQ_SEL_Z), |
||
1965 | SRC_SEL_W(SQ_SEL_W), |
||
1966 | R6xx_ELEM_LOOP(0), |
||
1967 | BURST_COUNT(1), |
||
1968 | END_OF_PROGRAM(0), |
||
1969 | VALID_PIXEL_MODE(0), |
||
1970 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
1971 | WHOLE_QUAD_MODE(0), |
||
1972 | BARRIER(1)); |
||
1973 | /* 2 - always export a param whether it's used or not */ |
||
1974 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), |
||
1975 | TYPE(SQ_EXPORT_PARAM), |
||
1976 | RW_GPR(0), |
||
1977 | RW_REL(ABSOLUTE), |
||
1978 | INDEX_GPR(0), |
||
1979 | ELEM_SIZE(0)); |
||
1980 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
1981 | SRC_SEL_Y(SQ_SEL_Y), |
||
1982 | SRC_SEL_Z(SQ_SEL_Z), |
||
1983 | SRC_SEL_W(SQ_SEL_W), |
||
1984 | R6xx_ELEM_LOOP(0), |
||
1985 | BURST_COUNT(0), |
||
1986 | END_OF_PROGRAM(1), |
||
1987 | VALID_PIXEL_MODE(0), |
||
1988 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
1989 | WHOLE_QUAD_MODE(0), |
||
1990 | BARRIER(0)); |
||
1991 | /* 3 - padding */ |
||
1992 | shader[i++] = 0x00000000; |
||
1993 | shader[i++] = 0x00000000; |
||
1994 | /* 4/5 */ |
||
1995 | shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), |
||
1996 | FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), |
||
1997 | FETCH_WHOLE_QUAD(0), |
||
1998 | BUFFER_ID(0), |
||
1999 | SRC_GPR(0), |
||
2000 | SRC_REL(ABSOLUTE), |
||
2001 | SRC_SEL_X(SQ_SEL_X), |
||
2002 | MEGA_FETCH_COUNT(8)); |
||
2003 | shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), |
||
2004 | DST_REL(0), |
||
2005 | DST_SEL_X(SQ_SEL_X), |
||
2006 | DST_SEL_Y(SQ_SEL_Y), |
||
2007 | DST_SEL_Z(SQ_SEL_0), |
||
2008 | DST_SEL_W(SQ_SEL_1), |
||
2009 | USE_CONST_FIELDS(0), |
||
2010 | DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ |
||
2011 | NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ |
||
2012 | FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ |
||
2013 | SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); |
||
2014 | shader[i++] = VTX_DWORD2(OFFSET(0), |
||
2015 | ENDIAN_SWAP(ENDIAN_NONE), |
||
2016 | CONST_BUF_NO_STRIDE(0), |
||
2017 | MEGA_FETCH(1)); |
||
2018 | shader[i++] = VTX_DWORD_PAD; |
||
2019 | |||
2020 | |||
2021 | } |
||
2022 | |||
2023 | |||
2024 | { |
||
2025 | int i=0; |
||
2026 | |||
2027 | |||
2028 | shader[i++] = CF_ALU_DWORD0(ADDR(2), |
||
2029 | KCACHE_BANK0(0), |
||
2030 | KCACHE_BANK1(0), |
||
2031 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); |
||
2032 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), |
||
2033 | KCACHE_ADDR0(0), |
||
2034 | KCACHE_ADDR1(0), |
||
2035 | I_COUNT(4), |
||
2036 | USES_WATERFALL(0), |
||
2037 | CF_INST(SQ_CF_INST_ALU), |
||
2038 | WHOLE_QUAD_MODE(0), |
||
2039 | BARRIER(1)); |
||
2040 | /* 1 */ |
||
2041 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
||
2042 | TYPE(SQ_EXPORT_PIXEL), |
||
2043 | RW_GPR(0), |
||
2044 | RW_REL(ABSOLUTE), |
||
2045 | INDEX_GPR(0), |
||
2046 | ELEM_SIZE(1)); |
||
2047 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
||
2048 | SRC_SEL_Y(SQ_SEL_Y), |
||
2049 | SRC_SEL_Z(SQ_SEL_Z), |
||
2050 | SRC_SEL_W(SQ_SEL_W), |
||
2051 | R6xx_ELEM_LOOP(0), |
||
2052 | BURST_COUNT(1), |
||
2053 | END_OF_PROGRAM(1), |
||
2054 | VALID_PIXEL_MODE(0), |
||
2055 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
||
2056 | WHOLE_QUAD_MODE(0), |
||
2057 | BARRIER(1)); |
||
2058 | |||
2059 | |||
2060 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
2061 | SRC0_REL(ABSOLUTE), |
||
2062 | SRC0_ELEM(ELEM_X), |
||
2063 | SRC0_NEG(0), |
||
2064 | SRC1_SEL(0), |
||
2065 | SRC1_REL(ABSOLUTE), |
||
2066 | SRC1_ELEM(ELEM_X), |
||
2067 | SRC1_NEG(0), |
||
2068 | INDEX_MODE(SQ_INDEX_AR_X), |
||
2069 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
2070 | LAST(0)); |
||
2071 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
2072 | SRC0_ABS(0), |
||
2073 | SRC1_ABS(0), |
||
2074 | UPDATE_EXECUTE_MASK(0), |
||
2075 | UPDATE_PRED(0), |
||
2076 | WRITE_MASK(1), |
||
2077 | FOG_MERGE(0), |
||
2078 | OMOD(SQ_ALU_OMOD_OFF), |
||
2079 | ALU_INST(SQ_OP2_INST_MOV), |
||
2080 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
2081 | DST_GPR(0), |
||
2082 | DST_REL(ABSOLUTE), |
||
2083 | DST_ELEM(ELEM_X), |
||
2084 | CLAMP(1)); |
||
2085 | /* 3 */ |
||
2086 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
2087 | SRC0_REL(ABSOLUTE), |
||
2088 | SRC0_ELEM(ELEM_Y), |
||
2089 | SRC0_NEG(0), |
||
2090 | SRC1_SEL(0), |
||
2091 | SRC1_REL(ABSOLUTE), |
||
2092 | SRC1_ELEM(ELEM_Y), |
||
2093 | SRC1_NEG(0), |
||
2094 | INDEX_MODE(SQ_INDEX_AR_X), |
||
2095 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
2096 | LAST(0)); |
||
2097 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
2098 | SRC0_ABS(0), |
||
2099 | SRC1_ABS(0), |
||
2100 | UPDATE_EXECUTE_MASK(0), |
||
2101 | UPDATE_PRED(0), |
||
2102 | WRITE_MASK(1), |
||
2103 | FOG_MERGE(0), |
||
2104 | OMOD(SQ_ALU_OMOD_OFF), |
||
2105 | ALU_INST(SQ_OP2_INST_MOV), |
||
2106 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
2107 | DST_GPR(0), |
||
2108 | DST_REL(ABSOLUTE), |
||
2109 | DST_ELEM(ELEM_Y), |
||
2110 | CLAMP(1)); |
||
2111 | /* 4 */ |
||
2112 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
2113 | SRC0_REL(ABSOLUTE), |
||
2114 | SRC0_ELEM(ELEM_Z), |
||
2115 | SRC0_NEG(0), |
||
2116 | SRC1_SEL(0), |
||
2117 | SRC1_REL(ABSOLUTE), |
||
2118 | SRC1_ELEM(ELEM_Z), |
||
2119 | SRC1_NEG(0), |
||
2120 | INDEX_MODE(SQ_INDEX_AR_X), |
||
2121 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
2122 | LAST(0)); |
||
2123 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
2124 | SRC0_ABS(0), |
||
2125 | SRC1_ABS(0), |
||
2126 | UPDATE_EXECUTE_MASK(0), |
||
2127 | UPDATE_PRED(0), |
||
2128 | WRITE_MASK(1), |
||
2129 | FOG_MERGE(0), |
||
2130 | OMOD(SQ_ALU_OMOD_OFF), |
||
2131 | ALU_INST(SQ_OP2_INST_MOV), |
||
2132 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
2133 | DST_GPR(0), |
||
2134 | DST_REL(ABSOLUTE), |
||
2135 | DST_ELEM(ELEM_Z), |
||
2136 | CLAMP(1)); |
||
2137 | /* 5 */ |
||
2138 | shader[i++] = ALU_DWORD0(SRC0_SEL(256), |
||
2139 | SRC0_REL(ABSOLUTE), |
||
2140 | SRC0_ELEM(ELEM_W), |
||
2141 | SRC0_NEG(0), |
||
2142 | SRC1_SEL(0), |
||
2143 | SRC1_REL(ABSOLUTE), |
||
2144 | SRC1_ELEM(ELEM_W), |
||
2145 | SRC1_NEG(0), |
||
2146 | INDEX_MODE(SQ_INDEX_AR_X), |
||
2147 | PRED_SEL(SQ_PRED_SEL_OFF), |
||
2148 | LAST(1)); |
||
2149 | shader[i++] = ALU_DWORD1_OP2(rdev->family, |
||
2150 | SRC0_ABS(0), |
||
2151 | SRC1_ABS(0), |
||
2152 | UPDATE_EXECUTE_MASK(0), |
||
2153 | UPDATE_PRED(0), |
||
2154 | WRITE_MASK(1), |
||
2155 | FOG_MERGE(0), |
||
2156 | OMOD(SQ_ALU_OMOD_OFF), |
||
2157 | ALU_INST(SQ_OP2_INST_MOV), |
||
2158 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
||
2159 | DST_GPR(0), |
||
2160 | DST_REL(ABSOLUTE), |
||
2161 | DST_ELEM(ELEM_W), |
||
2162 | CLAMP(1)); |
||
2163 | |||
2164 | |||
2165 | } |
||
2166 | |||
2167 | |||
2168 | memcpy_toio(volatile void __iomem *dst, const void *src, int count) |
||
2169 | { |
||
2170 | __memcpy((void __force *)dst, src, count); |
||
2171 | } |
||
2172 | |||
2173 | |||
2174 | do { \ |
||
2175 | union { float f; uint32_t d; } a; \ |
||
2176 | a.f = (val); \ |
||
2177 | radeon_ring_write(rdev, a.d); \ |
||
2178 | } while (0) |
||
2179 | |||
2180 | |||
2181 | { |
||
2182 | uint32_t ps_shader[16]; |
||
2183 | uint32_t vs_shader[16]; |
||
2184 | |||
2185 | |||
2186 | int num_packet2s = 0; |
||
2187 | |||
2188 | |||
2189 | uint32_t offset; |
||
2190 | |||
2191 | |||
2192 | int dwords; |
||
2193 | u32 obj_size; |
||
2194 | |||
2195 | |||
2196 | u64 state_gpu_addr = 0; |
||
2197 | |||
2198 | |||
2199 | u32 ps_offset; |
||
2200 | u32 vb_offset; |
||
2201 | |||
2202 | |||
2203 | int ps_size; |
||
2204 | |||
2205 | |||
2206 | void *ptr; |
||
2207 | |||
2208 | |||
2209 | |||
2210 | |||
2211 | |||
2212 | |||
2213 | |||
2214 | |||
2215 | offset = rdev->mc.vram_start; |
||
1430 | serge | 2216 | ps_size = R600_solid_ps(rdev, ps_shader); |
1428 | serge | 2217 | vs_size = R600_solid_vs(rdev, vs_shader); |
2218 | |||
2219 | |||
2220 | state_len = r7xx_default_size; |
||
2221 | else |
||
2222 | state_len = r6xx_default_size; |
||
2223 | |||
2224 | |||
2225 | |||
2226 | |||
2227 | packet2s[num_packet2s++] = PACKET2(0); |
||
2228 | dwords++; |
||
2229 | } |
||
2230 | |||
2231 | |||
2232 | obj_size = ALIGN(obj_size, 256); |
||
2233 | |||
2234 | |||
2235 | obj_size += vs_size * 4; |
||
2236 | obj_size = ALIGN(obj_size, 256); |
||
2237 | |||
2238 | |||
2239 | obj_size += ps_size * 4; |
||
2240 | obj_size = ALIGN(obj_size, 256); |
||
2241 | |||
2242 | |||
2243 | obj_size += 32*4; |
||
2244 | obj_size = ALIGN(obj_size, 256); |
||
2245 | |||
2246 | |||
1963 | serge | 2247 | RADEON_GEM_DOMAIN_VRAM, &state_obj); |
2248 | if (r) { |
||
1428 | serge | 2249 | DRM_ERROR("r600 failed to allocate state buffer\n"); |
2250 | return r; |
||
2251 | } |
||
2252 | |||
2253 | |||
2254 | obj_size, vs_offset, ps_offset); |
||
2255 | |||
2256 | |||
2257 | &state_gpu_addr); |
||
2258 | if (r) { |
||
2259 | DRM_ERROR("failed to pin state object %d\n", r); |
||
2260 | return r; |
||
2261 | }; |
||
2262 | |||
2263 | |||
2264 | if (r) { |
||
2265 | DRM_ERROR("failed to map state object %d\n", r); |
||
2266 | return r; |
||
2267 | }; |
||
2268 | |||
2269 | |||
2270 | memcpy_toio(ptr + state_offset, |
||
2271 | r7xx_default_state, state_len * 4); |
||
2272 | else |
||
2273 | memcpy_toio(ptr + state_offset, |
||
2274 | r6xx_default_state, state_len * 4); |
||
2275 | |||
2276 | |||
2277 | memcpy_toio(ptr + state_offset + (state_len * 4), |
||
2278 | packet2s, num_packet2s * 4); |
||
2279 | |||
2280 | |||
2281 | memcpy(ptr + ps_offset, ps_shader, ps_size * 4); |
||
2282 | |||
2283 | |||
2284 | |||
2285 | |||
2286 | |||
2287 | vb[1] = (float)64; |
||
2288 | |||
2289 | |||
2290 | vb[3] = (float)(64+128); |
||
2291 | |||
2292 | |||
2293 | vb[5] = (float)(64+128); |
||
2294 | |||
2295 | |||
2296 | int vb_size = vb_index * 8; |
||
2297 | int vtx_num_entries = vb_size / 4; |
||
2298 | |||
2299 | |||
2300 | |||
2301 | |||
2302 | if (r) { |
||
2303 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
2304 | return r; |
||
2305 | } |
||
2306 | |||
2307 | |||
2308 | |||
2309 | |||
2310 | |||
2311 | u32 sq_pgm_resources; |
||
2312 | |||
2313 | |||
2314 | |||
2315 | |||
2316 | |||
2317 | |||
2318 | gpu_addr = state_gpu_addr + vs_offset; |
||
2319 | |||
2320 | |||
2321 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2322 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
2323 | |||
2324 | |||
2325 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2326 | radeon_ring_write(rdev, sq_pgm_resources); |
||
2327 | |||
2328 | |||
2329 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2330 | radeon_ring_write(rdev, 0); |
||
2331 | |||
2332 | |||
2333 | |||
2334 | |||
2335 | gpu_addr = state_gpu_addr + ps_offset; |
||
2336 | |||
2337 | |||
2338 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2339 | radeon_ring_write(rdev, gpu_addr >> 8); |
||
2340 | |||
2341 | |||
2342 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2343 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
||
2344 | |||
2345 | |||
2346 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2347 | radeon_ring_write(rdev, 2); |
||
2348 | |||
2349 | |||
2350 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
||
2351 | radeon_ring_write(rdev, 0); |
||
2352 | |||
2353 | |||
2354 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
||
2355 | |||
2356 | |||
2357 | |||
2358 | rdev->mc.vram_start); |
||
1430 | serge | 2359 | |
1428 | serge | 2360 | |
2361 | |||
2362 | |||
2363 | |||
2364 | radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2); |
||
2365 | EFLOAT(0.0f); /* r */ |
||
2366 | EFLOAT(1.0f); /* g */ |
||
2367 | EFLOAT(0.0f); /* b */ |
||
2368 | EFLOAT(1.0f); /* a */ |
||
2369 | |||
2370 | |||
2371 | |||
2372 | |||
2373 | |||
2374 | |||
2375 | |||
2376 | |||
2377 | radeon_ring_write(rdev, 0x460); |
||
2378 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */ |
||
2379 | radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */ |
||
2380 | radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */ |
||
2381 | radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */ |
||
2382 | radeon_ring_write(rdev, 0); |
||
2383 | radeon_ring_write(rdev, 0); |
||
2384 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
||
2385 | |||
2386 | |||
2387 | (rdev->family == CHIP_RV620) || |
||
2388 | (rdev->family == CHIP_RS780) || |
||
2389 | (rdev->family == CHIP_RS880) || |
||
2390 | (rdev->family == CHIP_RV710)) |
||
2391 | cp_set_surface_sync(rdev, |
||
2392 | PACKET3_TC_ACTION_ENA, 24, gpu_addr); |
||
2393 | else |
||
2394 | cp_set_surface_sync(rdev, |
||
2395 | PACKET3_VC_ACTION_ENA, 24, gpu_addr); |
||
2396 | |||
2397 | |||
2398 | |||
2399 | |||
2400 | 1024*4*512, offset); |
||
2401 | |||
2402 | |||
2403 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); |
||
2404 | /* wait for 3D idle clean */ |
||
2405 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
2406 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
||
2407 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
||
2408 | |||
2409 | |||
2410 | |||
2411 | |||
2412 | |||
2413 | |||
2414 | return r; |
||
2415 | } |
||
2416 | |||
1963 | serge | 2417 | |
2418 |