WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/rdisplay.c

Rev	Author	Line No.	Line
1221	serge	1
		2	#include
		3	#include
		4	#include "radeon_drm.h"
		5	#include "radeon.h"
		6	#include "radeon_object.h"
		7	#include "display.h"
1246	serge	8
1221	serge	9
1428	serge	10
		11
		12
1246	serge	13
1221	serge	14
1246	serge	15	static void __stdcall move_cursor(cursor_t *cursor, int x, int y);
		16
1221	serge	17
1313	serge	18
		19
		20	{};
		21
		22
1221	serge	23	{
		24	struct radeon_device *rdev;
		25
		26
		27	uint32_t *src;
		28
		29
		30	int r;
		31
		32
		33
		34
1404	serge	35	false, RADEON_GEM_DOMAIN_VRAM, &cursor->robj);
		36
1221	serge	37
		38	return r;
		39
		40
1404	serge	41	if (unlikely(r != 0))
		42	return r;
		43
1221	serge	44
1404	serge	45	if (unlikely(r != 0))
		46	return r;
		47
		48
		49	if (r) {
1221	serge	50	DRM_ERROR("radeon: failed to map cursor (%d).\n", r);
		51	return r;
		52	};
		53
		54
		55
		56
		57	{
		58	for(j = 0; j < 32; j++)
		59	bits++ = src++;
		60	for(j = 32; j < CURSOR_WIDTH; j++)
1230	serge	61	*bits++ = 0;
1221	serge	62	}
		63	for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
		64	*bits++ = 0;
		65
		66
1404	serge	67
1221	serge	68
1403	serge	69
1313	serge	70
1221	serge	71	};
		72
		73
1313	serge	74	{
		75	list_del(&cursor->list);
		76	radeon_bo_unpin(cursor->robj);
1404	serge	77	KernelFree(cursor->data);
1313	serge	78	__DestroyObject(cursor);
		79	};
		80
		81
		82
1246	serge	83	{
1221	serge	84	struct radeon_device rdev = (struct radeon_device )rdisplay->ddev->dev_private;
1246	serge	85
1230	serge	86
		87	WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL);
1246	serge	88	WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN \|
1230	serge	89	(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
		90	} else {
		91	WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
1275	serge	92	WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN \|
1230	serge	93	(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
		94	~(RADEON_CRTC_CUR_EN \| RADEON_CRTC_CUR_MODE_MASK));
		95	}
		96	}
		97
		98
		99	{
1221	serge	100	struct radeon_device *rdev;
		101	cursor_t *old;
		102	uint32_t gpu_addr;
		103
		104
		105
		106
1230	serge	107
1221	serge	108
1230	serge	109	gpu_addr = radeon_bo_gpu_offset(cursor->robj);
1404	serge	110
1221	serge	111
		112	WREG32(AVIVO_D1CUR_SURFACE_ADDRESS, gpu_addr);
1246	serge	113	else {
1221	serge	114	WREG32(RADEON_CUR_OFFSET, gpu_addr - rdev->mc.vram_location);
1246	serge	115	}
1221	serge	116
1230	serge	117
1221	serge	118	};
		119
		120
1246	serge	121	{
		122	struct radeon_device *rdev;
		123
1221	serge	124
1246	serge	125
		126
		127
		128
		129	cur_lock = RREG32(AVIVO_D1CUR_UPDATE);
		130	if (lock)
		131	cur_lock \|= AVIVO_D1CURSOR_UPDATE_LOCK;
		132	else
		133	cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
		134	WREG32(AVIVO_D1CUR_UPDATE, cur_lock);
		135	} else {
		136	cur_lock = RREG32(RADEON_CUR_OFFSET);
		137	if (lock)
		138	cur_lock \|= RADEON_CUR_LOCK;
		139	else
		140	cur_lock &= ~RADEON_CUR_LOCK;
		141	WREG32(RADEON_CUR_OFFSET, cur_lock);
		142	}
		143	}
		144
		145
		146
1230	serge	147	{
1221	serge	148	struct radeon_device *rdev;
1230	serge	149	rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
		150
1221	serge	151
1230	serge	152	int hot_y = cursor->hot_y;
		153
1221	serge	154
1246	serge	155	if (ASIC_IS_AVIVO(rdev))
1221	serge	156	{
		157	int w = 32;
		158
		159
1246	serge	160	WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) \| hot_y);
		161	WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) \| 31);
		162	} else {
1275	serge	163
1404	serge	164
1246	serge	165	int xorg =0, yorg=0;
1404	serge	166
1221	serge	167
1404	serge	168	y = y - hot_y;
		169
		170
		171	{
		172	xorg = -x + 1;
		173	x = 0;
		174	}
		175
		176
		177	{
		178	yorg = -hot_y + 1;
		179	y = 0;
		180	};
		181
		182
1246	serge	183	(RADEON_CUR_LOCK \| (xorg << 16) \| yorg ));
1404	serge	184	WREG32(RADEON_CUR_HORZ_VERT_POSN,
1246	serge	185	(RADEON_CUR_LOCK \| (x << 16) \| y));
1221	serge	186
		187
1404	serge	188
1246	serge	189
1221	serge	190	WREG32(RADEON_CUR_OFFSET,
1246	serge	191	(gpu_addr - rdev->mc.vram_location + (yorg * 256)));
1404	serge	192	}
1221	serge	193	radeon_lock_cursor(false);
1246	serge	194	}
1221	serge	195
		196
1230	serge	197	{
		198	};
		199
1221	serge	200
1233	serge	201
1404	serge	202	{
1233	serge	203	struct drm_device *dev;
1275	serge	204
1246	serge	205
1275	serge	206	bool retval = true;
1268	serge	207	u32_t ifl;
1246	serge	208
1233	serge	209
		210
		211
		212
		213
1239	serge	214
1233	serge	215
1246	serge	216	{
		217	list_for_each_entry(cursor, &rdisplay->cursors, list)
1275	serge	218	{
		219	init_cursor(cursor);
		220	};
		221
1233	serge	222
1275	serge	223	rdisplay->init_cursor = init_cursor;
		224	rdisplay->select_cursor = select_cursor;
		225	rdisplay->show_cursor = NULL;
		226	rdisplay->move_cursor = move_cursor;
		227	rdisplay->restore_cursor = restore_cursor;
		228	rdisplay->disable_mouse = disable_mouse;
1313	serge	229
1233	serge	230
1246	serge	231	radeon_show_cursor();
		232	};
		233	safe_sti(ifl);
		234
		235
1233	serge	236
		237
1239	serge	238	};
1233	serge	239
		240
		241
1404	serge	242	{
		243	#define BYTES_PER_LONG (BITS_PER_LONG/8)
		244	#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
		245	int fb_info_size = sizeof(struct fb_info);
		246	struct fb_info *info;
		247	char *p;
		248
1233	serge	249
1404	serge	250	fb_info_size += PADDING;
		251
		252
		253
		254
		255	return NULL;
		256
		257
		258
		259
		260	info->par = p + fb_info_size;
		261
		262
		263	#undef PADDING
		264	#undef BYTES_PER_LONG
		265	}
		266
		267
		268	{
		269	kfree(info);
		270	}
		271
		272
1428	serge	273	# define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28)
		274	# define R5XX_GMC_WR_MSK_DIS (1 << 30)
		275	# define R5XX_ROP3_P 0x00f00000
		276
		277
		278	#define R5XX_SC_BOTTOM_RIGHT 0x16f0
		279	# define R5XX_SC_SIGN_MASK_LO 0x8000
		280	# define R5XX_SC_SIGN_MASK_HI 0x80000000
		281
		282
		283	# define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
		284	# define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
		285
		286
		287
		288	{
		289
		290
		291	uint32_t offset;
		292
		293
		294
		295
		296
		297
		298	offset = rdev->mc.vram_location;
		299
		300
		301	if (r) {
		302	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		303	return r;
		304	}
		305	radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0));
		306	radeon_ring_write(rdev, 0);
		307
		308
		309	radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX \|
		310	RADEON_DEFAULT_SC_BOTTOM_MAX);
		311
		312
		313	radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX \|
		314	RADEON_DEFAULT_SC_BOTTOM_MAX);
		315
		316
		317	radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		318	RADEON_GMC_BRUSH_SOLID_COLOR \|
		319	RADEON_GMC_DST_32BPP \|
		320	RADEON_GMC_SRC_DATATYPE_COLOR \|
		321	R5XX_GMC_CLR_CMP_CNTL_DIS \|
		322	R5XX_GMC_WR_MSK_DIS \|
		323	R5XX_ROP3_P);
		324
		325
		326	radeon_ring_write(rdev, 0x0000FF00);
		327	radeon_ring_write(rdev, (64<<16)\|64);
		328	radeon_ring_write(rdev, (128<<16)\|128);
		329
		330
		331	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		332	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		333	radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN \|
		334	RADEON_WAIT_HOST_IDLECLEAN \|
		335	RADEON_WAIT_DMA_GUI_IDLE);
		336
		337
		338
		339
		340	return r;
		341	}
		342
		343
		344
		345	#include "r600_reg_r6xx.h"
		346	#include "r600d.h"
		347
		348
		349	{
		350	0xc0002400,
		351	0x00000000,
		352	0xc0012800,
		353	0x80000000,
		354	0x80000000,
		355	0xc0004600,
		356	0x00000016,
		357	0xc0016800,
		358	0x00000010,
		359	0x00028000,
		360	0xc0016800,
		361	0x00000010,
		362	0x00008000,
		363	0xc0016800,
		364	0x00000542,
		365	0x07000003,
		366	0xc0016800,
		367	0x000005c5,
		368	0x00000000,
		369	0xc0016800,
		370	0x00000363,
		371	0x00000000,
		372	0xc0016800,
		373	0x0000060c,
		374	0x82000000,
		375	0xc0016800,
		376	0x0000060e,
		377	0x01020204,
		378	0xc0016f00,
		379	0x00000000,
		380	0x00000000,
		381	0xc0016f00,
		382	0x00000001,
		383	0x00000000,
		384	0xc0096900,
		385	0x0000022a,
		386	0x00000000,
		387	0x00000000,
		388	0x00000000,
		389	0x00000000,
		390	0x00000000,
		391	0x00000000,
		392	0x00000000,
		393	0x00000000,
		394	0x00000000,
		395	0xc0016900,
		396	0x00000004,
		397	0x00000000,
		398	0xc0016900,
		399	0x0000000a,
		400	0x00000000,
		401	0xc0016900,
		402	0x0000000b,
		403	0x00000000,
		404	0xc0016900,
		405	0x0000010c,
		406	0x00000000,
		407	0xc0016900,
		408	0x0000010d,
		409	0x00000000,
		410	0xc0016900,
		411	0x00000200,
		412	0x00000000,
		413	0xc0016900,
		414	0x00000343,
		415	0x00000060,
		416	0xc0016900,
		417	0x00000344,
		418	0x00000040,
		419	0xc0016900,
		420	0x00000351,
		421	0x0000aa00,
		422	0xc0016900,
		423	0x00000104,
		424	0x00000000,
		425	0xc0016900,
		426	0x0000010e,
		427	0x00000000,
		428	0xc0046900,
		429	0x00000105,
		430	0x00000000,
		431	0x00000000,
		432	0x00000000,
		433	0x00000000,
		434	0xc0036900,
		435	0x00000109,
		436	0x00000000,
		437	0x00000000,
		438	0x00000000,
		439	0xc0046900,
		440	0x0000030c,
		441	0x01000000,
		442	0x00000000,
		443	0x00000000,
		444	0x00000000,
		445	0xc0046900,
		446	0x00000048,
		447	0x3f800000,
		448	0x00000000,
		449	0x3f800000,
		450	0x3f800000,
		451	0xc0016900,
		452	0x0000008e,
		453	0x0000000f,
		454	0xc0016900,
		455	0x00000080,
		456	0x00000000,
		457	0xc0016900,
		458	0x00000083,
		459	0x0000ffff,
		460	0xc0016900,
		461	0x00000084,
		462	0x00000000,
		463	0xc0016900,
		464	0x00000085,
		465	0x20002000,
		466	0xc0016900,
		467	0x00000086,
		468	0x00000000,
		469	0xc0016900,
		470	0x00000087,
		471	0x20002000,
		472	0xc0016900,
		473	0x00000088,
		474	0x00000000,
		475	0xc0016900,
		476	0x00000089,
		477	0x20002000,
		478	0xc0016900,
		479	0x0000008a,
		480	0x00000000,
		481	0xc0016900,
		482	0x0000008b,
		483	0x20002000,
		484	0xc0016900,
		485	0x0000008c,
		486	0x00000000,
		487	0xc0016900,
		488	0x00000094,
		489	0x80000000,
		490	0xc0016900,
		491	0x00000095,
		492	0x20002000,
		493	0xc0026900,
		494	0x000000b4,
		495	0x00000000,
		496	0x3f800000,
		497	0xc0016900,
		498	0x00000096,
		499	0x80000000,
		500	0xc0016900,
		501	0x00000097,
		502	0x20002000,
		503	0xc0026900,
		504	0x000000b6,
		505	0x00000000,
		506	0x3f800000,
		507	0xc0016900,
		508	0x00000098,
		509	0x80000000,
		510	0xc0016900,
		511	0x00000099,
		512	0x20002000,
		513	0xc0026900,
		514	0x000000b8,
		515	0x00000000,
		516	0x3f800000,
		517	0xc0016900,
		518	0x0000009a,
		519	0x80000000,
		520	0xc0016900,
		521	0x0000009b,
		522	0x20002000,
		523	0xc0026900,
		524	0x000000ba,
		525	0x00000000,
		526	0x3f800000,
		527	0xc0016900,
		528	0x0000009c,
		529	0x80000000,
		530	0xc0016900,
		531	0x0000009d,
		532	0x20002000,
		533	0xc0026900,
		534	0x000000bc,
		535	0x00000000,
		536	0x3f800000,
		537	0xc0016900,
		538	0x0000009e,
		539	0x80000000,
		540	0xc0016900,
		541	0x0000009f,
		542	0x20002000,
		543	0xc0026900,
		544	0x000000be,
		545	0x00000000,
		546	0x3f800000,
		547	0xc0016900,
		548	0x000000a0,
		549	0x80000000,
		550	0xc0016900,
		551	0x000000a1,
		552	0x20002000,
		553	0xc0026900,
		554	0x000000c0,
		555	0x00000000,
		556	0x3f800000,
		557	0xc0016900,
		558	0x000000a2,
		559	0x80000000,
		560	0xc0016900,
		561	0x000000a3,
		562	0x20002000,
		563	0xc0026900,
		564	0x000000c2,
		565	0x00000000,
		566	0x3f800000,
		567	0xc0016900,
		568	0x000000a4,
		569	0x80000000,
		570	0xc0016900,
		571	0x000000a5,
		572	0x20002000,
		573	0xc0026900,
		574	0x000000c4,
		575	0x00000000,
		576	0x3f800000,
		577	0xc0016900,
		578	0x000000a6,
		579	0x80000000,
		580	0xc0016900,
		581	0x000000a7,
		582	0x20002000,
		583	0xc0026900,
		584	0x000000c6,
		585	0x00000000,
		586	0x3f800000,
		587	0xc0016900,
		588	0x000000a8,
		589	0x80000000,
		590	0xc0016900,
		591	0x000000a9,
		592	0x20002000,
		593	0xc0026900,
		594	0x000000c8,
		595	0x00000000,
		596	0x3f800000,
		597	0xc0016900,
		598	0x000000aa,
		599	0x80000000,
		600	0xc0016900,
		601	0x000000ab,
		602	0x20002000,
		603	0xc0026900,
		604	0x000000ca,
		605	0x00000000,
		606	0x3f800000,
		607	0xc0016900,
		608	0x000000ac,
		609	0x80000000,
		610	0xc0016900,
		611	0x000000ad,
		612	0x20002000,
		613	0xc0026900,
		614	0x000000cc,
		615	0x00000000,
		616	0x3f800000,
		617	0xc0016900,
		618	0x000000ae,
		619	0x80000000,
		620	0xc0016900,
		621	0x000000af,
		622	0x20002000,
		623	0xc0026900,
		624	0x000000ce,
		625	0x00000000,
		626	0x3f800000,
		627	0xc0016900,
		628	0x000000b0,
		629	0x80000000,
		630	0xc0016900,
		631	0x000000b1,
		632	0x20002000,
		633	0xc0026900,
		634	0x000000d0,
		635	0x00000000,
		636	0x3f800000,
		637	0xc0016900,
		638	0x000000b2,
		639	0x80000000,
		640	0xc0016900,
		641	0x000000b3,
		642	0x20002000,
		643	0xc0026900,
		644	0x000000d2,
		645	0x00000000,
		646	0x3f800000,
		647	0xc0016900,
		648	0x00000293,
		649	0x00004010,
		650	0xc0016900,
		651	0x00000300,
		652	0x00000000,
		653	0xc0016900,
		654	0x00000301,
		655	0x00000000,
		656	0xc0016900,
		657	0x00000312,
		658	0xffffffff,
		659	0xc0016900,
		660	0x00000307,
		661	0x00000000,
		662	0xc0016900,
		663	0x00000308,
		664	0x00000000,
		665	0xc0016900,
		666	0x00000283,
		667	0x00000000,
		668	0xc0016900,
		669	0x00000292,
		670	0x00000000,
		671	0xc0066900,
		672	0x0000010f,
		673	0x00000000,
		674	0x00000000,
		675	0x00000000,
		676	0x00000000,
		677	0x00000000,
		678	0x00000000,
		679	0xc0016900,
		680	0x00000206,
		681	0x00000000,
		682	0xc0016900,
		683	0x00000207,
		684	0x00000000,
		685	0xc0016900,
		686	0x00000208,
		687	0x00000000,
		688	0xc0046900,
		689	0x00000303,
		690	0x3f800000,
		691	0x3f800000,
		692	0x3f800000,
		693	0x3f800000,
		694	0xc0016900,
		695	0x00000205,
		696	0x00000004,
		697	0xc0016900,
		698	0x00000280,
		699	0x00000000,
		700	0xc0016900,
		701	0x00000281,
		702	0x00000000,
		703	0xc0016900,
		704	0x0000037e,
		705	0x00000000,
		706	0xc0016900,
		707	0x00000382,
		708	0x00000000,
		709	0xc0016900,
		710	0x00000380,
		711	0x00000000,
		712	0xc0016900,
		713	0x00000383,
		714	0x00000000,
		715	0xc0016900,
		716	0x00000381,
		717	0x00000000,
		718	0xc0016900,
		719	0x00000282,
		720	0x00000008,
		721	0xc0016900,
		722	0x00000302,
		723	0x0000002d,
		724	0xc0016900,
		725	0x0000037f,
		726	0x00000000,
		727	0xc0016900,
		728	0x000001b2,
		729	0x00000000,
		730	0xc0016900,
		731	0x000001b6,
		732	0x00000000,
		733	0xc0016900,
		734	0x000001b7,
		735	0x00000000,
		736	0xc0016900,
		737	0x000001b8,
		738	0x00000000,
		739	0xc0016900,
		740	0x000001b9,
		741	0x00000000,
		742	0xc0016900,
		743	0x00000225,
		744	0x00000000,
		745	0xc0016900,
		746	0x00000229,
		747	0x00000000,
		748	0xc0016900,
		749	0x00000237,
		750	0x00000000,
		751	0xc0016900,
		752	0x00000100,
		753	0x00000800,
		754	0xc0016900,
		755	0x00000101,
		756	0x00000000,
		757	0xc0016900,
		758	0x00000102,
		759	0x00000000,
		760	0xc0016900,
		761	0x000002a8,
		762	0x00000000,
		763	0xc0016900,
		764	0x000002a9,
		765	0x00000000,
		766	0xc0016900,
		767	0x00000103,
		768	0x00000000,
		769	0xc0016900,
		770	0x00000284,
		771	0x00000000,
		772	0xc0016900,
		773	0x00000290,
		774	0x00000000,
		775	0xc0016900,
		776	0x00000285,
		777	0x00000000,
		778	0xc0016900,
		779	0x00000286,
		780	0x00000000,
		781	0xc0016900,
		782	0x00000287,
		783	0x00000000,
		784	0xc0016900,
		785	0x00000288,
		786	0x00000000,
		787	0xc0016900,
		788	0x00000289,
		789	0x00000000,
		790	0xc0016900,
		791	0x0000028a,
		792	0x00000000,
		793	0xc0016900,
		794	0x0000028b,
		795	0x00000000,
		796	0xc0016900,
		797	0x0000028c,
		798	0x00000000,
		799	0xc0016900,
		800	0x0000028d,
		801	0x00000000,
		802	0xc0016900,
		803	0x0000028e,
		804	0x00000000,
		805	0xc0016900,
		806	0x0000028f,
		807	0x00000000,
		808	0xc0016900,
		809	0x000002a1,
		810	0x00000000,
		811	0xc0016900,
		812	0x000002a5,
		813	0x00000000,
		814	0xc0016900,
		815	0x000002ac,
		816	0x00000000,
		817	0xc0016900,
		818	0x000002ad,
		819	0x00000000,
		820	0xc0016900,
		821	0x000002ae,
		822	0x00000000,
		823	0xc0016900,
		824	0x000002c8,
		825	0x00000000,
		826	0xc0016900,
		827	0x00000206,
		828	0x00000100,
		829	0xc0016900,
		830	0x00000204,
		831	0x00010000,
		832	0xc0036e00,
		833	0x00000000,
		834	0x00000012,
		835	0x00000000,
		836	0x00000000,
		837	0xc0016900,
		838	0x0000008f,
		839	0x0000000f,
		840	0xc0016900,
		841	0x000001e8,
		842	0x00000001,
		843	0xc0016900,
		844	0x00000202,
		845	0x00cc0000,
		846	0xc0016900,
		847	0x00000205,
		848	0x00000244,
		849	0xc0016900,
		850	0x00000203,
		851	0x00000210,
		852	0xc0016900,
		853	0x000001b1,
		854	0x00000000,
		855	0xc0016900,
		856	0x00000185,
		857	0x00000000,
		858	0xc0016900,
		859	0x000001b3,
		860	0x00000001,
		861	0xc0016900,
		862	0x000001b4,
		863	0x00000000,
		864	0xc0016900,
		865	0x00000191,
		866	0x00000b00,
		867	0xc0016900,
		868	0x000001b5,
		869	0x00000000,
		870	};
		871
		872
		873
		874
		875	{
		876	0xc0012800,
		877	0x80000000,
		878	0x80000000,
		879	0xc0004600,
		880	0x00000016,
		881	0xc0016800,
		882	0x00000010,
		883	0x00028000,
		884	0xc0016800,
		885	0x00000010,
		886	0x00008000,
		887	0xc0016800,
		888	0x00000542,
		889	0x07000002,
		890	0xc0016800,
		891	0x000005c5,
		892	0x00000000,
		893	0xc0016800,
		894	0x00000363,
		895	0x00004000,
		896	0xc0016800,
		897	0x0000060c,
		898	0x00000000,
		899	0xc0016800,
		900	0x0000060e,
		901	0x00420204,
		902	0xc0016f00,
		903	0x00000000,
		904	0x00000000,
		905	0xc0016f00,
		906	0x00000001,
		907	0x00000000,
		908	0xc0096900,
		909	0x0000022a,
		910	0x00000000,
		911	0x00000000,
		912	0x00000000,
		913	0x00000000,
		914	0x00000000,
		915	0x00000000,
		916	0x00000000,
		917	0x00000000,
		918	0x00000000,
		919	0xc0016900,
		920	0x00000004,
		921	0x00000000,
		922	0xc0016900,
		923	0x0000000a,
		924	0x00000000,
		925	0xc0016900,
		926	0x0000000b,
		927	0x00000000,
		928	0xc0016900,
		929	0x0000010c,
		930	0x00000000,
		931	0xc0016900,
		932	0x0000010d,
		933	0x00000000,
		934	0xc0016900,
		935	0x00000200,
		936	0x00000000,
		937	0xc0016900,
		938	0x00000343,
		939	0x00000060,
		940	0xc0016900,
		941	0x00000344,
		942	0x00000000,
		943	0xc0016900,
		944	0x00000351,
		945	0x0000aa00,
		946	0xc0016900,
		947	0x00000104,
		948	0x00000000,
		949	0xc0016900,
		950	0x0000010e,
		951	0x00000000,
		952	0xc0046900,
		953	0x00000105,
		954	0x00000000,
		955	0x00000000,
		956	0x00000000,
		957	0x00000000,
		958	0xc0046900,
		959	0x0000030c,
		960	0x01000000,
		961	0x00000000,
		962	0x00000000,
		963	0x00000000,
		964	0xc0016900,
		965	0x0000008e,
		966	0x0000000f,
		967	0xc0016900,
		968	0x00000080,
		969	0x00000000,
		970	0xc0016900,
		971	0x00000083,
		972	0x0000ffff,
		973	0xc0016900,
		974	0x00000084,
		975	0x00000000,
		976	0xc0016900,
		977	0x00000085,
		978	0x20002000,
		979	0xc0016900,
		980	0x00000086,
		981	0x00000000,
		982	0xc0016900,
		983	0x00000087,
		984	0x20002000,
		985	0xc0016900,
		986	0x00000088,
		987	0x00000000,
		988	0xc0016900,
		989	0x00000089,
		990	0x20002000,
		991	0xc0016900,
		992	0x0000008a,
		993	0x00000000,
		994	0xc0016900,
		995	0x0000008b,
		996	0x20002000,
		997	0xc0016900,
		998	0x0000008c,
		999	0xaaaaaaaa,
		1000	0xc0016900,
		1001	0x00000094,
		1002	0x80000000,
		1003	0xc0016900,
		1004	0x00000095,
		1005	0x20002000,
		1006	0xc0026900,
		1007	0x000000b4,
		1008	0x00000000,
		1009	0x3f800000,
		1010	0xc0016900,
		1011	0x00000096,
		1012	0x80000000,
		1013	0xc0016900,
		1014	0x00000097,
		1015	0x20002000,
		1016	0xc0026900,
		1017	0x000000b6,
		1018	0x00000000,
		1019	0x3f800000,
		1020	0xc0016900,
		1021	0x00000098,
		1022	0x80000000,
		1023	0xc0016900,
		1024	0x00000099,
		1025	0x20002000,
		1026	0xc0026900,
		1027	0x000000b8,
		1028	0x00000000,
		1029	0x3f800000,
		1030	0xc0016900,
		1031	0x0000009a,
		1032	0x80000000,
		1033	0xc0016900,
		1034	0x0000009b,
		1035	0x20002000,
		1036	0xc0026900,
		1037	0x000000ba,
		1038	0x00000000,
		1039	0x3f800000,
		1040	0xc0016900,
		1041	0x0000009c,
		1042	0x80000000,
		1043	0xc0016900,
		1044	0x0000009d,
		1045	0x20002000,
		1046	0xc0026900,
		1047	0x000000bc,
		1048	0x00000000,
		1049	0x3f800000,
		1050	0xc0016900,
		1051	0x0000009e,
		1052	0x80000000,
		1053	0xc0016900,
		1054	0x0000009f,
		1055	0x20002000,
		1056	0xc0026900,
		1057	0x000000be,
		1058	0x00000000,
		1059	0x3f800000,
		1060	0xc0016900,
		1061	0x000000a0,
		1062	0x80000000,
		1063	0xc0016900,
		1064	0x000000a1,
		1065	0x20002000,
		1066	0xc0026900,
		1067	0x000000c0,
		1068	0x00000000,
		1069	0x3f800000,
		1070	0xc0016900,
		1071	0x000000a2,
		1072	0x80000000,
		1073	0xc0016900,
		1074	0x000000a3,
		1075	0x20002000,
		1076	0xc0026900,
		1077	0x000000c2,
		1078	0x00000000,
		1079	0x3f800000,
		1080	0xc0016900,
		1081	0x000000a4,
		1082	0x80000000,
		1083	0xc0016900,
		1084	0x000000a5,
		1085	0x20002000,
		1086	0xc0026900,
		1087	0x000000c4,
		1088	0x00000000,
		1089	0x3f800000,
		1090	0xc0016900,
		1091	0x000000a6,
		1092	0x80000000,
		1093	0xc0016900,
		1094	0x000000a7,
		1095	0x20002000,
		1096	0xc0026900,
		1097	0x000000c6,
		1098	0x00000000,
		1099	0x3f800000,
		1100	0xc0016900,
		1101	0x000000a8,
		1102	0x80000000,
		1103	0xc0016900,
		1104	0x000000a9,
		1105	0x20002000,
		1106	0xc0026900,
		1107	0x000000c8,
		1108	0x00000000,
		1109	0x3f800000,
		1110	0xc0016900,
		1111	0x000000aa,
		1112	0x80000000,
		1113	0xc0016900,
		1114	0x000000ab,
		1115	0x20002000,
		1116	0xc0026900,
		1117	0x000000ca,
		1118	0x00000000,
		1119	0x3f800000,
		1120	0xc0016900,
		1121	0x000000ac,
		1122	0x80000000,
		1123	0xc0016900,
		1124	0x000000ad,
		1125	0x20002000,
		1126	0xc0026900,
		1127	0x000000cc,
		1128	0x00000000,
		1129	0x3f800000,
		1130	0xc0016900,
		1131	0x000000ae,
		1132	0x80000000,
		1133	0xc0016900,
		1134	0x000000af,
		1135	0x20002000,
		1136	0xc0026900,
		1137	0x000000ce,
		1138	0x00000000,
		1139	0x3f800000,
		1140	0xc0016900,
		1141	0x000000b0,
		1142	0x80000000,
		1143	0xc0016900,
		1144	0x000000b1,
		1145	0x20002000,
		1146	0xc0026900,
		1147	0x000000d0,
		1148	0x00000000,
		1149	0x3f800000,
		1150	0xc0016900,
		1151	0x000000b2,
		1152	0x80000000,
		1153	0xc0016900,
		1154	0x000000b3,
		1155	0x20002000,
		1156	0xc0026900,
		1157	0x000000d2,
		1158	0x00000000,
		1159	0x3f800000,
		1160	0xc0016900,
		1161	0x00000293,
		1162	0x00514000,
		1163	0xc0016900,
		1164	0x00000300,
		1165	0x00000000,
		1166	0xc0016900,
		1167	0x00000301,
		1168	0x00000000,
		1169	0xc0016900,
		1170	0x00000312,
		1171	0xffffffff,
		1172	0xc0016900,
		1173	0x00000307,
		1174	0x00000000,
		1175	0xc0016900,
		1176	0x00000308,
		1177	0x00000000,
		1178	0xc0016900,
		1179	0x00000283,
		1180	0x00000000,
		1181	0xc0016900,
		1182	0x00000292,
		1183	0x00000000,
		1184	0xc0066900,
		1185	0x0000010f,
		1186	0x00000000,
		1187	0x00000000,
		1188	0x00000000,
		1189	0x00000000,
		1190	0x00000000,
		1191	0x00000000,
		1192	0xc0016900,
		1193	0x00000206,
		1194	0x00000000,
		1195	0xc0016900,
		1196	0x00000207,
		1197	0x00000000,
		1198	0xc0016900,
		1199	0x00000208,
		1200	0x00000000,
		1201	0xc0046900,
		1202	0x00000303,
		1203	0x3f800000,
		1204	0x3f800000,
		1205	0x3f800000,
		1206	0x3f800000,
		1207	0xc0016900,
		1208	0x00000205,
		1209	0x00000004,
		1210	0xc0016900,
		1211	0x00000280,
		1212	0x00000000,
		1213	0xc0016900,
		1214	0x00000281,
		1215	0x00000000,
		1216	0xc0016900,
		1217	0x0000037e,
		1218	0x00000000,
		1219	0xc0016900,
		1220	0x00000382,
		1221	0x00000000,
		1222	0xc0016900,
		1223	0x00000380,
		1224	0x00000000,
		1225	0xc0016900,
		1226	0x00000383,
		1227	0x00000000,
		1228	0xc0016900,
		1229	0x00000381,
		1230	0x00000000,
		1231	0xc0016900,
		1232	0x00000282,
		1233	0x00000008,
		1234	0xc0016900,
		1235	0x00000302,
		1236	0x0000002d,
		1237	0xc0016900,
		1238	0x0000037f,
		1239	0x00000000,
		1240	0xc0016900,
		1241	0x000001b2,
		1242	0x00000001,
		1243	0xc0016900,
		1244	0x000001b6,
		1245	0x00000000,
		1246	0xc0016900,
		1247	0x000001b7,
		1248	0x00000000,
		1249	0xc0016900,
		1250	0x000001b8,
		1251	0x00000000,
		1252	0xc0016900,
		1253	0x000001b9,
		1254	0x00000000,
		1255	0xc0016900,
		1256	0x00000225,
		1257	0x00000000,
		1258	0xc0016900,
		1259	0x00000229,
		1260	0x00000000,
		1261	0xc0016900,
		1262	0x00000237,
		1263	0x00000000,
		1264	0xc0016900,
		1265	0x00000100,
		1266	0x00000800,
		1267	0xc0016900,
		1268	0x00000101,
		1269	0x00000000,
		1270	0xc0016900,
		1271	0x00000102,
		1272	0x00000000,
		1273	0xc0016900,
		1274	0x000002a8,
		1275	0x00000000,
		1276	0xc0016900,
		1277	0x000002a9,
		1278	0x00000000,
		1279	0xc0016900,
		1280	0x00000103,
		1281	0x00000000,
		1282	0xc0016900,
		1283	0x00000284,
		1284	0x00000000,
		1285	0xc0016900,
		1286	0x00000290,
		1287	0x00000000,
		1288	0xc0016900,
		1289	0x00000285,
		1290	0x00000000,
		1291	0xc0016900,
		1292	0x00000286,
		1293	0x00000000,
		1294	0xc0016900,
		1295	0x00000287,
		1296	0x00000000,
		1297	0xc0016900,
		1298	0x00000288,
		1299	0x00000000,
		1300	0xc0016900,
		1301	0x00000289,
		1302	0x00000000,
		1303	0xc0016900,
		1304	0x0000028a,
		1305	0x00000000,
		1306	0xc0016900,
		1307	0x0000028b,
		1308	0x00000000,
		1309	0xc0016900,
		1310	0x0000028c,
		1311	0x00000000,
		1312	0xc0016900,
		1313	0x0000028d,
		1314	0x00000000,
		1315	0xc0016900,
		1316	0x0000028e,
		1317	0x00000000,
		1318	0xc0016900,
		1319	0x0000028f,
		1320	0x00000000,
		1321	0xc0016900,
		1322	0x000002a1,
		1323	0x00000000,
		1324	0xc0016900,
		1325	0x000002a5,
		1326	0x00000000,
		1327	0xc0016900,
		1328	0x000002ac,
		1329	0x00000000,
		1330	0xc0016900,
		1331	0x000002ad,
		1332	0x00000000,
		1333	0xc0016900,
		1334	0x000002ae,
		1335	0x00000000,
		1336	0xc0016900,
		1337	0x000002c8,
		1338	0x00000000,
		1339	0xc0016900,
		1340	0x00000206,
		1341	0x00000100,
		1342	0xc0016900,
		1343	0x00000204,
		1344	0x00010000,
		1345	0xc0036e00,
		1346	0x00000000,
		1347	0x00000012,
		1348	0x00000000,
		1349	0x00000000,
		1350	0xc0016900,
		1351	0x0000008f,
		1352	0x0000000f,
		1353	0xc0016900,
		1354	0x000001e8,
		1355	0x00000001,
		1356	0xc0016900,
		1357	0x00000202,
		1358	0x00cc0000,
		1359	0xc0016900,
		1360	0x00000205,
		1361	0x00000244,
		1362	0xc0016900,
		1363	0x00000203,
		1364	0x00000210,
		1365	0xc0016900,
		1366	0x000001b1,
		1367	0x00000000,
		1368	0xc0016900,
		1369	0x00000185,
		1370	0x00000000,
		1371	0xc0016900,
		1372	0x000001b3,
		1373	0x00000001,
		1374	0xc0016900,
		1375	0x000001b4,
		1376	0x00000000,
		1377	0xc0016900,
		1378	0x00000191,
		1379	0x00000b00,
		1380	0xc0016900,
		1381	0x000001b5,
		1382	0x00000000,
		1383	};
		1384
		1385
		1386	const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
		1387
		1388
		1389
		1390	int R600_solid_vs(struct radeon_device rdev, uint32_t shader);
		1391
		1392
		1393
		1394
		1395	static void
		1396	set_render_target(struct radeon_device *rdev, int format,
		1397	int w, int h, u64 gpu_addr)
		1398	{
		1399	u32 cb_color_info;
		1400	int pitch, slice;
		1401
		1402
		1403	if (h < 8)
		1404	h = 8;
		1405
		1406
		1407	pitch = (w / 8) - 1;
		1408	slice = ((w * h) / 64) - 1;
		1409
		1410
		1411	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1412	radeon_ring_write(rdev, gpu_addr >> 8);
		1413
		1414
		1415	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
		1416	radeon_ring_write(rdev, 2 << 0);
		1417	}
		1418
		1419
		1420	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1421	radeon_ring_write(rdev, (pitch << 0) \| (slice << 10));
		1422
		1423
		1424	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1425	radeon_ring_write(rdev, 0);
		1426
		1427
		1428	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1429	radeon_ring_write(rdev, cb_color_info);
		1430
		1431
		1432	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1433	radeon_ring_write(rdev, 0);
		1434
		1435
		1436	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1437	radeon_ring_write(rdev, 0);
		1438
		1439
		1440	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1441	radeon_ring_write(rdev, 0);
		1442	}
		1443
		1444
		1445
		1446	static void
		1447	cp_set_surface_sync(struct radeon_device *rdev,
		1448	u32 sync_type, u32 size,
		1449	u64 mc_addr)
		1450	{
		1451	u32 cp_coher_size;
		1452
		1453
		1454	cp_coher_size = 0xffffffff;
		1455	else
		1456	cp_coher_size = ((size + 255) >> 8);
		1457
		1458
		1459	radeon_ring_write(rdev, sync_type);
		1460	radeon_ring_write(rdev, cp_coher_size);
		1461	radeon_ring_write(rdev, mc_addr >> 8);
		1462	radeon_ring_write(rdev, 10); /* poll interval */
		1463	}
		1464
		1465
		1466	static void
		1467	set_default_state(struct radeon_device *rdev,
		1468	u64 state_gpu_addr, u32 state_len)
		1469	{
		1470	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
		1471	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
		1472	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
		1473	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
		1474	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
		1475	u64 gpu_addr;
		1476	int dwords;
		1477
		1478
		1479	case CHIP_R600:
		1480	num_ps_gprs = 192;
		1481	num_vs_gprs = 56;
		1482	num_temp_gprs = 4;
		1483	num_gs_gprs = 0;
		1484	num_es_gprs = 0;
		1485	num_ps_threads = 136;
		1486	num_vs_threads = 48;
		1487	num_gs_threads = 4;
		1488	num_es_threads = 4;
		1489	num_ps_stack_entries = 128;
		1490	num_vs_stack_entries = 128;
		1491	num_gs_stack_entries = 0;
		1492	num_es_stack_entries = 0;
		1493	break;
		1494	case CHIP_RV630:
		1495	case CHIP_RV635:
		1496	num_ps_gprs = 84;
		1497	num_vs_gprs = 36;
		1498	num_temp_gprs = 4;
		1499	num_gs_gprs = 0;
		1500	num_es_gprs = 0;
		1501	num_ps_threads = 144;
		1502	num_vs_threads = 40;
		1503	num_gs_threads = 4;
		1504	num_es_threads = 4;
		1505	num_ps_stack_entries = 40;
		1506	num_vs_stack_entries = 40;
		1507	num_gs_stack_entries = 32;
		1508	num_es_stack_entries = 16;
		1509	break;
		1510	case CHIP_RV610:
		1511	case CHIP_RV620:
		1512	case CHIP_RS780:
		1513	case CHIP_RS880:
		1514	default:
		1515	num_ps_gprs = 84;
		1516	num_vs_gprs = 36;
		1517	num_temp_gprs = 4;
		1518	num_gs_gprs = 0;
		1519	num_es_gprs = 0;
		1520	num_ps_threads = 136;
		1521	num_vs_threads = 48;
		1522	num_gs_threads = 4;
		1523	num_es_threads = 4;
		1524	num_ps_stack_entries = 40;
		1525	num_vs_stack_entries = 40;
		1526	num_gs_stack_entries = 32;
		1527	num_es_stack_entries = 16;
		1528	break;
		1529	case CHIP_RV670:
		1530	num_ps_gprs = 144;
		1531	num_vs_gprs = 40;
		1532	num_temp_gprs = 4;
		1533	num_gs_gprs = 0;
		1534	num_es_gprs = 0;
		1535	num_ps_threads = 136;
		1536	num_vs_threads = 48;
		1537	num_gs_threads = 4;
		1538	num_es_threads = 4;
		1539	num_ps_stack_entries = 40;
		1540	num_vs_stack_entries = 40;
		1541	num_gs_stack_entries = 32;
		1542	num_es_stack_entries = 16;
		1543	break;
		1544	case CHIP_RV770:
		1545	num_ps_gprs = 192;
		1546	num_vs_gprs = 56;
		1547	num_temp_gprs = 4;
		1548	num_gs_gprs = 0;
		1549	num_es_gprs = 0;
		1550	num_ps_threads = 188;
		1551	num_vs_threads = 60;
		1552	num_gs_threads = 0;
		1553	num_es_threads = 0;
		1554	num_ps_stack_entries = 256;
		1555	num_vs_stack_entries = 256;
		1556	num_gs_stack_entries = 0;
		1557	num_es_stack_entries = 0;
		1558	break;
		1559	case CHIP_RV730:
		1560	case CHIP_RV740:
		1561	num_ps_gprs = 84;
		1562	num_vs_gprs = 36;
		1563	num_temp_gprs = 4;
		1564	num_gs_gprs = 0;
		1565	num_es_gprs = 0;
		1566	num_ps_threads = 188;
		1567	num_vs_threads = 60;
		1568	num_gs_threads = 0;
		1569	num_es_threads = 0;
		1570	num_ps_stack_entries = 128;
		1571	num_vs_stack_entries = 128;
		1572	num_gs_stack_entries = 0;
		1573	num_es_stack_entries = 0;
		1574	break;
		1575	case CHIP_RV710:
		1576	num_ps_gprs = 192;
		1577	num_vs_gprs = 56;
		1578	num_temp_gprs = 4;
		1579	num_gs_gprs = 0;
		1580	num_es_gprs = 0;
		1581	num_ps_threads = 144;
		1582	num_vs_threads = 48;
		1583	num_gs_threads = 0;
		1584	num_es_threads = 0;
		1585	num_ps_stack_entries = 128;
		1586	num_vs_stack_entries = 128;
		1587	num_gs_stack_entries = 0;
		1588	num_es_stack_entries = 0;
		1589	break;
		1590	}
		1591
		1592
		1593	(rdev->family == CHIP_RV620) \|\|
		1594	(rdev->family == CHIP_RS780) \|\|
		1595	(rdev->family == CHIP_RS880) \|\|
		1596	(rdev->family == CHIP_RV710))
		1597	sq_config = 0;
		1598	else
		1599	sq_config = VC_ENABLE;
		1600
		1601
		1602	ALU_INST_PREFER_VECTOR \|
		1603	PS_PRIO(0) \|
		1604	VS_PRIO(1) \|
		1605	GS_PRIO(2) \|
		1606	ES_PRIO(3));
		1607
		1608
		1609	NUM_VS_GPRS(num_vs_gprs) \|
		1610	NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
		1611	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) \|
		1612	NUM_ES_GPRS(num_es_gprs));
		1613	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) \|
		1614	NUM_VS_THREADS(num_vs_threads) \|
		1615	NUM_GS_THREADS(num_gs_threads) \|
		1616	NUM_ES_THREADS(num_es_threads));
		1617	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) \|
		1618	NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
		1619	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) \|
		1620	NUM_ES_STACK_ENTRIES(num_es_stack_entries));
		1621
		1622
		1623	dwords = (state_len + 0xf) & ~0xf;
		1624	gpu_addr = state_gpu_addr;
		1625
		1626
		1627	radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
		1628	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
		1629	radeon_ring_write(rdev, dwords);
		1630
		1631
		1632	radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
		1633	/* SQ config */
		1634	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
		1635	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
		1636	radeon_ring_write(rdev, sq_config);
		1637	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
		1638	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
		1639	radeon_ring_write(rdev, sq_thread_resource_mgmt);
		1640	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
		1641	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
		1642	}
		1643
		1644
		1645	static void
		1646	set_scissors(struct radeon_device *rdev, int x1, int y1,
		1647	int x2, int y2)
		1648	{
		1649	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
		1650	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1651	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16));
		1652	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
		1653
		1654
		1655	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1656	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));
		1657	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
		1658
		1659
		1660	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		1661	radeon_ring_write(rdev, (x1 << 0) \| (y1 << 16) \| (1 << 31));
		1662	radeon_ring_write(rdev, (x2 << 0) \| (y2 << 16));
		1663	}
		1664
		1665
		1666	draw_auto(struct radeon_device *rdev)
		1667	{
		1668	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		1669	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
		1670	radeon_ring_write(rdev, DI_PT_RECTLIST);
		1671
		1672
		1673	radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
		1674
		1675
		1676	radeon_ring_write(rdev, 1);
		1677
		1678
		1679	radeon_ring_write(rdev, 3);
		1680	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
		1681
		1682
		1683
		1684
		1685	#define SRC0_SEL(x) (x)
		1686	#define SRC1_SEL(x) (x)
		1687	#define SRC2_SEL(x) (x)
		1688	/* src[0-2]_sel */
		1689	/* 0-127 GPR */
		1690	/* 128-159 kcache constants bank 0 */
		1691	/* 160-191 kcache constants bank 1 */
		1692	/* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */
		1693
		1694
		1695	#define SRC1_REL(x) (x)
		1696	#define SRC2_REL(x) (x)
		1697	/* elem */
		1698	#define SRC0_ELEM(x) (x)
		1699	#define SRC1_ELEM(x) (x)
		1700	#define SRC2_ELEM(x) (x)
		1701	#define ELEM_X 0
		1702	#define ELEM_Y 1
		1703	#define ELEM_Z 2
		1704	#define ELEM_W 3
		1705	/* neg */
		1706	#define SRC0_NEG(x) (x)
		1707	#define SRC1_NEG(x) (x)
		1708	#define SRC2_NEG(x) (x)
		1709	/* im */
		1710	#define INDEX_MODE(x) (x) /* SQ_INDEX_* */
		1711	/* ps */
		1712	#define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */
		1713	/* last */
		1714	#define LAST(x) (x)
		1715	/* abs */
		1716	#define SRC0_ABS(x) (x)
		1717	#define SRC1_ABS(x) (x)
		1718	/* uem */
		1719	#define UPDATE_EXECUTE_MASK(x) (x)
		1720	/* up */
		1721	#define UPDATE_PRED(x) (x)
		1722	/* wm */
		1723	#define WRITE_MASK(x) (x)
		1724	/* fm */
		1725	#define FOG_MERGE(x) (x)
		1726	/* omod */
		1727	#define OMOD(x) (x) /* SQ_ALU_OMOD_* */
		1728	/* alu inst */
		1729	#define ALU_INST(x) (x) /* SQ_ALU_INST_* */
		1730	/bs /
		1731	#define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */
		1732	#define DST_GPR(x) (x)
		1733	#define DST_REL(x) (x)
		1734	#define DST_ELEM(x) (x)
		1735	#define CLAMP(x) (x)
		1736
		1737
		1738	(((src0_sel) << 0) \| ((s0r) << 9) \| ((s0e) << 10) \| ((s0n) << 12) \| \
		1739	((src1_sel) << 13) \| ((s1r) << 22) \| ((s1e) << 23) \| ((s1n) << 25) \| \
		1740	((im) << 26) \| ((ps) << 29) \| ((last) << 31))
		1741
		1742
		1743	#define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
		1744	(((s0a) << 0) \| ((s1a) << 1) \| ((uem) << 2) \| ((up) << 3) \| ((wm) << 4) \| \
		1745	((fm) << 5) \| ((omod) << 6) \| ((alu_inst) << 8) \| ((bs) << 18) \| ((dst_gpr) << 21) \| \
		1746	((dr) << 28) \| ((de) << 29) \| ((clamp) << 31))
		1747
		1748
		1749	(((s0a) << 0) \| ((s1a) << 1) \| ((uem) << 2) \| ((up) << 3) \| ((wm) << 4) \| \
		1750	((omod) << 5) \| ((alu_inst) << 7) \| ((bs) << 18) \| ((dst_gpr) << 21) \| \
		1751	((dr) << 28) \| ((de) << 29) \| ((clamp) << 31))
		1752
		1753
		1754	/* Fog is NOT USED on R7xx, even if specified. */
		1755	#define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
		1756	((chipid) < CHIP_RV770 ? \
		1757	R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
		1758	R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))
		1759
		1760
		1761	(((src2_sel) << 0) \| ((s2r) << 9) \| ((s2e) << 10) \| ((s2n) << 12) \| \
		1762	((alu_inst) << 13) \| ((bs) << 18) \| ((dst_gpr) << 21) \| ((dr) << 28) \| \
		1763	((de) << 29) \| ((clamp) << 31))
		1764
		1765
		1766	/* addr */
		1767	#define ADDR(x) (x)
		1768	/* pc */
		1769	#define POP_COUNT(x) (x)
		1770	/* const */
		1771	#define CF_CONST(x) (x)
		1772	/* cond */
		1773	#define COND(x) (x) /* SQ_COND_* */
		1774	/* count */
		1775	#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
		1776	/r7xx /
		1777	#define COUNT_3(x) (x)
		1778	/* call count */
		1779	#define CALL_COUNT(x) (x)
		1780	/* eop */
		1781	#define END_OF_PROGRAM(x) (x)
		1782	/* vpm */
		1783	#define VALID_PIXEL_MODE(x) (x)
		1784	/* cf inst */
		1785	#define CF_INST(x) (x) /* SQ_CF_INST_* */
		1786
		1787
		1788	#define WHOLE_QUAD_MODE(x) (x)
		1789	/* barrier */
		1790	#define BARRIER(x) (x)
		1791	/kb0 /
		1792	#define KCACHE_BANK0(x) (x)
		1793	/kb1 /
		1794	#define KCACHE_BANK1(x) (x)
		1795	/* km0/1 */
		1796	#define KCACHE_MODE0(x) (x)
		1797	#define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */
		1798	/* */
		1799	#define KCACHE_ADDR0(x) (x)
		1800	#define KCACHE_ADDR1(x) (x)
		1801	/* uw */
		1802	#define USES_WATERFALL(x) (x)
		1803
		1804
		1805	/* export pixel */
		1806	#define CF_PIXEL_MRT0 0
		1807	#define CF_PIXEL_MRT1 1
		1808	#define CF_PIXEL_MRT2 2
		1809	#define CF_PIXEL_MRT3 3
		1810	#define CF_PIXEL_MRT4 4
		1811	#define CF_PIXEL_MRT5 5
		1812	#define CF_PIXEL_MRT6 6
		1813	#define CF_PIXEL_MRT7 7
		1814	/* _FOG: r6xx only /
		1815	#define CF_PIXEL_MRT0_FOG 16
		1816	#define CF_PIXEL_MRT1_FOG 17
		1817	#define CF_PIXEL_MRT2_FOG 18
		1818	#define CF_PIXEL_MRT3_FOG 19
		1819	#define CF_PIXEL_MRT4_FOG 20
		1820	#define CF_PIXEL_MRT5_FOG 21
		1821	#define CF_PIXEL_MRT6_FOG 22
		1822	#define CF_PIXEL_MRT7_FOG 23
		1823	#define CF_PIXEL_Z 61
		1824	/* export pos */
		1825	#define CF_POS0 60
		1826	#define CF_POS1 61
		1827	#define CF_POS2 62
		1828	#define CF_POS3 63
		1829	/* export param */
		1830	/* 0...31 */
		1831	#define TYPE(x) (x) /* SQ_EXPORT_* */
		1832	#if 0
		1833	/* type export */
		1834	#define SQ_EXPORT_PIXEL 0
		1835	#define SQ_EXPORT_POS 1
		1836	#define SQ_EXPORT_PARAM 2
		1837	/* reserved 3 */
		1838	/* type mem */
		1839	#define SQ_EXPORT_WRITE 0
		1840	#define SQ_EXPORT_WRITE_IND 1
		1841	#define SQ_EXPORT_WRITE_ACK 2
		1842	#define SQ_EXPORT_WRITE_IND_ACK 3
		1843	#endif
		1844
		1845
		1846	#define RW_REL(x) (x)
		1847	#define ABSOLUTE 0
		1848	#define RELATIVE 1
		1849	#define INDEX_GPR(x) (x)
		1850	#define ELEM_SIZE(x) (x ? (x - 1) : 0)
		1851	#define COMP_MASK(x) (x)
		1852	#define R6xx_ELEM_LOOP(x) (x)
		1853	#define BURST_COUNT(x) (x ? (x - 1) : 0)
		1854
		1855
		1856	#define SRC_SEL_X(x) (x) /* SQ_SEL_* each */
		1857	#define SRC_SEL_Y(x) (x)
		1858	#define SRC_SEL_Z(x) (x)
		1859	#define SRC_SEL_W(x) (x)
		1860
		1861
		1862	/* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */
		1863	/* We allow one more bit for count in the argument of the macro on R7xx instead. */
		1864	/* R6xx: [0,7] R7xx: [1,16] */
		1865	#define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \
		1866	(((pc) << 0) \| ((cf_const) << 3) \| ((cond) << 8) \| (((count) & 7) << 10) \| (((count) >> 3) << 19) \| \
		1867	((call_count) << 13) \| ((eop) << 21) \| ((vpm) << 22) \| ((cf_inst) << 23) \| ((wqm) << 30) \| ((b) << 31))
		1868
		1869
		1870	#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \
		1871	(((km1) << 0) \| ((kcache_addr0) << 2) \| ((kcache_addr1) << 10) \| \
		1872	((count) << 18) \| ((uw) << 25) \| ((cf_inst) << 26) \| ((wqm) << 30) \| ((b) << 31))
		1873
		1874
		1875	(((array_base) << 0) \| ((type) << 13) \| ((rw_gpr) << 15) \| ((rr) << 22) \| ((index_gpr) << 23) \| \
		1876	((es) << 30))
		1877	/* R7xx apparently doesn't have the ELEM_LOOP entry any more */
		1878	/* We still expose it, but ELEM_LOOP is explicitely R6xx now. */
		1879	/* TODO: is this just forgotten in the docs, or really not available any more? */
		1880	#define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \
		1881	(((array_size) << 0) \| ((comp_mask) << 12) \| ((el) << 16) \| ((bc) << 17) \| \
		1882	((eop) << 21) \| ((vpm) << 22) \| ((cf_inst) << 23) \| ((wqm) << 30) \| ((b) << 31))
		1883	#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \
		1884	(((sel_x) << 0) \| ((sel_y) << 3) \| ((sel_z) << 6) \| ((sel_w) << 9) \| ((el) << 16) \| \
		1885	((bc) << 17) \| ((eop) << 21) \| ((vpm) << 22) \| ((cf_inst) << 23) \| \
		1886	((wqm) << 30) \| ((b) << 31))
		1887
		1888
		1889	/* vxt insts */
		1890	#define VTX_INST(x) (x) /* SQ_VTX_INST_* */
		1891
		1892
		1893	#define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */
		1894
		1895
		1896	#define BUFFER_ID(x) (x)
		1897	#define SRC_GPR(x) (x)
		1898	#define SRC_REL(x) (x)
		1899	#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
		1900
		1901
		1902	#define DST_SEL_X(x) (x)
		1903	#define DST_SEL_Y(x) (x)
		1904	#define DST_SEL_Z(x) (x)
		1905	#define DST_SEL_W(x) (x)
		1906	#define USE_CONST_FIELDS(x) (x)
		1907	#define DATA_FORMAT(x) (x)
		1908	/* num format */
		1909	#define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */
		1910	/* format comp */
		1911	#define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */
		1912	/* sma */
		1913	#define SRF_MODE_ALL(x) (x)
		1914	#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
		1915	#define SRF_MODE_NO_ZERO 1
		1916	#define OFFSET(x) (x)
		1917	/* endian swap */
		1918	#define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */
		1919	#define CONST_BUF_NO_STRIDE(x) (x)
		1920	/* mf */
		1921	#define MEGA_FETCH(x) (x)
		1922
		1923
		1924	(((vtx_inst) << 0) \| ((ft) << 5) \| ((fwq) << 7) \| ((buffer_id) << 8) \| \
		1925	((src_gpr) << 16) \| ((sr) << 23) \| ((ssx) << 24) \| ((mfc) << 26))
		1926	#define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
		1927	(((semantic_id) << 0) \| ((dsx) << 9) \| ((dsy) << 12) \| ((dsz) << 15) \| ((dsw) << 18) \| \
		1928	((ucf) << 21) \| ((data_format) << 22) \| ((nfa) << 28) \| ((fca) << 30) \| ((sma) << 31))
		1929	#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
		1930	(((dst_gpr) << 0) \| ((dr) << 7) \| ((dsx) << 9) \| ((dsy) << 12) \| ((dsz) << 15) \| ((dsw) << 18) \| \
		1931	((ucf) << 21) \| ((data_format) << 22) \| ((nfa) << 28) \| ((fca) << 30) \| ((sma) << 31))
		1932	#define VTX_DWORD2(offset, es, cbns, mf) \
		1933	(((offset) << 0) \| ((es) << 16) \| ((cbns) << 18) \| ((mf) << 19))
		1934	#define VTX_DWORD_PAD 0x00000000
		1935
		1936
		1937
		1938	{
		1939	int i=0;
		1940
		1941
		1942	shader[i++] = CF_DWORD0(ADDR(4));
		1943	shader[i++] = CF_DWORD1(POP_COUNT(0),
		1944	CF_CONST(0),
		1945	COND(SQ_CF_COND_ACTIVE),
		1946	I_COUNT(1),
		1947	CALL_COUNT(0),
		1948	END_OF_PROGRAM(0),
		1949	VALID_PIXEL_MODE(0),
		1950	CF_INST(SQ_CF_INST_VTX),
		1951	WHOLE_QUAD_MODE(0),
		1952	BARRIER(1));
		1953	/* 1 */
		1954	shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
		1955	TYPE(SQ_EXPORT_POS),
		1956	RW_GPR(1),
		1957	RW_REL(ABSOLUTE),
		1958	INDEX_GPR(0),
		1959	ELEM_SIZE(0));
		1960	shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
		1961	SRC_SEL_Y(SQ_SEL_Y),
		1962	SRC_SEL_Z(SQ_SEL_Z),
		1963	SRC_SEL_W(SQ_SEL_W),
		1964	R6xx_ELEM_LOOP(0),
		1965	BURST_COUNT(1),
		1966	END_OF_PROGRAM(0),
		1967	VALID_PIXEL_MODE(0),
		1968	CF_INST(SQ_CF_INST_EXPORT_DONE),
		1969	WHOLE_QUAD_MODE(0),
		1970	BARRIER(1));
		1971	/* 2 - always export a param whether it's used or not */
		1972	shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
		1973	TYPE(SQ_EXPORT_PARAM),
		1974	RW_GPR(0),
		1975	RW_REL(ABSOLUTE),
		1976	INDEX_GPR(0),
		1977	ELEM_SIZE(0));
		1978	shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
		1979	SRC_SEL_Y(SQ_SEL_Y),
		1980	SRC_SEL_Z(SQ_SEL_Z),
		1981	SRC_SEL_W(SQ_SEL_W),
		1982	R6xx_ELEM_LOOP(0),
		1983	BURST_COUNT(0),
		1984	END_OF_PROGRAM(1),
		1985	VALID_PIXEL_MODE(0),
		1986	CF_INST(SQ_CF_INST_EXPORT_DONE),
		1987	WHOLE_QUAD_MODE(0),
		1988	BARRIER(0));
		1989	/* 3 - padding */
		1990	shader[i++] = 0x00000000;
		1991	shader[i++] = 0x00000000;
		1992	/* 4/5 */
		1993	shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
		1994	FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
		1995	FETCH_WHOLE_QUAD(0),
		1996	BUFFER_ID(0),
		1997	SRC_GPR(0),
		1998	SRC_REL(ABSOLUTE),
		1999	SRC_SEL_X(SQ_SEL_X),
		2000	MEGA_FETCH_COUNT(8));
		2001	shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
		2002	DST_REL(0),
		2003	DST_SEL_X(SQ_SEL_X),
		2004	DST_SEL_Y(SQ_SEL_Y),
		2005	DST_SEL_Z(SQ_SEL_0),
		2006	DST_SEL_W(SQ_SEL_1),
		2007	USE_CONST_FIELDS(0),
		2008	DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
		2009	NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
		2010	FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
		2011	SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
		2012	shader[i++] = VTX_DWORD2(OFFSET(0),
		2013	ENDIAN_SWAP(ENDIAN_NONE),
		2014	CONST_BUF_NO_STRIDE(0),
		2015	MEGA_FETCH(1));
		2016	shader[i++] = VTX_DWORD_PAD;
		2017
		2018
		2019	}
		2020
		2021
		2022	{
		2023	int i=0;
		2024
		2025
		2026	shader[i++] = CF_ALU_DWORD0(ADDR(2),
		2027	KCACHE_BANK0(0),
		2028	KCACHE_BANK1(0),
		2029	KCACHE_MODE0(SQ_CF_KCACHE_NOP));
		2030	shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
		2031	KCACHE_ADDR0(0),
		2032	KCACHE_ADDR1(0),
		2033	I_COUNT(4),
		2034	USES_WATERFALL(0),
		2035	CF_INST(SQ_CF_INST_ALU),
		2036	WHOLE_QUAD_MODE(0),
		2037	BARRIER(1));
		2038	/* 1 */
		2039	shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
		2040	TYPE(SQ_EXPORT_PIXEL),
		2041	RW_GPR(0),
		2042	RW_REL(ABSOLUTE),
		2043	INDEX_GPR(0),
		2044	ELEM_SIZE(1));
		2045	shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
		2046	SRC_SEL_Y(SQ_SEL_Y),
		2047	SRC_SEL_Z(SQ_SEL_Z),
		2048	SRC_SEL_W(SQ_SEL_W),
		2049	R6xx_ELEM_LOOP(0),
		2050	BURST_COUNT(1),
		2051	END_OF_PROGRAM(1),
		2052	VALID_PIXEL_MODE(0),
		2053	CF_INST(SQ_CF_INST_EXPORT_DONE),
		2054	WHOLE_QUAD_MODE(0),
		2055	BARRIER(1));
		2056
		2057
		2058	shader[i++] = ALU_DWORD0(SRC0_SEL(256),
		2059	SRC0_REL(ABSOLUTE),
		2060	SRC0_ELEM(ELEM_X),
		2061	SRC0_NEG(0),
		2062	SRC1_SEL(0),
		2063	SRC1_REL(ABSOLUTE),
		2064	SRC1_ELEM(ELEM_X),
		2065	SRC1_NEG(0),
		2066	INDEX_MODE(SQ_INDEX_AR_X),
		2067	PRED_SEL(SQ_PRED_SEL_OFF),
		2068	LAST(0));
		2069	shader[i++] = ALU_DWORD1_OP2(rdev->family,
		2070	SRC0_ABS(0),
		2071	SRC1_ABS(0),
		2072	UPDATE_EXECUTE_MASK(0),
		2073	UPDATE_PRED(0),
		2074	WRITE_MASK(1),
		2075	FOG_MERGE(0),
		2076	OMOD(SQ_ALU_OMOD_OFF),
		2077	ALU_INST(SQ_OP2_INST_MOV),
		2078	BANK_SWIZZLE(SQ_ALU_VEC_012),
		2079	DST_GPR(0),
		2080	DST_REL(ABSOLUTE),
		2081	DST_ELEM(ELEM_X),
		2082	CLAMP(1));
		2083	/* 3 */
		2084	shader[i++] = ALU_DWORD0(SRC0_SEL(256),
		2085	SRC0_REL(ABSOLUTE),
		2086	SRC0_ELEM(ELEM_Y),
		2087	SRC0_NEG(0),
		2088	SRC1_SEL(0),
		2089	SRC1_REL(ABSOLUTE),
		2090	SRC1_ELEM(ELEM_Y),
		2091	SRC1_NEG(0),
		2092	INDEX_MODE(SQ_INDEX_AR_X),
		2093	PRED_SEL(SQ_PRED_SEL_OFF),
		2094	LAST(0));
		2095	shader[i++] = ALU_DWORD1_OP2(rdev->family,
		2096	SRC0_ABS(0),
		2097	SRC1_ABS(0),
		2098	UPDATE_EXECUTE_MASK(0),
		2099	UPDATE_PRED(0),
		2100	WRITE_MASK(1),
		2101	FOG_MERGE(0),
		2102	OMOD(SQ_ALU_OMOD_OFF),
		2103	ALU_INST(SQ_OP2_INST_MOV),
		2104	BANK_SWIZZLE(SQ_ALU_VEC_012),
		2105	DST_GPR(0),
		2106	DST_REL(ABSOLUTE),
		2107	DST_ELEM(ELEM_Y),
		2108	CLAMP(1));
		2109	/* 4 */
		2110	shader[i++] = ALU_DWORD0(SRC0_SEL(256),
		2111	SRC0_REL(ABSOLUTE),
		2112	SRC0_ELEM(ELEM_Z),
		2113	SRC0_NEG(0),
		2114	SRC1_SEL(0),
		2115	SRC1_REL(ABSOLUTE),
		2116	SRC1_ELEM(ELEM_Z),
		2117	SRC1_NEG(0),
		2118	INDEX_MODE(SQ_INDEX_AR_X),
		2119	PRED_SEL(SQ_PRED_SEL_OFF),
		2120	LAST(0));
		2121	shader[i++] = ALU_DWORD1_OP2(rdev->family,
		2122	SRC0_ABS(0),
		2123	SRC1_ABS(0),
		2124	UPDATE_EXECUTE_MASK(0),
		2125	UPDATE_PRED(0),
		2126	WRITE_MASK(1),
		2127	FOG_MERGE(0),
		2128	OMOD(SQ_ALU_OMOD_OFF),
		2129	ALU_INST(SQ_OP2_INST_MOV),
		2130	BANK_SWIZZLE(SQ_ALU_VEC_012),
		2131	DST_GPR(0),
		2132	DST_REL(ABSOLUTE),
		2133	DST_ELEM(ELEM_Z),
		2134	CLAMP(1));
		2135	/* 5 */
		2136	shader[i++] = ALU_DWORD0(SRC0_SEL(256),
		2137	SRC0_REL(ABSOLUTE),
		2138	SRC0_ELEM(ELEM_W),
		2139	SRC0_NEG(0),
		2140	SRC1_SEL(0),
		2141	SRC1_REL(ABSOLUTE),
		2142	SRC1_ELEM(ELEM_W),
		2143	SRC1_NEG(0),
		2144	INDEX_MODE(SQ_INDEX_AR_X),
		2145	PRED_SEL(SQ_PRED_SEL_OFF),
		2146	LAST(1));
		2147	shader[i++] = ALU_DWORD1_OP2(rdev->family,
		2148	SRC0_ABS(0),
		2149	SRC1_ABS(0),
		2150	UPDATE_EXECUTE_MASK(0),
		2151	UPDATE_PRED(0),
		2152	WRITE_MASK(1),
		2153	FOG_MERGE(0),
		2154	OMOD(SQ_ALU_OMOD_OFF),
		2155	ALU_INST(SQ_OP2_INST_MOV),
		2156	BANK_SWIZZLE(SQ_ALU_VEC_012),
		2157	DST_GPR(0),
		2158	DST_REL(ABSOLUTE),
		2159	DST_ELEM(ELEM_W),
		2160	CLAMP(1));
		2161
		2162
		2163	}
		2164
		2165
		2166	memcpy_toio(volatile void __iomem dst, const void src, int count)
		2167	{
		2168	__memcpy((void __force *)dst, src, count);
		2169	}
		2170
		2171
		2172	do { \
		2173	union { float f; uint32_t d; } a; \
		2174	a.f = (val); \
		2175	radeon_ring_write(rdev, a.d); \
		2176	} while (0)
		2177
		2178
		2179	{
		2180	uint32_t ps_shader[16];
		2181	uint32_t vs_shader[16];
		2182
		2183
		2184	int num_packet2s = 0;
		2185
		2186
		2187	uint32_t offset;
		2188
		2189
		2190	int dwords;
		2191	u32 obj_size;
		2192
		2193
		2194	u64 state_gpu_addr = 0;
		2195
		2196
		2197	u32 ps_offset;
		2198	u32 vb_offset;
		2199
		2200
		2201	int ps_size;
		2202
		2203
		2204	void *ptr;
		2205
		2206
		2207
		2208
		2209
		2210
		2211
		2212
		2213	offset = rdev->mc.vram_location;
		2214
		2215
		2216	vs_size = R600_solid_vs(rdev, vs_shader);
		2217
		2218
		2219	state_len = r7xx_default_size;
		2220	else
		2221	state_len = r6xx_default_size;
		2222
		2223
		2224
		2225
		2226	packet2s[num_packet2s++] = PACKET2(0);
		2227	dwords++;
		2228	}
		2229
		2230
		2231	obj_size = ALIGN(obj_size, 256);
		2232
		2233
		2234	obj_size += vs_size * 4;
		2235	obj_size = ALIGN(obj_size, 256);
		2236
		2237
		2238	obj_size += ps_size * 4;
		2239	obj_size = ALIGN(obj_size, 256);
		2240
		2241
		2242	obj_size += 32*4;
		2243	obj_size = ALIGN(obj_size, 256);
		2244
		2245
		2246	&state_obj);
		2247	if (r) {
		2248	DRM_ERROR("r600 failed to allocate state buffer\n");
		2249	return r;
		2250	}
		2251
		2252
		2253	obj_size, vs_offset, ps_offset);
		2254
		2255
		2256	&state_gpu_addr);
		2257	if (r) {
		2258	DRM_ERROR("failed to pin state object %d\n", r);
		2259	return r;
		2260	};
		2261
		2262
		2263	if (r) {
		2264	DRM_ERROR("failed to map state object %d\n", r);
		2265	return r;
		2266	};
		2267
		2268
		2269	memcpy_toio(ptr + state_offset,
		2270	r7xx_default_state, state_len * 4);
		2271	else
		2272	memcpy_toio(ptr + state_offset,
		2273	r6xx_default_state, state_len * 4);
		2274
		2275
		2276	memcpy_toio(ptr + state_offset + (state_len * 4),
		2277	packet2s, num_packet2s * 4);
		2278
		2279
		2280	memcpy(ptr + ps_offset, ps_shader, ps_size * 4);
		2281
		2282
		2283
		2284
		2285
		2286	vb[1] = (float)64;
		2287
		2288
		2289	vb[3] = (float)(64+128);
		2290
		2291
		2292	vb[5] = (float)(64+128);
		2293
		2294
		2295	int vb_size = vb_index * 8;
		2296	int vtx_num_entries = vb_size / 4;
		2297
		2298
		2299
		2300
		2301	if (r) {
		2302	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		2303	return r;
		2304	}
		2305
		2306
		2307
		2308
		2309
		2310	u32 sq_pgm_resources;
		2311
		2312
		2313
		2314
		2315
		2316
		2317	gpu_addr = state_gpu_addr + vs_offset;
		2318
		2319
		2320	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2321	radeon_ring_write(rdev, gpu_addr >> 8);
		2322
		2323
		2324	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2325	radeon_ring_write(rdev, sq_pgm_resources);
		2326
		2327
		2328	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2329	radeon_ring_write(rdev, 0);
		2330
		2331
		2332
		2333
		2334	gpu_addr = state_gpu_addr + ps_offset;
		2335
		2336
		2337	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2338	radeon_ring_write(rdev, gpu_addr >> 8);
		2339
		2340
		2341	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2342	radeon_ring_write(rdev, sq_pgm_resources \| (1 << 28));
		2343
		2344
		2345	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2346	radeon_ring_write(rdev, 2);
		2347
		2348
		2349	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
		2350	radeon_ring_write(rdev, 0);
		2351
		2352
		2353	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
		2354
		2355
		2356
		2357	rdev->mc.vram_location);
		2358
		2359
		2360
		2361
		2362
		2363	radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2);
		2364	EFLOAT(0.0f); /* r */
		2365	EFLOAT(1.0f); /* g */
		2366	EFLOAT(0.0f); /* b */
		2367	EFLOAT(1.0f); /* a */
		2368
		2369
		2370
		2371
		2372
		2373
		2374
		2375
		2376	radeon_ring_write(rdev, 0x460);
		2377	radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */
		2378	radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */
		2379	radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */
		2380	radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */
		2381	radeon_ring_write(rdev, 0);
		2382	radeon_ring_write(rdev, 0);
		2383	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
		2384
		2385
		2386	(rdev->family == CHIP_RV620) \|\|
		2387	(rdev->family == CHIP_RS780) \|\|
		2388	(rdev->family == CHIP_RS880) \|\|
		2389	(rdev->family == CHIP_RV710))
		2390	cp_set_surface_sync(rdev,
		2391	PACKET3_TC_ACTION_ENA, 24, gpu_addr);
		2392	else
		2393	cp_set_surface_sync(rdev,
		2394	PACKET3_VC_ACTION_ENA, 24, gpu_addr);
		2395
		2396
		2397
		2398
		2399	10244512, offset);
		2400
		2401
		2402	radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
		2403	/* wait for 3D idle clean */
		2404	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		2405	radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
		2406	radeon_ring_write(rdev, WAIT_3D_IDLE_bit \| WAIT_3D_IDLECLEAN_bit);
		2407
		2408
		2409
		2410
		2411
		2412
		2413	return r;
		2414	}
		2415

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(root)/drivers/video/drm/radeon/rdisplay.c – Rev 1428