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Rev | Author | Line No. | Line |
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1221 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include |
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5 | #include "radeon_drm.h" |
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6 | #include "radeon.h" |
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7 | #include "radeon_object.h" |
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8 | |||
9 | |||
10 | #define CURSOR_HEIGHT 64 |
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11 | |||
12 | |||
13 | typedef struct tag_display display_t; |
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14 | |||
15 | |||
16 | { |
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17 | uint32_t magic; |
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18 | void *destroy; |
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19 | kobj_t *fd; |
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20 | kobj_t *bk; |
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21 | uint32_t pid; |
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22 | }; |
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23 | |||
24 | |||
25 | { |
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26 | kobj_t header; |
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27 | |||
28 | |||
29 | uint32_t hot_x; |
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30 | uint32_t hot_y; |
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31 | |||
32 | |||
33 | struct radeon_object *robj; |
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34 | }cursor_t; |
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35 | |||
36 | |||
1230 | serge | 37 | cursor_t* __stdcall select_cursor(cursor_t *cursor); |
38 | void __stdcall move_cursor(cursor_t *cursor, int x, int y); |
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39 | void __stdcall restore_cursor(int x, int y); |
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40 | |||
41 | |||
1221 | serge | 42 | { |
43 | int x; |
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44 | int y; |
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45 | int width; |
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46 | int height; |
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47 | int bpp; |
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48 | int vrefresh; |
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49 | int pitch; |
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50 | int lfb; |
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51 | |||
52 | |||
53 | struct drm_crtc *crtc; |
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54 | |||
55 | |||
56 | |||
57 | |||
58 | int (*init_cursor)(cursor_t*); |
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59 | cursor_t* (__stdcall *select_cursor)(cursor_t*); |
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1230 | serge | 60 | void (*show_cursor)(int show); |
1221 | serge | 61 | void (__stdcall *move_cursor)(cursor_t *cursor, int x, int y); |
1230 | serge | 62 | void (__stdcall *restore_cursor)(int x, int y); |
63 | |||
64 | |||
1221 | serge | 65 | |
66 | |||
67 | |||
1230 | serge | 68 | |
1221 | serge | 69 | |
1230 | serge | 70 | |
71 | { |
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72 | ENTER(); |
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73 | rdisplay->crtc = crtc; |
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74 | LEAVE(); |
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75 | } |
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76 | |||
77 | |||
1221 | serge | 78 | { |
79 | struct radeon_device *rdev; |
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80 | |||
81 | |||
82 | uint32_t *src; |
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83 | |||
84 | |||
85 | int r; |
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86 | |||
87 | |||
88 | |||
89 | |||
90 | false, |
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91 | RADEON_GEM_DOMAIN_VRAM, |
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92 | false, &cursor->robj); |
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93 | |||
94 | |||
95 | return r; |
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96 | |||
97 | |||
98 | |||
99 | |||
100 | if (r) { |
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101 | DRM_ERROR("radeon: failed to map cursor (%d).\n", r); |
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102 | return r; |
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103 | }; |
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104 | |||
105 | |||
106 | |||
107 | |||
108 | { |
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109 | for(j = 0; j < 32; j++) |
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110 | *bits++ = *src++; |
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111 | for(j = 32; j < CURSOR_WIDTH; j++) |
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1230 | serge | 112 | *bits++ = 0; |
1221 | serge | 113 | } |
114 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
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115 | *bits++ = 0; |
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116 | |||
117 | |||
118 | |||
119 | |||
120 | }; |
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121 | |||
122 | |||
1230 | serge | 123 | { |
1221 | serge | 124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1230 | serge | 125 | struct radeon_device *rdev = crtc->dev->dev_private; |
126 | |||
127 | |||
128 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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129 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
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130 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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131 | } else { |
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132 | switch (radeon_crtc->crtc_id) { |
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133 | case 0: |
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134 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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135 | break; |
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136 | case 1: |
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137 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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138 | break; |
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139 | default: |
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140 | return; |
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141 | } |
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142 | |||
143 | |||
144 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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145 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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146 | } |
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147 | } |
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148 | |||
149 | |||
150 | { |
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151 | cursor_t *cursor; |
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1221 | serge | 152 | |
153 | |||
1230 | serge | 154 | |
1221 | serge | 155 | |
1230 | serge | 156 | |
157 | |||
1221 | serge | 158 | |
159 | |||
160 | { |
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161 | init_cursor(cursor); |
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162 | }; |
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163 | |||
1230 | serge | 164 | |
165 | |||
166 | |||
1221 | serge | 167 | }; |
168 | |||
169 | |||
1230 | serge | 170 | { |
171 | cursor_t *cursor; |
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172 | |||
173 | |||
174 | |||
175 | |||
176 | |||
177 | |||
178 | |||
179 | |||
180 | rdisplay->select_cursor = select_cursor; |
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181 | rdisplay->show_cursor = NULL; |
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182 | rdisplay->move_cursor = move_cursor; |
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183 | rdisplay->restore_cursor = restore_cursor; |
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184 | |||
185 | |||
186 | |||
187 | |||
188 | }; |
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189 | |||
190 | |||
1221 | serge | 191 | { |
192 | struct radeon_device *rdev = crtc->dev->dev_private; |
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193 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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194 | uint32_t cur_lock; |
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195 | |||
196 | |||
197 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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198 | if (lock) |
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199 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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200 | else |
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201 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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202 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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203 | } else { |
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204 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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205 | if (lock) |
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206 | cur_lock |= RADEON_CUR_LOCK; |
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207 | else |
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208 | cur_lock &= ~RADEON_CUR_LOCK; |
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209 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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210 | } |
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211 | } |
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212 | |||
213 | |||
1230 | serge | 214 | { |
1221 | serge | 215 | struct radeon_device *rdev; |
216 | struct radeon_crtc *radeon_crtc; |
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217 | cursor_t *old; |
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218 | uint32_t gpu_addr; |
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219 | |||
220 | |||
221 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
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222 | |||
223 | |||
1230 | serge | 224 | |
1221 | serge | 225 | |
1230 | serge | 226 | gpu_addr = cursor->robj->gpu_addr; |
1221 | serge | 227 | |
228 | |||
229 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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230 | else { |
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231 | radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; |
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232 | /* offset is from DISP(2)_BASE_ADDRESS */ |
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233 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
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234 | } |
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235 | |||
1230 | serge | 236 | |
1221 | serge | 237 | }; |
238 | |||
239 | |||
240 | |||
1230 | serge | 241 | { |
1221 | serge | 242 | struct radeon_device *rdev; |
1230 | serge | 243 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
244 | struct drm_crtc *crtc = rdisplay->crtc; |
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1221 | serge | 245 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
246 | |||
247 | |||
1230 | serge | 248 | int hot_y = cursor->hot_y; |
249 | |||
1221 | serge | 250 | |
251 | if (ASIC_IS_AVIVO(rdev)) |
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252 | { |
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253 | int w = 32; |
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254 | int i = 0; |
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255 | struct drm_crtc *crtc_p; |
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256 | |||
257 | |||
258 | // x += crtc->x; |
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1230 | serge | 259 | // y += crtc->y; |
260 | |||
1221 | serge | 261 | |
262 | #if 0 |
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263 | /* avivo cursor image can't end on 128 pixel boundry or |
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264 | * go past the end of the frame if both crtcs are enabled |
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265 | */ |
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266 | list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { |
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267 | if (crtc_p->enabled) |
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268 | i++; |
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269 | } |
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270 | if (i > 1) { |
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271 | int cursor_end, frame_end; |
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272 | |||
273 | |||
274 | frame_end = crtc->x + crtc->mode.crtc_hdisplay; |
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275 | if (cursor_end >= frame_end) { |
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276 | w = w - (cursor_end - frame_end); |
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277 | if (!(frame_end & 0x7f)) |
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278 | w--; |
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279 | } else { |
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280 | if (!(cursor_end & 0x7f)) |
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281 | w--; |
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282 | } |
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283 | if (w <= 0) |
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284 | w = 1; |
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285 | } |
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286 | #endif |
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287 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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288 | (x << 16) | y); |
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289 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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290 | (hot_x << 16) | hot_y); |
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1230 | serge | 291 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
1221 | serge | 292 | ((w - 1) << 16) | 31); |
293 | } else { |
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294 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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295 | y *= 2; |
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296 | |||
297 | |||
298 | (RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16))); |
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299 | WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, |
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300 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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301 | |||
302 | |||
303 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, |
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304 | (radeon_crtc->legacy_cursor_offset + (hot_y * 256))); |
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305 | } |
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306 | radeon_lock_cursor(crtc, false); |
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307 | } |
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308 | |||
309 | |||
1230 | serge | 310 | { |
311 | };><>><>><>><>><>><>=>><>><>>>>> |
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312 |