WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_uvd.c

Rev	Author	Line No.	Line
5078	serge	1	/*
		2	* Copyright 2011 Advanced Micro Devices, Inc.
		3	* All Rights Reserved.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the
		7	* "Software"), to deal in the Software without restriction, including
		8	* without limitation the rights to use, copy, modify, merge, publish,
		9	* distribute, sub license, and/or sell copies of the Software, and to
		10	* permit persons to whom the Software is furnished to do so, subject to
		11	* the following conditions:
		12	*
		13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
		17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
		18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
		19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
		20	*
		21	* The above copyright notice and this permission notice (including the
		22	* next paragraph) shall be included in all copies or substantial portions
		23	* of the Software.
		24	*
		25	*/
		26	/*
		27	* Authors:
		28	* Christian König
		29	*/
		30
		31	#include
		32	#include
		33	#include
		34	#include
		35
		36	#include "radeon.h"
		37	#include "r600d.h"
		38
		39	/* 1 second timeout */
		40	#define UVD_IDLE_TIMEOUT_MS 1000
		41
		42	/* Firmware Names */
		43	#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
		44	#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
		45	#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
		46	#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
		47	#define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
		48
5271	serge	49	MODULE_FIRMWARE(FIRMWARE_R600);
		50	MODULE_FIRMWARE(FIRMWARE_RS780);
		51	MODULE_FIRMWARE(FIRMWARE_RV770);
5078	serge	52	MODULE_FIRMWARE(FIRMWARE_RV710);
		53	MODULE_FIRMWARE(FIRMWARE_CYPRESS);
		54	MODULE_FIRMWARE(FIRMWARE_SUMO);
		55	MODULE_FIRMWARE(FIRMWARE_TAHITI);
		56	MODULE_FIRMWARE(FIRMWARE_BONAIRE);
		57
		58	static void radeon_uvd_idle_work_handler(struct work_struct *work);
		59
		60	int radeon_uvd_init(struct radeon_device *rdev)
		61	{
		62	unsigned long bo_size;
		63	const char *fw_name;
		64	int i, r;
		65
		66	// INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
		67
		68	switch (rdev->family) {
		69	case CHIP_RV710:
		70	case CHIP_RV730:
		71	case CHIP_RV740:
		72	fw_name = FIRMWARE_RV710;
		73	break;
		74
		75	case CHIP_CYPRESS:
		76	case CHIP_HEMLOCK:
		77	case CHIP_JUNIPER:
		78	case CHIP_REDWOOD:
		79	case CHIP_CEDAR:
		80	fw_name = FIRMWARE_CYPRESS;
		81	break;
		82
		83	case CHIP_SUMO:
		84	case CHIP_SUMO2:
		85	case CHIP_PALM:
		86	case CHIP_CAYMAN:
		87	case CHIP_BARTS:
		88	case CHIP_TURKS:
		89	case CHIP_CAICOS:
		90	fw_name = FIRMWARE_SUMO;
		91	break;
		92
		93	case CHIP_TAHITI:
		94	case CHIP_VERDE:
		95	case CHIP_PITCAIRN:
		96	case CHIP_ARUBA:
		97	case CHIP_OLAND:
		98	fw_name = FIRMWARE_TAHITI;
		99	break;
		100
		101	case CHIP_BONAIRE:
		102	case CHIP_KABINI:
		103	case CHIP_KAVERI:
		104	case CHIP_HAWAII:
		105	case CHIP_MULLINS:
		106	fw_name = FIRMWARE_BONAIRE;
		107	break;
		108
		109	default:
		110	return -EINVAL;
		111	}
		112
		113	r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
		114	if (r) {
		115	dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
		116	fw_name);
		117	return r;
		118	}
		119
		120	bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
5271	serge	121	RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
		122	RADEON_GPU_PAGE_SIZE;
5078	serge	123	r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
5271	serge	124	RADEON_GEM_DOMAIN_VRAM, 0, NULL,
		125	NULL, &rdev->uvd.vcpu_bo);
5078	serge	126	if (r) {
		127	dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
		128	return r;
		129	}
		130
		131	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
		132	if (r) {
		133	radeon_bo_unref(&rdev->uvd.vcpu_bo);
		134	dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
		135	return r;
		136	}
		137
		138	r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
		139	&rdev->uvd.gpu_addr);
		140	if (r) {
		141	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		142	radeon_bo_unref(&rdev->uvd.vcpu_bo);
		143	dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
		144	return r;
		145	}
		146
		147	r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
		148	if (r) {
		149	dev_err(rdev->dev, "(%d) UVD map failed\n", r);
		150	return r;
		151	}
		152
		153	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		154
		155	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		156	atomic_set(&rdev->uvd.handles[i], 0);
		157	rdev->uvd.filp[i] = NULL;
		158	rdev->uvd.img_size[i] = 0;
		159	}
		160
		161	return 0;
		162	}
		163
		164	void radeon_uvd_fini(struct radeon_device *rdev)
		165	{
		166	int r;
		167
		168	if (rdev->uvd.vcpu_bo == NULL)
		169	return;
		170
		171	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
		172	if (!r) {
		173	radeon_bo_kunmap(rdev->uvd.vcpu_bo);
		174	radeon_bo_unpin(rdev->uvd.vcpu_bo);
		175	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		176	}
		177
		178	radeon_bo_unref(&rdev->uvd.vcpu_bo);
		179
		180	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
		181
		182	release_firmware(rdev->uvd_fw);
		183	}
		184
		185	int radeon_uvd_suspend(struct radeon_device *rdev)
		186	{
		187	unsigned size;
		188	void *ptr;
		189	int i;
		190
		191	if (rdev->uvd.vcpu_bo == NULL)
		192	return 0;
		193
		194	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
		195	if (atomic_read(&rdev->uvd.handles[i]))
		196	break;
		197
		198	if (i == RADEON_MAX_UVD_HANDLES)
		199	return 0;
		200
		201	size = radeon_bo_size(rdev->uvd.vcpu_bo);
		202	size -= rdev->uvd_fw->size;
		203
		204	ptr = rdev->uvd.cpu_addr;
		205	ptr += rdev->uvd_fw->size;
		206
		207	rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
		208	memcpy(rdev->uvd.saved_bo, ptr, size);
		209
		210	return 0;
		211	}
		212
		213	int radeon_uvd_resume(struct radeon_device *rdev)
		214	{
		215	unsigned size;
		216	void *ptr;
		217
		218	if (rdev->uvd.vcpu_bo == NULL)
		219	return -EINVAL;
		220
		221	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
		222
		223	size = radeon_bo_size(rdev->uvd.vcpu_bo);
		224	size -= rdev->uvd_fw->size;
		225
		226	ptr = rdev->uvd.cpu_addr;
		227	ptr += rdev->uvd_fw->size;
		228
		229	if (rdev->uvd.saved_bo != NULL) {
		230	memcpy(ptr, rdev->uvd.saved_bo, size);
		231	kfree(rdev->uvd.saved_bo);
		232	rdev->uvd.saved_bo = NULL;
		233	} else
		234	memset(ptr, 0, size);
		235
		236	return 0;
		237	}
		238
5271	serge	239	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
		240	uint32_t allowed_domains)
5078	serge	241	{
5271	serge	242	int i;
		243
		244	for (i = 0; i < rbo->placement.num_placement; ++i) {
		245	rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
		246	rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
		247	}
		248
		249	/* If it must be in VRAM it must be in the first segment as well */
		250	if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
		251	return;
		252
		253	/* abort if we already have more than one placement */
		254	if (rbo->placement.num_placement > 1)
		255	return;
		256
		257	/* add another 256MB segment */
		258	rbo->placements[1] = rbo->placements[0];
		259	rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
		260	rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
		261	rbo->placement.num_placement++;
		262	rbo->placement.num_busy_placement++;
5078	serge	263	}
		264
		265	void radeon_uvd_free_handles(struct radeon_device rdev, struct drm_file filp)
		266	{
		267	int i, r;
		268	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		269	uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
		270	if (handle != 0 && rdev->uvd.filp[i] == filp) {
		271	struct radeon_fence *fence;
		272
		273	radeon_uvd_note_usage(rdev);
		274
		275	r = radeon_uvd_get_destroy_msg(rdev,
		276	R600_RING_TYPE_UVD_INDEX, handle, &fence);
		277	if (r) {
		278	DRM_ERROR("Error destroying UVD (%d)!\n", r);
		279	continue;
		280	}
		281
		282	radeon_fence_wait(fence, false);
		283	radeon_fence_unref(&fence);
		284
		285	rdev->uvd.filp[i] = NULL;
		286	atomic_set(&rdev->uvd.handles[i], 0);
		287	}
		288	}
		289	}
		290
		291	static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
		292	{
		293	unsigned stream_type = msg[4];
		294	unsigned width = msg[6];
		295	unsigned height = msg[7];
		296	unsigned dpb_size = msg[9];
		297	unsigned pitch = msg[28];
		298
		299	unsigned width_in_mb = width / 16;
		300	unsigned height_in_mb = ALIGN(height / 16, 2);
		301
		302	unsigned image_size, tmp, min_dpb_size;
		303
		304	image_size = width * height;
		305	image_size += image_size / 2;
		306	image_size = ALIGN(image_size, 1024);
		307
		308	switch (stream_type) {
		309	case 0: /* H264 */
		310
		311	/* reference picture buffer */
		312	min_dpb_size = image_size * 17;
		313
		314	/* macroblock context buffer */
		315	min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
		316
		317	/* IT surface buffer */
		318	min_dpb_size += width_in_mb * height_in_mb * 32;
		319	break;
		320
		321	case 1: /* VC1 */
		322
		323	/* reference picture buffer */
		324	min_dpb_size = image_size * 3;
		325
		326	/* CONTEXT_BUFFER */
		327	min_dpb_size += width_in_mb * height_in_mb * 128;
		328
		329	/* IT surface buffer */
		330	min_dpb_size += width_in_mb * 64;
		331
		332	/* DB surface buffer */
		333	min_dpb_size += width_in_mb * 128;
		334
		335	/* BP */
		336	tmp = max(width_in_mb, height_in_mb);
		337	min_dpb_size += ALIGN(tmp * 7 * 16, 64);
		338	break;
		339
		340	case 3: /* MPEG2 */
		341
		342	/* reference picture buffer */
		343	min_dpb_size = image_size * 3;
		344	break;
		345
		346	case 4: /* MPEG4 */
		347
		348	/* reference picture buffer */
		349	min_dpb_size = image_size * 3;
		350
		351	/* CM */
		352	min_dpb_size += width_in_mb * height_in_mb * 64;
		353
		354	/* IT surface buffer */
		355	min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
		356	break;
		357
		358	default:
		359	DRM_ERROR("UVD codec not handled %d!\n", stream_type);
		360	return -EINVAL;
		361	}
		362
		363	if (width > pitch) {
		364	DRM_ERROR("Invalid UVD decoding target pitch!\n");
		365	return -EINVAL;
		366	}
		367
		368	if (dpb_size < min_dpb_size) {
		369	DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
		370	dpb_size, min_dpb_size);
		371	return -EINVAL;
		372	}
		373
		374	buf_sizes[0x1] = dpb_size;
		375	buf_sizes[0x2] = image_size;
		376	return 0;
		377	}
		378
		379	static int radeon_uvd_cs_msg(struct radeon_cs_parser p, struct radeon_bo bo,
		380	unsigned offset, unsigned buf_sizes[])
		381	{
		382	int32_t *msg, msg_type, handle;
		383	unsigned img_size = 0;
5271	serge	384	struct fence *f;
5078	serge	385	void *ptr;
		386
		387	int i, r;
		388
		389	if (offset & 0x3F) {
		390	DRM_ERROR("UVD messages must be 64 byte aligned!\n");
		391	return -EINVAL;
		392	}
		393
5271	serge	394	f = reservation_object_get_excl(bo->tbo.resv);
		395	if (f) {
		396	r = radeon_fence_wait((struct radeon_fence *)f, false);
5078	serge	397	if (r) {
		398	DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
		399	return r;
		400	}
		401	}
		402
		403	r = radeon_bo_kmap(bo, &ptr);
		404	if (r) {
		405	DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
		406	return r;
		407	}
		408
		409	msg = ptr + offset;
		410
		411	msg_type = msg[1];
		412	handle = msg[2];
		413
		414	if (handle == 0) {
		415	DRM_ERROR("Invalid UVD handle!\n");
		416	return -EINVAL;
		417	}
		418
		419	if (msg_type == 1) {
		420	/* it's a decode msg, calc buffer sizes */
		421	r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
		422	/* calc image size (width * height) */
		423	img_size = msg[6] * msg[7];
		424	radeon_bo_kunmap(bo);
		425	if (r)
		426	return r;
		427
		428	} else if (msg_type == 2) {
		429	/* it's a destroy msg, free the handle */
		430	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
		431	atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
		432	radeon_bo_kunmap(bo);
		433	return 0;
		434	} else {
		435	/* it's a create msg, calc image size (width * height) */
		436	img_size = msg[7] * msg[8];
		437	radeon_bo_kunmap(bo);
		438
		439	if (msg_type != 0) {
		440	DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
		441	return -EINVAL;
		442	}
		443
		444	/* it's a create msg, no special handling needed */
		445	}
		446
		447	/* create or decode, validate the handle */
		448	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		449	if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
		450	return 0;
		451	}
		452
		453	/* handle not found try to alloc a new one */
		454	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		455	if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
		456	p->rdev->uvd.filp[i] = p->filp;
		457	p->rdev->uvd.img_size[i] = img_size;
		458	return 0;
		459	}
		460	}
		461
		462	DRM_ERROR("No more free UVD handles!\n");
		463	return -EINVAL;
		464	}
		465
		466	static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
		467	int data0, int data1,
		468	unsigned buf_sizes[], bool *has_msg_cmd)
		469	{
		470	struct radeon_cs_chunk *relocs_chunk;
5271	serge	471	struct radeon_bo_list *reloc;
5078	serge	472	unsigned idx, cmd, offset;
		473	uint64_t start, end;
		474	int r;
		475
5271	serge	476	relocs_chunk = p->chunk_relocs;
5078	serge	477	offset = radeon_get_ib_value(p, data0);
		478	idx = radeon_get_ib_value(p, data1);
		479	if (idx >= relocs_chunk->length_dw) {
		480	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		481	idx, relocs_chunk->length_dw);
		482	return -EINVAL;
		483	}
		484
5271	serge	485	reloc = &p->relocs[(idx / 4)];
5078	serge	486	start = reloc->gpu_offset;
		487	end = start + radeon_bo_size(reloc->robj);
		488	start += offset;
		489
		490	p->ib.ptr[data0] = start & 0xFFFFFFFF;
		491	p->ib.ptr[data1] = start >> 32;
		492
		493	cmd = radeon_get_ib_value(p, p->idx) >> 1;
		494
		495	if (cmd < 0x4) {
		496	if (end <= start) {
		497	DRM_ERROR("invalid reloc offset %X!\n", offset);
		498	return -EINVAL;
		499	}
		500	if ((end - start) < buf_sizes[cmd]) {
		501	DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
		502	(unsigned)(end - start), buf_sizes[cmd]);
		503	return -EINVAL;
		504	}
		505
		506	} else if (cmd != 0x100) {
		507	DRM_ERROR("invalid UVD command %X!\n", cmd);
		508	return -EINVAL;
		509	}
		510
		511	if ((start >> 28) != ((end - 1) >> 28)) {
		512	DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
		513	start, end);
		514	return -EINVAL;
		515	}
		516
		517	/* TODO: is this still necessary on NI+ ? */
		518	if ((cmd == 0 \|\| cmd == 0x3) &&
		519	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
		520	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
		521	start, end);
		522	return -EINVAL;
		523	}
		524
		525	if (cmd == 0) {
		526	if (*has_msg_cmd) {
		527	DRM_ERROR("More than one message in a UVD-IB!\n");
		528	return -EINVAL;
		529	}
		530	*has_msg_cmd = true;
		531	r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
		532	if (r)
		533	return r;
		534	} else if (!*has_msg_cmd) {
		535	DRM_ERROR("Message needed before other commands are send!\n");
		536	return -EINVAL;
		537	}
		538
		539	return 0;
		540	}
		541
		542	static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
		543	struct radeon_cs_packet *pkt,
		544	int data0, int data1,
		545	unsigned buf_sizes[],
		546	bool *has_msg_cmd)
		547	{
		548	int i, r;
		549
		550	p->idx++;
		551	for (i = 0; i <= pkt->count; ++i) {
		552	switch (pkt->reg + i*4) {
		553	case UVD_GPCOM_VCPU_DATA0:
		554	*data0 = p->idx;
		555	break;
		556	case UVD_GPCOM_VCPU_DATA1:
		557	*data1 = p->idx;
		558	break;
		559	case UVD_GPCOM_VCPU_CMD:
		560	r = radeon_uvd_cs_reloc(p, data0, data1,
		561	buf_sizes, has_msg_cmd);
		562	if (r)
		563	return r;
		564	break;
		565	case UVD_ENGINE_CNTL:
		566	break;
		567	default:
		568	DRM_ERROR("Invalid reg 0x%X!\n",
		569	pkt->reg + i*4);
		570	return -EINVAL;
		571	}
		572	p->idx++;
		573	}
		574	return 0;
		575	}
		576
		577	int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
		578	{
		579	struct radeon_cs_packet pkt;
		580	int r, data0 = 0, data1 = 0;
		581
		582	/* does the IB has a msg command */
		583	bool has_msg_cmd = false;
		584
		585	/* minimum buffer sizes */
		586	unsigned buf_sizes[] = {
		587	[0x00000000] = 2048,
		588	[0x00000001] = 32 * 1024 * 1024,
		589	[0x00000002] = 2048 * 1152 * 3,
		590	[0x00000003] = 2048,
		591	};
		592
5271	serge	593	if (p->chunk_ib->length_dw % 16) {
5078	serge	594	DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
5271	serge	595	p->chunk_ib->length_dw);
5078	serge	596	return -EINVAL;
		597	}
		598
5271	serge	599	if (p->chunk_relocs == NULL) {
5078	serge	600	DRM_ERROR("No relocation chunk !\n");
		601	return -EINVAL;
		602	}
		603
		604
		605	do {
		606	r = radeon_cs_packet_parse(p, &pkt, p->idx);
		607	if (r)
		608	return r;
		609	switch (pkt.type) {
		610	case RADEON_PACKET_TYPE0:
		611	r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
		612	buf_sizes, &has_msg_cmd);
		613	if (r)
		614	return r;
		615	break;
		616	case RADEON_PACKET_TYPE2:
		617	p->idx += pkt.count + 2;
		618	break;
		619	default:
		620	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		621	return -EINVAL;
		622	}
5271	serge	623	} while (p->idx < p->chunk_ib->length_dw);
5078	serge	624
		625	if (!has_msg_cmd) {
		626	DRM_ERROR("UVD-IBs need a msg command!\n");
		627	return -EINVAL;
		628	}
		629
		630	return 0;
		631	}
		632
		633	static int radeon_uvd_send_msg(struct radeon_device *rdev,
5271	serge	634	int ring, uint64_t addr,
5078	serge	635	struct radeon_fence **fence)
		636	{
		637	struct radeon_ib ib;
		638	int i, r;
		639
5271	serge	640	r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
5078	serge	641	if (r)
		642	return r;
		643
		644	ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
		645	ib.ptr[1] = addr;
		646	ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
		647	ib.ptr[3] = addr >> 32;
		648	ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
		649	ib.ptr[5] = 0;
		650	for (i = 6; i < 16; ++i)
		651	ib.ptr[i] = PACKET2(0);
		652	ib.length_dw = 16;
		653
		654	r = radeon_ib_schedule(rdev, &ib, NULL, false);
		655
		656	if (fence)
		657	*fence = radeon_fence_ref(ib.fence);
		658
		659	radeon_ib_free(rdev, &ib);
		660	return r;
		661	}
		662
		663	/* multiple fence commands without any stream commands in between can
		664	crash the vcpu so just try to emmit a dummy create/destroy msg to
		665	avoid this */
		666	int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
		667	uint32_t handle, struct radeon_fence **fence)
		668	{
5271	serge	669	/* we use the last page of the vcpu bo for the UVD message */
		670	uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
		671	RADEON_GPU_PAGE_SIZE;
		672
		673	uint32_t *msg = rdev->uvd.cpu_addr + offs;
		674	uint64_t addr = rdev->uvd.gpu_addr + offs;
		675
5078	serge	676	int r, i;
		677
5271	serge	678	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
5078	serge	679	if (r)
		680	return r;
		681
		682	/* stitch together an UVD create msg */
		683	msg[0] = cpu_to_le32(0x00000de4);
		684	msg[1] = cpu_to_le32(0x00000000);
		685	msg[2] = cpu_to_le32(handle);
		686	msg[3] = cpu_to_le32(0x00000000);
		687	msg[4] = cpu_to_le32(0x00000000);
		688	msg[5] = cpu_to_le32(0x00000000);
		689	msg[6] = cpu_to_le32(0x00000000);
		690	msg[7] = cpu_to_le32(0x00000780);
		691	msg[8] = cpu_to_le32(0x00000440);
		692	msg[9] = cpu_to_le32(0x00000000);
		693	msg[10] = cpu_to_le32(0x01b37000);
		694	for (i = 11; i < 1024; ++i)
		695	msg[i] = cpu_to_le32(0x0);
		696
5271	serge	697	r = radeon_uvd_send_msg(rdev, ring, addr, fence);
		698	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		699	return r;
5078	serge	700	}
		701
		702	int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
		703	uint32_t handle, struct radeon_fence **fence)
		704	{
5271	serge	705	/* we use the last page of the vcpu bo for the UVD message */
		706	uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
		707	RADEON_GPU_PAGE_SIZE;
		708
		709	uint32_t *msg = rdev->uvd.cpu_addr + offs;
		710	uint64_t addr = rdev->uvd.gpu_addr + offs;
		711
5078	serge	712	int r, i;
		713
5271	serge	714	r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
5078	serge	715	if (r)
		716	return r;
		717
		718	/* stitch together an UVD destroy msg */
		719	msg[0] = cpu_to_le32(0x00000de4);
		720	msg[1] = cpu_to_le32(0x00000002);
		721	msg[2] = cpu_to_le32(handle);
		722	msg[3] = cpu_to_le32(0x00000000);
		723	for (i = 4; i < 1024; ++i)
		724	msg[i] = cpu_to_le32(0x0);
		725
5271	serge	726	r = radeon_uvd_send_msg(rdev, ring, addr, fence);
		727	radeon_bo_unreserve(rdev->uvd.vcpu_bo);
		728	return r;
5078	serge	729	}
		730
		731	/**
		732	* radeon_uvd_count_handles - count number of open streams
		733	*
		734	* @rdev: radeon_device pointer
		735	* @sd: number of SD streams
		736	* @hd: number of HD streams
		737	*
		738	* Count the number of open SD/HD streams as a hint for power mangement
		739	*/
		740	static void radeon_uvd_count_handles(struct radeon_device *rdev,
		741	unsigned sd, unsigned hd)
		742	{
		743	unsigned i;
		744
		745	*sd = 0;
		746	*hd = 0;
		747
		748	for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
		749	if (!atomic_read(&rdev->uvd.handles[i]))
		750	continue;
		751
		752	if (rdev->uvd.img_size[i] >= 720*576)
		753	++(*hd);
		754	else
		755	++(*sd);
		756	}
		757	}
		758
		759	static void radeon_uvd_idle_work_handler(struct work_struct *work)
		760	{
		761	struct radeon_device *rdev =
		762	container_of(work, struct radeon_device, uvd.idle_work.work);
		763
		764	if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
		765	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
		766	radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
		767	&rdev->pm.dpm.hd);
		768	radeon_dpm_enable_uvd(rdev, false);
		769	} else {
		770	radeon_set_uvd_clocks(rdev, 0, 0);
		771	}
		772	} else {
		773	schedule_delayed_work(&rdev->uvd.idle_work,
		774	msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
		775	}
		776	}
		777
		778	void radeon_uvd_note_usage(struct radeon_device *rdev)
		779	{
		780	bool streams_changed = false;
		781	bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
		782	set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
		783	msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
		784
		785	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
		786	unsigned hd = 0, sd = 0;
		787	radeon_uvd_count_handles(rdev, &sd, &hd);
		788	if ((rdev->pm.dpm.sd != sd) \|\|
		789	(rdev->pm.dpm.hd != hd)) {
		790	rdev->pm.dpm.sd = sd;
		791	rdev->pm.dpm.hd = hd;
		792	/* disable this for now */
		793	/streams_changed = true;/
		794	}
		795	}
		796
		797	if (set_clocks \|\| streams_changed) {
		798	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
		799	radeon_dpm_enable_uvd(rdev, true);
		800	} else {
		801	radeon_set_uvd_clocks(rdev, 53300, 40000);
		802	}
		803	}
		804	}
		805
		806	static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
		807	unsigned target_freq,
		808	unsigned pd_min,
		809	unsigned pd_even)
		810	{
		811	unsigned post_div = vco_freq / target_freq;
		812
		813	/* adjust to post divider minimum value */
		814	if (post_div < pd_min)
		815	post_div = pd_min;
		816
		817	/* we alway need a frequency less than or equal the target */
		818	if ((vco_freq / post_div) > target_freq)
		819	post_div += 1;
		820
		821	/* post dividers above a certain value must be even */
		822	if (post_div > pd_even && post_div % 2)
		823	post_div += 1;
		824
		825	return post_div;
		826	}
		827
		828	/**
		829	* radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
		830	*
		831	* @rdev: radeon_device pointer
		832	* @vclk: wanted VCLK
		833	* @dclk: wanted DCLK
		834	* @vco_min: minimum VCO frequency
		835	* @vco_max: maximum VCO frequency
		836	* @fb_factor: factor to multiply vco freq with
		837	* @fb_mask: limit and bitmask for feedback divider
		838	* @pd_min: post divider minimum
		839	* @pd_max: post divider maximum
		840	* @pd_even: post divider must be even above this value
		841	* @optimal_fb_div: resulting feedback divider
		842	* @optimal_vclk_div: resulting vclk post divider
		843	* @optimal_dclk_div: resulting dclk post divider
		844	*
		845	* Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
		846	* Returns zero on success -EINVAL on error.
		847	*/
		848	int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
		849	unsigned vclk, unsigned dclk,
		850	unsigned vco_min, unsigned vco_max,
		851	unsigned fb_factor, unsigned fb_mask,
		852	unsigned pd_min, unsigned pd_max,
		853	unsigned pd_even,
		854	unsigned *optimal_fb_div,
		855	unsigned *optimal_vclk_div,
		856	unsigned *optimal_dclk_div)
		857	{
		858	unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
		859
		860	/* start off with something large */
		861	unsigned optimal_score = ~0;
		862
		863	/* loop through vco from low to high */
		864	vco_min = max(max(vco_min, vclk), dclk);
		865	for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
		866
		867	uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
		868	unsigned vclk_div, dclk_div, score;
		869
		870	do_div(fb_div, ref_freq);
		871
		872	/* fb div out of range ? */
		873	if (fb_div > fb_mask)
		874	break; /* it can oly get worse */
		875
		876	fb_div &= fb_mask;
		877
		878	/* calc vclk divider with current vco freq */
		879	vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
		880	pd_min, pd_even);
		881	if (vclk_div > pd_max)
		882	break; /* vco is too big, it has to stop */
		883
		884	/* calc dclk divider with current vco freq */
		885	dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
		886	pd_min, pd_even);
		887	if (vclk_div > pd_max)
		888	break; /* vco is too big, it has to stop */
		889
		890	/* calc score with current vco freq */
		891	score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
		892
		893	/* determine if this vco setting is better than current optimal settings */
		894	if (score < optimal_score) {
		895	*optimal_fb_div = fb_div;
		896	*optimal_vclk_div = vclk_div;
		897	*optimal_dclk_div = dclk_div;
		898	optimal_score = score;
		899	if (optimal_score == 0)
		900	break; /* it can't get better than this */
		901	}
		902	}
		903
		904	/* did we found a valid setup ? */
		905	if (optimal_score == ~0)
		906	return -EINVAL;
		907
		908	return 0;
		909	}
		910
		911	int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
		912	unsigned cg_upll_func_cntl)
		913	{
		914	unsigned i;
		915
		916	/* make sure UPLL_CTLREQ is deasserted */
		917	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
		918
		919	mdelay(10);
		920
		921	/* assert UPLL_CTLREQ */
		922	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
		923
		924	/* wait for CTLACK and CTLACK2 to get asserted */
		925	for (i = 0; i < 100; ++i) {
		926	uint32_t mask = UPLL_CTLACK_MASK \| UPLL_CTLACK2_MASK;
		927	if ((RREG32(cg_upll_func_cntl) & mask) == mask)
		928	break;
		929	mdelay(10);
		930	}
		931
		932	/* deassert UPLL_CTLREQ */
		933	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
		934
		935	if (i == 100) {
		936	DRM_ERROR("Timeout setting UVD clocks!\n");
		937	return -ETIMEDOUT;
		938	}
		939
		940	return 0;
		941	}

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(root)/drivers/video/drm/radeon/radeon_uvd.c – Rev 5271