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Rev | Author | Line No. | Line |
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5078 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | * Christian König |
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28 | */ |
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29 | #include |
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30 | #include "radeon.h" |
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31 | |||
32 | /* |
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33 | * Rings |
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34 | * Most engines on the GPU are fed via ring buffers. Ring |
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35 | * buffers are areas of GPU accessible memory that the host |
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36 | * writes commands into and the GPU reads commands out of. |
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37 | * There is a rptr (read pointer) that determines where the |
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38 | * GPU is currently reading, and a wptr (write pointer) |
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39 | * which determines where the host has written. When the |
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40 | * pointers are equal, the ring is idle. When the host |
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41 | * writes commands to the ring buffer, it increments the |
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42 | * wptr. The GPU then starts fetching commands and executes |
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43 | * them until the pointers are equal again. |
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44 | */ |
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45 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
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46 | |||
47 | /** |
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48 | * radeon_ring_supports_scratch_reg - check if the ring supports |
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49 | * writing to scratch registers |
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50 | * |
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51 | * @rdev: radeon_device pointer |
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52 | * @ring: radeon_ring structure holding ring information |
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53 | * |
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54 | * Check if a specific ring supports writing to scratch registers (all asics). |
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55 | * Returns true if the ring supports writing to scratch regs, false if not. |
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56 | */ |
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57 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
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58 | struct radeon_ring *ring) |
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59 | { |
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60 | switch (ring->idx) { |
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61 | case RADEON_RING_TYPE_GFX_INDEX: |
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62 | case CAYMAN_RING_TYPE_CP1_INDEX: |
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63 | case CAYMAN_RING_TYPE_CP2_INDEX: |
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64 | return true; |
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65 | default: |
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66 | return false; |
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67 | } |
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68 | } |
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69 | |||
70 | /** |
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71 | * radeon_ring_free_size - update the free size |
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72 | * |
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73 | * @rdev: radeon_device pointer |
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74 | * @ring: radeon_ring structure holding ring information |
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75 | * |
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76 | * Update the free dw slots in the ring buffer (all asics). |
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77 | */ |
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78 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
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79 | { |
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80 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
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81 | |||
82 | /* This works because ring_size is a power of 2 */ |
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83 | ring->ring_free_dw = rptr + (ring->ring_size / 4); |
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84 | ring->ring_free_dw -= ring->wptr; |
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85 | ring->ring_free_dw &= ring->ptr_mask; |
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86 | if (!ring->ring_free_dw) { |
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87 | /* this is an empty ring */ |
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88 | ring->ring_free_dw = ring->ring_size / 4; |
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89 | /* update lockup info to avoid false positive */ |
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90 | radeon_ring_lockup_update(rdev, ring); |
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91 | } |
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92 | } |
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93 | |||
94 | /** |
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95 | * radeon_ring_alloc - allocate space on the ring buffer |
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96 | * |
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97 | * @rdev: radeon_device pointer |
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98 | * @ring: radeon_ring structure holding ring information |
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99 | * @ndw: number of dwords to allocate in the ring buffer |
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100 | * |
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101 | * Allocate @ndw dwords in the ring buffer (all asics). |
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102 | * Returns 0 on success, error on failure. |
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103 | */ |
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104 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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105 | { |
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106 | int r; |
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107 | |||
108 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
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109 | if (ndw > (ring->ring_size / 4)) |
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110 | return -ENOMEM; |
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111 | /* Align requested size with padding so unlock_commit can |
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112 | * pad safely */ |
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113 | radeon_ring_free_size(rdev, ring); |
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114 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
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115 | while (ndw > (ring->ring_free_dw - 1)) { |
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116 | radeon_ring_free_size(rdev, ring); |
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117 | if (ndw < ring->ring_free_dw) { |
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118 | break; |
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119 | } |
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120 | r = radeon_fence_wait_next(rdev, ring->idx); |
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121 | if (r) |
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122 | return r; |
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123 | } |
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124 | ring->count_dw = ndw; |
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125 | ring->wptr_old = ring->wptr; |
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126 | return 0; |
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127 | } |
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128 | |||
129 | /** |
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130 | * radeon_ring_lock - lock the ring and allocate space on it |
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131 | * |
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132 | * @rdev: radeon_device pointer |
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133 | * @ring: radeon_ring structure holding ring information |
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134 | * @ndw: number of dwords to allocate in the ring buffer |
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135 | * |
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136 | * Lock the ring and allocate @ndw dwords in the ring buffer |
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137 | * (all asics). |
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138 | * Returns 0 on success, error on failure. |
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139 | */ |
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140 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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141 | { |
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142 | int r; |
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143 | |||
144 | mutex_lock(&rdev->ring_lock); |
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145 | r = radeon_ring_alloc(rdev, ring, ndw); |
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146 | if (r) { |
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147 | mutex_unlock(&rdev->ring_lock); |
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148 | return r; |
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149 | } |
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150 | return 0; |
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151 | } |
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152 | |||
153 | /** |
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154 | * radeon_ring_commit - tell the GPU to execute the new |
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155 | * commands on the ring buffer |
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156 | * |
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157 | * @rdev: radeon_device pointer |
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158 | * @ring: radeon_ring structure holding ring information |
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159 | * @hdp_flush: Whether or not to perform an HDP cache flush |
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160 | * |
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161 | * Update the wptr (write pointer) to tell the GPU to |
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162 | * execute new commands on the ring buffer (all asics). |
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163 | */ |
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164 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
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165 | bool hdp_flush) |
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166 | { |
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167 | /* If we are emitting the HDP flush via the ring buffer, we need to |
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168 | * do it before padding. |
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169 | */ |
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170 | if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) |
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171 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); |
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172 | /* We pad to match fetch size */ |
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173 | while (ring->wptr & ring->align_mask) { |
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174 | radeon_ring_write(ring, ring->nop); |
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175 | } |
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176 | mb(); |
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177 | /* If we are emitting the HDP flush via MMIO, we need to do it after |
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178 | * all CPU writes to VRAM finished. |
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179 | */ |
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180 | if (hdp_flush && rdev->asic->mmio_hdp_flush) |
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181 | rdev->asic->mmio_hdp_flush(rdev); |
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182 | radeon_ring_set_wptr(rdev, ring); |
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183 | } |
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184 | |||
185 | /** |
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186 | * radeon_ring_unlock_commit - tell the GPU to execute the new |
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187 | * commands on the ring buffer and unlock it |
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188 | * |
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189 | * @rdev: radeon_device pointer |
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190 | * @ring: radeon_ring structure holding ring information |
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191 | * @hdp_flush: Whether or not to perform an HDP cache flush |
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192 | * |
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193 | * Call radeon_ring_commit() then unlock the ring (all asics). |
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194 | */ |
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195 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
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196 | bool hdp_flush) |
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197 | { |
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198 | radeon_ring_commit(rdev, ring, hdp_flush); |
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199 | mutex_unlock(&rdev->ring_lock); |
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200 | } |
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201 | |||
202 | /** |
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203 | * radeon_ring_undo - reset the wptr |
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204 | * |
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205 | * @ring: radeon_ring structure holding ring information |
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206 | * |
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207 | * Reset the driver's copy of the wptr (all asics). |
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208 | */ |
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209 | void radeon_ring_undo(struct radeon_ring *ring) |
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210 | { |
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211 | ring->wptr = ring->wptr_old; |
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212 | } |
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213 | |||
214 | /** |
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215 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring |
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216 | * |
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217 | * @ring: radeon_ring structure holding ring information |
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218 | * |
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219 | * Call radeon_ring_undo() then unlock the ring (all asics). |
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220 | */ |
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221 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
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222 | { |
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223 | radeon_ring_undo(ring); |
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224 | mutex_unlock(&rdev->ring_lock); |
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225 | } |
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226 | |||
227 | /** |
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228 | * radeon_ring_lockup_update - update lockup variables |
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229 | * |
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230 | * @ring: radeon_ring structure holding ring information |
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231 | * |
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232 | * Update the last rptr value and timestamp (all asics). |
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233 | */ |
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234 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
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235 | struct radeon_ring *ring) |
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236 | { |
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237 | atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring)); |
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238 | atomic64_set(&ring->last_activity, jiffies_64); |
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239 | } |
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240 | |||
241 | /** |
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242 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
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243 | * @rdev: radeon device structure |
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244 | * @ring: radeon_ring structure holding ring information |
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245 | * |
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246 | */ |
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247 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
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248 | { |
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249 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
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250 | uint64_t last = atomic64_read(&ring->last_activity); |
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251 | uint64_t elapsed; |
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252 | |||
253 | if (rptr != atomic_read(&ring->last_rptr)) { |
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254 | /* ring is still working, no lockup */ |
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255 | radeon_ring_lockup_update(rdev, ring); |
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256 | return false; |
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257 | } |
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258 | |||
259 | elapsed = jiffies_to_msecs(jiffies_64 - last); |
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260 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
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261 | dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n", |
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262 | ring->idx, elapsed); |
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263 | return true; |
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264 | } |
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265 | /* give a chance to the GPU ... */ |
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266 | return false; |
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267 | } |
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268 | |||
269 | /** |
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270 | * radeon_ring_backup - Back up the content of a ring |
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271 | * |
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272 | * @rdev: radeon_device pointer |
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273 | * @ring: the ring we want to back up |
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274 | * |
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275 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
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276 | */ |
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277 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
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278 | uint32_t **data) |
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279 | { |
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280 | unsigned size, ptr, i; |
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281 | |||
282 | /* just in case lock the ring */ |
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283 | mutex_lock(&rdev->ring_lock); |
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284 | *data = NULL; |
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285 | |||
286 | if (ring->ring_obj == NULL) { |
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287 | mutex_unlock(&rdev->ring_lock); |
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288 | return 0; |
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289 | } |
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290 | |||
291 | /* it doesn't make sense to save anything if all fences are signaled */ |
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292 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
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293 | mutex_unlock(&rdev->ring_lock); |
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294 | return 0; |
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295 | } |
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296 | |||
297 | /* calculate the number of dw on the ring */ |
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298 | if (ring->rptr_save_reg) |
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299 | ptr = RREG32(ring->rptr_save_reg); |
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300 | else if (rdev->wb.enabled) |
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301 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); |
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302 | else { |
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303 | /* no way to read back the next rptr */ |
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304 | mutex_unlock(&rdev->ring_lock); |
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305 | return 0; |
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306 | } |
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307 | |||
308 | size = ring->wptr + (ring->ring_size / 4); |
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309 | size -= ptr; |
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310 | size &= ring->ptr_mask; |
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311 | if (size == 0) { |
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312 | mutex_unlock(&rdev->ring_lock); |
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313 | return 0; |
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314 | } |
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315 | |||
316 | /* and then save the content of the ring */ |
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6104 | serge | 317 | *data = drm_malloc_ab(size, sizeof(uint32_t)); |
5078 | serge | 318 | if (!*data) { |
319 | mutex_unlock(&rdev->ring_lock); |
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320 | return 0; |
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321 | } |
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322 | for (i = 0; i < size; ++i) { |
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323 | (*data)[i] = ring->ring[ptr++]; |
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324 | ptr &= ring->ptr_mask; |
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325 | } |
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326 | |||
327 | mutex_unlock(&rdev->ring_lock); |
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328 | return size; |
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329 | } |
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330 | |||
331 | /** |
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332 | * radeon_ring_restore - append saved commands to the ring again |
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333 | * |
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334 | * @rdev: radeon_device pointer |
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335 | * @ring: ring to append commands to |
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336 | * @size: number of dwords we want to write |
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337 | * @data: saved commands |
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338 | * |
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339 | * Allocates space on the ring and restore the previously saved commands. |
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340 | */ |
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341 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
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342 | unsigned size, uint32_t *data) |
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343 | { |
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344 | int i, r; |
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345 | |||
346 | if (!size || !data) |
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347 | return 0; |
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348 | |||
349 | /* restore the saved ring content */ |
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350 | r = radeon_ring_lock(rdev, ring, size); |
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351 | if (r) |
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352 | return r; |
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353 | |||
354 | for (i = 0; i < size; ++i) { |
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355 | radeon_ring_write(ring, data[i]); |
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356 | } |
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357 | |||
358 | radeon_ring_unlock_commit(rdev, ring, false); |
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359 | kfree(data); |
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360 | return 0; |
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361 | } |
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362 | |||
363 | /** |
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364 | * radeon_ring_init - init driver ring struct. |
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365 | * |
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366 | * @rdev: radeon_device pointer |
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367 | * @ring: radeon_ring structure holding ring information |
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368 | * @ring_size: size of the ring |
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369 | * @rptr_offs: offset of the rptr writeback location in the WB buffer |
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370 | * @nop: nop packet for this ring |
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371 | * |
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372 | * Initialize the driver information for the selected ring (all asics). |
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373 | * Returns 0 on success, error on failure. |
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374 | */ |
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375 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
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376 | unsigned rptr_offs, u32 nop) |
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377 | { |
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378 | int r; |
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379 | |||
380 | ring->ring_size = ring_size; |
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381 | ring->rptr_offs = rptr_offs; |
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382 | ring->nop = nop; |
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383 | /* Allocate ring buffer */ |
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384 | if (ring->ring_obj == NULL) { |
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385 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
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5271 | serge | 386 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
5078 | serge | 387 | NULL, &ring->ring_obj); |
388 | if (r) { |
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389 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
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390 | return r; |
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391 | } |
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392 | r = radeon_bo_reserve(ring->ring_obj, false); |
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393 | if (unlikely(r != 0)) |
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394 | return r; |
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395 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
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396 | &ring->gpu_addr); |
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397 | if (r) { |
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398 | radeon_bo_unreserve(ring->ring_obj); |
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399 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
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400 | return r; |
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401 | } |
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402 | r = radeon_bo_kmap(ring->ring_obj, |
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403 | (void **)&ring->ring); |
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404 | radeon_bo_unreserve(ring->ring_obj); |
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405 | if (r) { |
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406 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
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407 | return r; |
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408 | } |
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409 | } |
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410 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
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411 | ring->ring_free_dw = ring->ring_size / 4; |
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412 | if (rdev->wb.enabled) { |
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413 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); |
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414 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; |
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415 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; |
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416 | } |
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417 | if (radeon_debugfs_ring_init(rdev, ring)) { |
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418 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
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419 | } |
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420 | radeon_ring_lockup_update(rdev, ring); |
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421 | return 0; |
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422 | } |
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423 | |||
424 | /** |
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425 | * radeon_ring_fini - tear down the driver ring struct. |
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426 | * |
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427 | * @rdev: radeon_device pointer |
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428 | * @ring: radeon_ring structure holding ring information |
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429 | * |
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430 | * Tear down the driver information for the selected ring (all asics). |
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431 | */ |
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432 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
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433 | { |
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434 | int r; |
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435 | struct radeon_bo *ring_obj; |
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436 | |||
437 | mutex_lock(&rdev->ring_lock); |
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438 | ring_obj = ring->ring_obj; |
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439 | ring->ready = false; |
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440 | ring->ring = NULL; |
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441 | ring->ring_obj = NULL; |
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442 | mutex_unlock(&rdev->ring_lock); |
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443 | |||
444 | if (ring_obj) { |
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445 | r = radeon_bo_reserve(ring_obj, false); |
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446 | if (likely(r == 0)) { |
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447 | radeon_bo_kunmap(ring_obj); |
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448 | radeon_bo_unpin(ring_obj); |
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449 | radeon_bo_unreserve(ring_obj); |
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450 | } |
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451 | radeon_bo_unref(&ring_obj); |
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452 | } |
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453 | } |
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454 | |||
455 | /* |
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456 | * Debugfs info |
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457 | */ |
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458 | #if defined(CONFIG_DEBUG_FS) |
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459 | |||
460 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
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461 | { |
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462 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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463 | struct drm_device *dev = node->minor->dev; |
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464 | struct radeon_device *rdev = dev->dev_private; |
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465 | int ridx = *(int*)node->info_ent->data; |
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466 | struct radeon_ring *ring = &rdev->ring[ridx]; |
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467 | |||
468 | uint32_t rptr, wptr, rptr_next; |
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469 | unsigned count, i, j; |
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470 | |||
471 | radeon_ring_free_size(rdev, ring); |
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472 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
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473 | |||
474 | wptr = radeon_ring_get_wptr(rdev, ring); |
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475 | seq_printf(m, "wptr: 0x%08x [%5d]\n", |
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476 | wptr, wptr); |
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477 | |||
478 | rptr = radeon_ring_get_rptr(rdev, ring); |
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479 | seq_printf(m, "rptr: 0x%08x [%5d]\n", |
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480 | rptr, rptr); |
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481 | |||
482 | if (ring->rptr_save_reg) { |
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483 | rptr_next = RREG32(ring->rptr_save_reg); |
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484 | seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", |
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485 | ring->rptr_save_reg, rptr_next, rptr_next); |
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486 | } else |
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487 | rptr_next = ~0; |
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488 | |||
489 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", |
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490 | ring->wptr, ring->wptr); |
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491 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", |
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492 | ring->last_semaphore_signal_addr); |
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493 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", |
||
494 | ring->last_semaphore_wait_addr); |
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495 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
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496 | seq_printf(m, "%u dwords in ring\n", count); |
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497 | |||
6104 | serge | 498 | if (!ring->ring) |
5078 | serge | 499 | return 0; |
500 | |||
501 | /* print 8 dw before current rptr as often it's the last executed |
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502 | * packet that is the root issue |
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503 | */ |
||
504 | i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
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505 | for (j = 0; j <= (count + 32); j++) { |
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506 | seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); |
||
507 | if (rptr == i) |
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508 | seq_puts(m, " *"); |
||
509 | if (rptr_next == i) |
||
510 | seq_puts(m, " #"); |
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511 | seq_puts(m, "\n"); |
||
512 | i = (i + 1) & ring->ptr_mask; |
||
513 | } |
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514 | return 0; |
||
515 | } |
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516 | |||
517 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
||
518 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
||
519 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
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520 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; |
||
521 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; |
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522 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; |
||
523 | static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX; |
||
524 | static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX; |
||
525 | |||
526 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
||
527 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
||
528 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, |
||
529 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, |
||
530 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, |
||
531 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, |
||
532 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, |
||
533 | {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index}, |
||
534 | {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index}, |
||
535 | }; |
||
536 | |||
537 | #endif |
||
538 | |||
539 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
||
540 | { |
||
541 | #if defined(CONFIG_DEBUG_FS) |
||
542 | unsigned i; |
||
543 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
||
544 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
||
545 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
||
546 | unsigned r; |
||
547 | |||
548 | if (&rdev->ring[ridx] != ring) |
||
549 | continue; |
||
550 | |||
551 | r = radeon_debugfs_add_files(rdev, info, 1); |
||
552 | if (r) |
||
553 | return r; |
||
554 | } |
||
555 | #endif |
||
556 | return 0; |
||
557 | }>=>>>> |