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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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2997 | Serge | 27 | * Christian Konig |
1117 | serge | 28 | */ |
1179 | serge | 29 | #include |
1963 | serge | 30 | #include |
2997 | Serge | 31 | #include |
32 | #include |
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1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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36 | |||
37 | /* |
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2997 | Serge | 38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where |
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40 | * commands are stored. You can put a pointer to the IB in the |
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41 | * command ring and the hw will fetch the commands from the IB |
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42 | * and execute them. Generally userspace acceleration drivers |
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43 | * produce command buffers which are send to the kernel and |
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44 | * put in IBs for execution by the requested ring. |
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1117 | serge | 45 | */ |
2997 | Serge | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
47 | |||
48 | /** |
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49 | * radeon_ib_get - request an IB (Indirect Buffer) |
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50 | * |
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51 | * @rdev: radeon_device pointer |
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52 | * @ring: ring index the IB is associated with |
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53 | * @ib: IB object returned |
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54 | * @size: requested IB size |
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55 | * |
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56 | * Request an IB (all asics). IBs are allocated using the |
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57 | * suballocator. |
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58 | * Returns 0 on success, error on failure. |
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59 | */ |
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60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
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61 | struct radeon_ib *ib, struct radeon_vm *vm, |
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62 | unsigned size) |
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1117 | serge | 63 | { |
2997 | Serge | 64 | int i, r; |
1117 | serge | 65 | |
2997 | Serge | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
1117 | serge | 67 | if (r) { |
2997 | Serge | 68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
1117 | serge | 69 | return r; |
70 | } |
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2997 | Serge | 71 | |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
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2005 | serge | 73 | if (r) { |
74 | return r; |
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75 | } |
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2997 | Serge | 76 | |
77 | ib->ring = ring; |
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78 | ib->fence = NULL; |
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79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
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80 | ib->vm = vm; |
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81 | if (vm) { |
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82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
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83 | * space and soffset is the offset inside the pool bo |
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84 | */ |
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85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
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86 | } else { |
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87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
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2005 | serge | 88 | } |
2997 | Serge | 89 | ib->is_const_ib = false; |
90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
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91 | ib->sync_to[i] = NULL; |
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92 | |||
1428 | serge | 93 | return 0; |
1117 | serge | 94 | } |
95 | |||
2997 | Serge | 96 | /** |
97 | * radeon_ib_free - free an IB (Indirect Buffer) |
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98 | * |
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99 | * @rdev: radeon_device pointer |
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100 | * @ib: IB object to free |
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101 | * |
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102 | * Free an IB (all asics). |
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103 | */ |
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104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
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1117 | serge | 105 | { |
2997 | Serge | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
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108 | radeon_fence_unref(&ib->fence); |
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1117 | serge | 109 | } |
110 | |||
2997 | Serge | 111 | /** |
3764 | Serge | 112 | * radeon_ib_sync_to - sync to fence before executing the IB |
113 | * |
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114 | * @ib: IB object to add fence to |
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115 | * @fence: fence to sync to |
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116 | * |
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117 | * Sync to the fence before executing the IB |
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118 | */ |
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119 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence) |
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120 | { |
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121 | struct radeon_fence *other; |
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122 | |||
123 | if (!fence) |
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124 | return; |
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125 | |||
126 | other = ib->sync_to[fence->ring]; |
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127 | ib->sync_to[fence->ring] = radeon_fence_later(fence, other); |
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128 | } |
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129 | |||
130 | /** |
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2997 | Serge | 131 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring |
132 | * |
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133 | * @rdev: radeon_device pointer |
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134 | * @ib: IB object to schedule |
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135 | * @const_ib: Const IB to schedule (SI only) |
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136 | * |
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137 | * Schedule an IB on the associated ring (all asics). |
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138 | * Returns 0 on success, error on failure. |
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139 | * |
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140 | * On SI, there are two parallel engines fed from the primary ring, |
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141 | * the CE (Constant Engine) and the DE (Drawing Engine). Since |
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142 | * resource descriptors have moved to memory, the CE allows you to |
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143 | * prime the caches while the DE is updating register state so that |
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144 | * the resource descriptors will be already in cache when the draw is |
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145 | * processed. To accomplish this, the userspace driver submits two |
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146 | * IBs, one for the CE and one for the DE. If there is a CE IB (called |
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147 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior |
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148 | * to SI there was just a DE IB. |
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149 | */ |
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150 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
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151 | struct radeon_ib *const_ib) |
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1117 | serge | 152 | { |
2997 | Serge | 153 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
154 | bool need_sync = false; |
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155 | int i, r = 0; |
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1117 | serge | 156 | |
2997 | Serge | 157 | if (!ib->length_dw || !ring->ready) { |
1117 | serge | 158 | /* TODO: Nothings in the ib we should report. */ |
2997 | Serge | 159 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
1117 | serge | 160 | return -EINVAL; |
161 | } |
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1179 | serge | 162 | |
163 | /* 64 dwords should be enough for fence too */ |
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2997 | Serge | 164 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
1117 | serge | 165 | if (r) { |
2997 | Serge | 166 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
1117 | serge | 167 | return r; |
168 | } |
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2997 | Serge | 169 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
170 | struct radeon_fence *fence = ib->sync_to[i]; |
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171 | if (radeon_fence_need_sync(fence, ib->ring)) { |
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172 | need_sync = true; |
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173 | radeon_semaphore_sync_rings(rdev, ib->semaphore, |
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174 | fence->ring, ib->ring); |
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175 | radeon_fence_note_sync(fence, ib->ring); |
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176 | } |
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177 | } |
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178 | /* immediately free semaphore when we don't need to sync */ |
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179 | if (!need_sync) { |
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180 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); |
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181 | } |
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182 | /* if we can't remember our last VM flush then flush now! */ |
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3764 | Serge | 183 | /* XXX figure out why we have to flush for every IB */ |
184 | if (ib->vm /*&& !ib->vm->last_flush*/) { |
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2997 | Serge | 185 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
186 | } |
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187 | if (const_ib) { |
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188 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); |
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189 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); |
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190 | } |
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191 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
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192 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
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193 | if (r) { |
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194 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
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195 | radeon_ring_unlock_undo(rdev, ring); |
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196 | return r; |
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197 | } |
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198 | if (const_ib) { |
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199 | const_ib->fence = radeon_fence_ref(ib->fence); |
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200 | } |
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201 | /* we just flushed the VM, remember that */ |
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202 | if (ib->vm && !ib->vm->last_flush) { |
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203 | ib->vm->last_flush = radeon_fence_ref(ib->fence); |
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204 | } |
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205 | radeon_ring_unlock_commit(rdev, ring); |
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1117 | serge | 206 | return 0; |
207 | } |
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208 | |||
2997 | Serge | 209 | /** |
210 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool |
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211 | * |
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212 | * @rdev: radeon_device pointer |
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213 | * |
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214 | * Initialize the suballocator to manage a pool of memory |
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215 | * for use as IBs (all asics). |
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216 | * Returns 0 on success, error on failure. |
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217 | */ |
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1117 | serge | 218 | int radeon_ib_pool_init(struct radeon_device *rdev) |
219 | { |
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2997 | Serge | 220 | int r; |
1117 | serge | 221 | |
2997 | Serge | 222 | if (rdev->ib_pool_ready) { |
1179 | serge | 223 | return 0; |
1117 | serge | 224 | } |
2997 | Serge | 225 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
226 | RADEON_IB_POOL_SIZE*64*1024, |
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227 | RADEON_GEM_DOMAIN_GTT); |
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1117 | serge | 228 | if (r) { |
229 | return r; |
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230 | } |
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2997 | Serge | 231 | |
232 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
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1117 | serge | 233 | if (r) { |
234 | return r; |
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235 | } |
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236 | |||
2997 | Serge | 237 | rdev->ib_pool_ready = true; |
238 | if (radeon_debugfs_sa_init(rdev)) { |
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239 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
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1117 | serge | 240 | } |
2997 | Serge | 241 | return 0; |
1117 | serge | 242 | } |
243 | |||
2997 | Serge | 244 | /** |
245 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool |
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246 | * |
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247 | * @rdev: radeon_device pointer |
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248 | * |
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249 | * Tear down the suballocator managing the pool of memory |
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250 | * for use as IBs (all asics). |
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251 | */ |
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1117 | serge | 252 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
253 | { |
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2997 | Serge | 254 | if (rdev->ib_pool_ready) { |
255 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
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256 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
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257 | rdev->ib_pool_ready = false; |
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258 | } |
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259 | } |
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260 | |||
261 | /** |
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262 | * radeon_ib_ring_tests - test IBs on the rings |
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263 | * |
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264 | * @rdev: radeon_device pointer |
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265 | * |
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266 | * Test an IB (Indirect Buffer) on each ring. |
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267 | * If the test fails, disable the ring. |
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268 | * Returns 0 on success, error if the primary GFX ring |
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269 | * IB test fails. |
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270 | */ |
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271 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
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272 | { |
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273 | unsigned i; |
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1404 | serge | 274 | int r; |
275 | |||
2997 | Serge | 276 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
277 | struct radeon_ring *ring = &rdev->ring[i]; |
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278 | |||
279 | if (!ring->ready) |
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280 | continue; |
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281 | |||
282 | r = radeon_ib_test(rdev, i, ring); |
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283 | if (r) { |
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284 | ring->ready = false; |
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285 | |||
286 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
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287 | /* oh, oh, that's really bad */ |
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288 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
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289 | rdev->accel_working = false; |
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290 | return r; |
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291 | |||
292 | } else { |
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293 | /* still not good, but we can live with it */ |
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294 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
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1117 | serge | 295 | } |
1404 | serge | 296 | } |
1117 | serge | 297 | } |
2997 | Serge | 298 | return 0; |
1117 | serge | 299 | } |
300 | |||
301 | /* |
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2997 | Serge | 302 | * Rings |
303 | * Most engines on the GPU are fed via ring buffers. Ring |
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304 | * buffers are areas of GPU accessible memory that the host |
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305 | * writes commands into and the GPU reads commands out of. |
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306 | * There is a rptr (read pointer) that determines where the |
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307 | * GPU is currently reading, and a wptr (write pointer) |
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308 | * which determines where the host has written. When the |
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309 | * pointers are equal, the ring is idle. When the host |
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310 | * writes commands to the ring buffer, it increments the |
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311 | * wptr. The GPU then starts fetching commands and executes |
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312 | * them until the pointers are equal again. |
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1117 | serge | 313 | */ |
2997 | Serge | 314 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
315 | |||
316 | /** |
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317 | * radeon_ring_write - write a value to the ring |
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318 | * |
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319 | * @ring: radeon_ring structure holding ring information |
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320 | * @v: dword (dw) value to write |
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321 | * |
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322 | * Write a value to the requested ring buffer (all asics). |
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323 | */ |
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324 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
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1117 | serge | 325 | { |
2997 | Serge | 326 | #if DRM_DEBUG_CODE |
327 | if (ring->count_dw <= 0) { |
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328 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
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329 | } |
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330 | #endif |
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331 | ring->ring[ring->wptr++] = v; |
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332 | ring->wptr &= ring->ptr_mask; |
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333 | ring->count_dw--; |
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334 | ring->ring_free_dw--; |
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335 | } |
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336 | |||
337 | /** |
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338 | * radeon_ring_supports_scratch_reg - check if the ring supports |
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339 | * writing to scratch registers |
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340 | * |
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341 | * @rdev: radeon_device pointer |
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342 | * @ring: radeon_ring structure holding ring information |
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343 | * |
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344 | * Check if a specific ring supports writing to scratch registers (all asics). |
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345 | * Returns true if the ring supports writing to scratch regs, false if not. |
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346 | */ |
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347 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
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348 | struct radeon_ring *ring) |
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349 | { |
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350 | switch (ring->idx) { |
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351 | case RADEON_RING_TYPE_GFX_INDEX: |
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352 | case CAYMAN_RING_TYPE_CP1_INDEX: |
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353 | case CAYMAN_RING_TYPE_CP2_INDEX: |
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354 | return true; |
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355 | default: |
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356 | return false; |
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357 | } |
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358 | } |
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359 | |||
360 | /** |
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361 | * radeon_ring_free_size - update the free size |
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362 | * |
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363 | * @rdev: radeon_device pointer |
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364 | * @ring: radeon_ring structure holding ring information |
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365 | * |
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366 | * Update the free dw slots in the ring buffer (all asics). |
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367 | */ |
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368 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
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369 | { |
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370 | u32 rptr; |
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371 | |||
3764 | Serge | 372 | if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX]) |
2997 | Serge | 373 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
1179 | serge | 374 | else |
2997 | Serge | 375 | rptr = RREG32(ring->rptr_reg); |
376 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
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1117 | serge | 377 | /* This works because ring_size is a power of 2 */ |
2997 | Serge | 378 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
379 | ring->ring_free_dw -= ring->wptr; |
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380 | ring->ring_free_dw &= ring->ptr_mask; |
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381 | if (!ring->ring_free_dw) { |
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382 | ring->ring_free_dw = ring->ring_size / 4; |
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1117 | serge | 383 | } |
384 | } |
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385 | |||
2997 | Serge | 386 | /** |
387 | * radeon_ring_alloc - allocate space on the ring buffer |
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388 | * |
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389 | * @rdev: radeon_device pointer |
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390 | * @ring: radeon_ring structure holding ring information |
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391 | * @ndw: number of dwords to allocate in the ring buffer |
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392 | * |
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393 | * Allocate @ndw dwords in the ring buffer (all asics). |
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394 | * Returns 0 on success, error on failure. |
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395 | */ |
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396 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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1117 | serge | 397 | { |
398 | int r; |
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399 | |||
3764 | Serge | 400 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
401 | if (ndw > (ring->ring_size / 4)) |
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402 | return -ENOMEM; |
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1117 | serge | 403 | /* Align requested size with padding so unlock_commit can |
404 | * pad safely */ |
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3764 | Serge | 405 | radeon_ring_free_size(rdev, ring); |
406 | if (ring->ring_free_dw == (ring->ring_size / 4)) { |
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407 | /* This is an empty ring update lockup info to avoid |
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408 | * false positive. |
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409 | */ |
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410 | radeon_ring_lockup_update(ring); |
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411 | } |
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2997 | Serge | 412 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
413 | while (ndw > (ring->ring_free_dw - 1)) { |
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414 | radeon_ring_free_size(rdev, ring); |
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415 | if (ndw < ring->ring_free_dw) { |
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1117 | serge | 416 | break; |
417 | } |
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3192 | Serge | 418 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
419 | if (r) |
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420 | return r; |
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1117 | serge | 421 | } |
2997 | Serge | 422 | ring->count_dw = ndw; |
423 | ring->wptr_old = ring->wptr; |
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1117 | serge | 424 | return 0; |
425 | } |
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426 | |||
2997 | Serge | 427 | /** |
428 | * radeon_ring_lock - lock the ring and allocate space on it |
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429 | * |
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430 | * @rdev: radeon_device pointer |
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431 | * @ring: radeon_ring structure holding ring information |
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432 | * @ndw: number of dwords to allocate in the ring buffer |
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433 | * |
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434 | * Lock the ring and allocate @ndw dwords in the ring buffer |
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435 | * (all asics). |
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436 | * Returns 0 on success, error on failure. |
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437 | */ |
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438 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
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1117 | serge | 439 | { |
1963 | serge | 440 | int r; |
441 | |||
2997 | Serge | 442 | mutex_lock(&rdev->ring_lock); |
443 | r = radeon_ring_alloc(rdev, ring, ndw); |
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1963 | serge | 444 | if (r) { |
2997 | Serge | 445 | mutex_unlock(&rdev->ring_lock); |
1963 | serge | 446 | return r; |
447 | } |
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448 | return 0; |
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449 | } |
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450 | |||
2997 | Serge | 451 | /** |
452 | * radeon_ring_commit - tell the GPU to execute the new |
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453 | * commands on the ring buffer |
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454 | * |
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455 | * @rdev: radeon_device pointer |
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456 | * @ring: radeon_ring structure holding ring information |
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457 | * |
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458 | * Update the wptr (write pointer) to tell the GPU to |
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459 | * execute new commands on the ring buffer (all asics). |
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460 | */ |
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461 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
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1963 | serge | 462 | { |
1117 | serge | 463 | /* We pad to match fetch size */ |
2997 | Serge | 464 | while (ring->wptr & ring->align_mask) { |
465 | radeon_ring_write(ring, ring->nop); |
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1117 | serge | 466 | } |
467 | DRM_MEMORYBARRIER(); |
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2997 | Serge | 468 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
469 | (void)RREG32(ring->wptr_reg); |
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1963 | serge | 470 | } |
471 | |||
2997 | Serge | 472 | /** |
473 | * radeon_ring_unlock_commit - tell the GPU to execute the new |
||
474 | * commands on the ring buffer and unlock it |
||
475 | * |
||
476 | * @rdev: radeon_device pointer |
||
477 | * @ring: radeon_ring structure holding ring information |
||
478 | * |
||
479 | * Call radeon_ring_commit() then unlock the ring (all asics). |
||
480 | */ |
||
481 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
||
1963 | serge | 482 | { |
2997 | Serge | 483 | radeon_ring_commit(rdev, ring); |
484 | mutex_unlock(&rdev->ring_lock); |
||
1117 | serge | 485 | } |
486 | |||
2997 | Serge | 487 | /** |
488 | * radeon_ring_undo - reset the wptr |
||
489 | * |
||
490 | * @ring: radeon_ring structure holding ring information |
||
491 | * |
||
3192 | Serge | 492 | * Reset the driver's copy of the wptr (all asics). |
2997 | Serge | 493 | */ |
494 | void radeon_ring_undo(struct radeon_ring *ring) |
||
1117 | serge | 495 | { |
2997 | Serge | 496 | ring->wptr = ring->wptr_old; |
1117 | serge | 497 | } |
498 | |||
2997 | Serge | 499 | /** |
500 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring |
||
501 | * |
||
502 | * @ring: radeon_ring structure holding ring information |
||
503 | * |
||
504 | * Call radeon_ring_undo() then unlock the ring (all asics). |
||
505 | */ |
||
506 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
||
1117 | serge | 507 | { |
2997 | Serge | 508 | radeon_ring_undo(ring); |
509 | mutex_unlock(&rdev->ring_lock); |
||
510 | } |
||
511 | |||
512 | /** |
||
513 | * radeon_ring_force_activity - add some nop packets to the ring |
||
514 | * |
||
515 | * @rdev: radeon_device pointer |
||
516 | * @ring: radeon_ring structure holding ring information |
||
517 | * |
||
518 | * Add some nop packets to the ring to force activity (all asics). |
||
519 | * Used for lockup detection to see if the rptr is advancing. |
||
520 | */ |
||
521 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
||
522 | { |
||
1117 | serge | 523 | int r; |
524 | |||
2997 | Serge | 525 | radeon_ring_free_size(rdev, ring); |
526 | if (ring->rptr == ring->wptr) { |
||
527 | r = radeon_ring_alloc(rdev, ring, 1); |
||
528 | if (!r) { |
||
529 | radeon_ring_write(ring, ring->nop); |
||
530 | radeon_ring_commit(rdev, ring); |
||
531 | } |
||
532 | } |
||
533 | } |
||
534 | |||
535 | /** |
||
3192 | Serge | 536 | * radeon_ring_lockup_update - update lockup variables |
2997 | Serge | 537 | * |
538 | * @ring: radeon_ring structure holding ring information |
||
539 | * |
||
540 | * Update the last rptr value and timestamp (all asics). |
||
541 | */ |
||
542 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
||
543 | { |
||
544 | ring->last_rptr = ring->rptr; |
||
545 | ring->last_activity = GetTimerTicks(); |
||
546 | } |
||
547 | |||
548 | /** |
||
549 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
||
550 | * @rdev: radeon device structure |
||
551 | * @ring: radeon_ring structure holding ring information |
||
552 | * |
||
553 | * We don't need to initialize the lockup tracking information as we will either |
||
554 | * have CP rptr to a different value of jiffies wrap around which will force |
||
555 | * initialization of the lockup tracking informations. |
||
556 | * |
||
557 | * A possible false positivie is if we get call after while and last_cp_rptr == |
||
558 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
||
559 | * if the elapsed time since last call is bigger than 2 second than we return |
||
560 | * false and update the tracking information. Due to this the caller must call |
||
561 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
||
562 | * the fencing code should be cautious about that. |
||
563 | * |
||
564 | * Caller should write to the ring to force CP to do something so we don't get |
||
565 | * false positive when CP is just gived nothing to do. |
||
566 | * |
||
567 | **/ |
||
568 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
||
569 | { |
||
570 | unsigned long cjiffies, elapsed; |
||
571 | uint32_t rptr; |
||
572 | |||
573 | cjiffies = GetTimerTicks(); |
||
574 | if (!time_after(cjiffies, ring->last_activity)) { |
||
575 | /* likely a wrap around */ |
||
576 | radeon_ring_lockup_update(ring); |
||
577 | return false; |
||
578 | } |
||
579 | rptr = RREG32(ring->rptr_reg); |
||
580 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
||
581 | if (ring->rptr != ring->last_rptr) { |
||
582 | /* CP is still working no lockup */ |
||
583 | radeon_ring_lockup_update(ring); |
||
584 | return false; |
||
585 | } |
||
586 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
||
587 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
||
588 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
||
589 | return true; |
||
590 | } |
||
591 | /* give a chance to the GPU ... */ |
||
592 | return false; |
||
593 | } |
||
594 | |||
595 | /** |
||
596 | * radeon_ring_backup - Back up the content of a ring |
||
597 | * |
||
598 | * @rdev: radeon_device pointer |
||
599 | * @ring: the ring we want to back up |
||
600 | * |
||
601 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
||
602 | */ |
||
603 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
||
604 | uint32_t **data) |
||
605 | { |
||
606 | unsigned size, ptr, i; |
||
607 | |||
608 | /* just in case lock the ring */ |
||
609 | mutex_lock(&rdev->ring_lock); |
||
610 | *data = NULL; |
||
611 | |||
612 | if (ring->ring_obj == NULL) { |
||
613 | mutex_unlock(&rdev->ring_lock); |
||
614 | return 0; |
||
615 | } |
||
616 | |||
617 | /* it doesn't make sense to save anything if all fences are signaled */ |
||
618 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
||
619 | mutex_unlock(&rdev->ring_lock); |
||
620 | return 0; |
||
621 | } |
||
622 | |||
623 | /* calculate the number of dw on the ring */ |
||
624 | if (ring->rptr_save_reg) |
||
625 | ptr = RREG32(ring->rptr_save_reg); |
||
626 | else if (rdev->wb.enabled) |
||
627 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); |
||
628 | else { |
||
629 | /* no way to read back the next rptr */ |
||
630 | mutex_unlock(&rdev->ring_lock); |
||
631 | return 0; |
||
632 | } |
||
633 | |||
634 | size = ring->wptr + (ring->ring_size / 4); |
||
635 | size -= ptr; |
||
636 | size &= ring->ptr_mask; |
||
637 | if (size == 0) { |
||
638 | mutex_unlock(&rdev->ring_lock); |
||
639 | return 0; |
||
640 | } |
||
641 | |||
642 | /* and then save the content of the ring */ |
||
643 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
||
644 | if (!*data) { |
||
645 | mutex_unlock(&rdev->ring_lock); |
||
646 | return 0; |
||
647 | } |
||
648 | for (i = 0; i < size; ++i) { |
||
649 | (*data)[i] = ring->ring[ptr++]; |
||
650 | ptr &= ring->ptr_mask; |
||
651 | } |
||
652 | |||
653 | mutex_unlock(&rdev->ring_lock); |
||
654 | return size; |
||
655 | } |
||
656 | |||
657 | /** |
||
658 | * radeon_ring_restore - append saved commands to the ring again |
||
659 | * |
||
660 | * @rdev: radeon_device pointer |
||
661 | * @ring: ring to append commands to |
||
662 | * @size: number of dwords we want to write |
||
663 | * @data: saved commands |
||
664 | * |
||
665 | * Allocates space on the ring and restore the previously saved commands. |
||
666 | */ |
||
667 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
||
668 | unsigned size, uint32_t *data) |
||
669 | { |
||
670 | int i, r; |
||
671 | |||
672 | if (!size || !data) |
||
673 | return 0; |
||
674 | |||
675 | /* restore the saved ring content */ |
||
676 | r = radeon_ring_lock(rdev, ring, size); |
||
677 | if (r) |
||
678 | return r; |
||
679 | |||
680 | for (i = 0; i < size; ++i) { |
||
681 | radeon_ring_write(ring, data[i]); |
||
682 | } |
||
683 | |||
684 | radeon_ring_unlock_commit(rdev, ring); |
||
685 | kfree(data); |
||
686 | return 0; |
||
687 | } |
||
688 | |||
689 | /** |
||
690 | * radeon_ring_init - init driver ring struct. |
||
691 | * |
||
692 | * @rdev: radeon_device pointer |
||
693 | * @ring: radeon_ring structure holding ring information |
||
694 | * @ring_size: size of the ring |
||
695 | * @rptr_offs: offset of the rptr writeback location in the WB buffer |
||
696 | * @rptr_reg: MMIO offset of the rptr register |
||
697 | * @wptr_reg: MMIO offset of the wptr register |
||
698 | * @ptr_reg_shift: bit offset of the rptr/wptr values |
||
699 | * @ptr_reg_mask: bit mask of the rptr/wptr values |
||
700 | * @nop: nop packet for this ring |
||
701 | * |
||
702 | * Initialize the driver information for the selected ring (all asics). |
||
703 | * Returns 0 on success, error on failure. |
||
704 | */ |
||
705 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
||
706 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
||
707 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
||
708 | { |
||
709 | int r; |
||
710 | |||
711 | ring->ring_size = ring_size; |
||
712 | ring->rptr_offs = rptr_offs; |
||
713 | ring->rptr_reg = rptr_reg; |
||
714 | ring->wptr_reg = wptr_reg; |
||
715 | ring->ptr_reg_shift = ptr_reg_shift; |
||
716 | ring->ptr_reg_mask = ptr_reg_mask; |
||
717 | ring->nop = nop; |
||
1120 | serge | 718 | /* Allocate ring buffer */ |
2997 | Serge | 719 | if (ring->ring_obj == NULL) { |
720 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
||
1117 | serge | 721 | RADEON_GEM_DOMAIN_GTT, |
2997 | Serge | 722 | NULL, &ring->ring_obj); |
1117 | serge | 723 | if (r) { |
1404 | serge | 724 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
1117 | serge | 725 | return r; |
726 | } |
||
2997 | Serge | 727 | r = radeon_bo_reserve(ring->ring_obj, false); |
1404 | serge | 728 | if (unlikely(r != 0)) |
729 | return r; |
||
2997 | Serge | 730 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
731 | &ring->gpu_addr); |
||
1117 | serge | 732 | if (r) { |
2997 | Serge | 733 | radeon_bo_unreserve(ring->ring_obj); |
1404 | serge | 734 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
1117 | serge | 735 | return r; |
736 | } |
||
2997 | Serge | 737 | r = radeon_bo_kmap(ring->ring_obj, |
738 | (void **)&ring->ring); |
||
739 | radeon_bo_unreserve(ring->ring_obj); |
||
1117 | serge | 740 | if (r) { |
1404 | serge | 741 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
1117 | serge | 742 | return r; |
743 | } |
||
744 | } |
||
2997 | Serge | 745 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
746 | ring->ring_free_dw = ring->ring_size / 4; |
||
747 | if (rdev->wb.enabled) { |
||
748 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); |
||
749 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; |
||
750 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; |
||
751 | } |
||
752 | if (radeon_debugfs_ring_init(rdev, ring)) { |
||
753 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
||
754 | } |
||
755 | radeon_ring_lockup_update(ring); |
||
1117 | serge | 756 | return 0; |
757 | } |
||
758 | |||
2997 | Serge | 759 | /** |
760 | * radeon_ring_fini - tear down the driver ring struct. |
||
761 | * |
||
762 | * @rdev: radeon_device pointer |
||
763 | * @ring: radeon_ring structure holding ring information |
||
764 | * |
||
765 | * Tear down the driver information for the selected ring (all asics). |
||
766 | */ |
||
767 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
||
1117 | serge | 768 | { |
1404 | serge | 769 | int r; |
1963 | serge | 770 | struct radeon_bo *ring_obj; |
1404 | serge | 771 | |
2997 | Serge | 772 | mutex_lock(&rdev->ring_lock); |
773 | ring_obj = ring->ring_obj; |
||
774 | ring->ready = false; |
||
775 | ring->ring = NULL; |
||
776 | ring->ring_obj = NULL; |
||
777 | mutex_unlock(&rdev->ring_lock); |
||
1963 | serge | 778 | |
779 | if (ring_obj) { |
||
780 | r = radeon_bo_reserve(ring_obj, false); |
||
1404 | serge | 781 | if (likely(r == 0)) { |
1963 | serge | 782 | radeon_bo_kunmap(ring_obj); |
783 | radeon_bo_unpin(ring_obj); |
||
784 | radeon_bo_unreserve(ring_obj); |
||
1404 | serge | 785 | } |
1963 | serge | 786 | radeon_bo_unref(&ring_obj); |
1117 | serge | 787 | } |
788 | } |
||
789 | |||
790 | /* |
||
791 | * Debugfs info |
||
792 | */ |
||
793 | #if defined(CONFIG_DEBUG_FS) |
||
2997 | Serge | 794 | |
795 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
||
1117 | serge | 796 | { |
797 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2997 | Serge | 798 | struct drm_device *dev = node->minor->dev; |
799 | struct radeon_device *rdev = dev->dev_private; |
||
800 | int ridx = *(int*)node->info_ent->data; |
||
801 | struct radeon_ring *ring = &rdev->ring[ridx]; |
||
802 | unsigned count, i, j; |
||
3192 | Serge | 803 | u32 tmp; |
1117 | serge | 804 | |
2997 | Serge | 805 | radeon_ring_free_size(rdev, ring); |
806 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
||
3192 | Serge | 807 | tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; |
808 | seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); |
||
809 | tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; |
||
810 | seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); |
||
2997 | Serge | 811 | if (ring->rptr_save_reg) { |
812 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, |
||
813 | RREG32(ring->rptr_save_reg)); |
||
1117 | serge | 814 | } |
3192 | Serge | 815 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); |
816 | seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); |
||
817 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); |
||
818 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); |
||
2997 | Serge | 819 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
820 | seq_printf(m, "%u dwords in ring\n", count); |
||
3192 | Serge | 821 | /* print 8 dw before current rptr as often it's the last executed |
822 | * packet that is the root issue |
||
823 | */ |
||
824 | i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
||
825 | for (j = 0; j <= (count + 32); j++) { |
||
826 | seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); |
||
2997 | Serge | 827 | i = (i + 1) & ring->ptr_mask; |
1117 | serge | 828 | } |
829 | return 0; |
||
830 | } |
||
831 | |||
3764 | Serge | 832 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
833 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
||
834 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
||
835 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; |
||
836 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; |
||
837 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; |
||
2997 | Serge | 838 | |
839 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
||
3764 | Serge | 840 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
841 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, |
||
842 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, |
||
843 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, |
||
844 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, |
||
845 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, |
||
2997 | Serge | 846 | }; |
847 | |||
848 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
||
1963 | serge | 849 | { |
850 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2997 | Serge | 851 | struct drm_device *dev = node->minor->dev; |
852 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | serge | 853 | |
2997 | Serge | 854 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
855 | |||
1963 | serge | 856 | return 0; |
2997 | Serge | 857 | |
1963 | serge | 858 | } |
859 | |||
2997 | Serge | 860 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
861 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
||
862 | }; |
||
1963 | serge | 863 | |
1117 | serge | 864 | #endif |
865 | |||
2997 | Serge | 866 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
1117 | serge | 867 | { |
868 | #if defined(CONFIG_DEBUG_FS) |
||
869 | unsigned i; |
||
2997 | Serge | 870 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
871 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
||
872 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
||
873 | unsigned r; |
||
1117 | serge | 874 | |
2997 | Serge | 875 | if (&rdev->ring[ridx] != ring) |
876 | continue; |
||
877 | |||
878 | r = radeon_debugfs_add_files(rdev, info, 1); |
||
1430 | serge | 879 | if (r) |
880 | return r; |
||
1117 | serge | 881 | } |
2997 | Serge | 882 | #endif |
883 | return 0; |
||
884 | } |
||
885 | |||
886 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
||
887 | { |
||
888 | #if defined(CONFIG_DEBUG_FS) |
||
889 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
||
1117 | serge | 890 | #else |
891 | return 0; |
||
892 | #endif |
||
893 | }>=>>>><>>=>>>> |