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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
1117 | serge | 30 | #include "radeon_drm.h" |
31 | #include "radeon_reg.h" |
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32 | #include "radeon.h" |
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33 | #include "atom.h" |
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34 | |||
35 | int radeon_debugfs_ib_init(struct radeon_device *rdev); |
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36 | |||
37 | /* |
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38 | * IB. |
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39 | */ |
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1120 | serge | 40 | |
41 | #if 0 |
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42 | |||
1117 | serge | 43 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) |
44 | { |
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45 | struct radeon_fence *fence; |
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46 | struct radeon_ib *nib; |
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47 | unsigned long i; |
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48 | int r = 0; |
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49 | |||
50 | *ib = NULL; |
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51 | r = radeon_fence_create(rdev, &fence); |
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52 | if (r) { |
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53 | DRM_ERROR("failed to create fence for new IB\n"); |
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54 | return r; |
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55 | } |
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56 | mutex_lock(&rdev->ib_pool.mutex); |
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57 | i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
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58 | if (i < RADEON_IB_POOL_SIZE) { |
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59 | set_bit(i, rdev->ib_pool.alloc_bm); |
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60 | rdev->ib_pool.ibs[i].length_dw = 0; |
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61 | *ib = &rdev->ib_pool.ibs[i]; |
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1179 | serge | 62 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 63 | goto out; |
64 | } |
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65 | if (list_empty(&rdev->ib_pool.scheduled_ibs)) { |
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66 | /* we go do nothings here */ |
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1179 | serge | 67 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 68 | DRM_ERROR("all IB allocated none scheduled.\n"); |
69 | r = -EINVAL; |
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70 | goto out; |
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71 | } |
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72 | /* get the first ib on the scheduled list */ |
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73 | nib = list_entry(rdev->ib_pool.scheduled_ibs.next, |
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74 | struct radeon_ib, list); |
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75 | if (nib->fence == NULL) { |
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76 | /* we go do nothings here */ |
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1179 | serge | 77 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 78 | DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); |
79 | r = -EINVAL; |
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80 | goto out; |
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81 | } |
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1179 | serge | 82 | mutex_unlock(&rdev->ib_pool.mutex); |
83 | |||
1117 | serge | 84 | r = radeon_fence_wait(nib->fence, false); |
85 | if (r) { |
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86 | DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, |
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87 | (unsigned long)nib->gpu_addr, nib->length_dw); |
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88 | DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); |
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89 | goto out; |
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90 | } |
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91 | radeon_fence_unref(&nib->fence); |
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1179 | serge | 92 | |
1117 | serge | 93 | nib->length_dw = 0; |
1179 | serge | 94 | |
95 | /* scheduled list is accessed here */ |
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96 | mutex_lock(&rdev->ib_pool.mutex); |
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1117 | serge | 97 | list_del(&nib->list); |
98 | INIT_LIST_HEAD(&nib->list); |
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1179 | serge | 99 | mutex_unlock(&rdev->ib_pool.mutex); |
100 | |||
1117 | serge | 101 | *ib = nib; |
102 | out: |
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103 | if (r) { |
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104 | radeon_fence_unref(&fence); |
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105 | } else { |
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106 | (*ib)->fence = fence; |
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107 | } |
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108 | return r; |
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109 | } |
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110 | |||
111 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) |
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112 | { |
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113 | struct radeon_ib *tmp = *ib; |
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114 | |||
115 | *ib = NULL; |
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116 | if (tmp == NULL) { |
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117 | return; |
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118 | } |
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119 | mutex_lock(&rdev->ib_pool.mutex); |
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120 | if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { |
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121 | /* IB is scheduled & not signaled don't do anythings */ |
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122 | mutex_unlock(&rdev->ib_pool.mutex); |
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123 | return; |
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124 | } |
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125 | list_del(&tmp->list); |
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126 | INIT_LIST_HEAD(&tmp->list); |
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1179 | serge | 127 | if (tmp->fence) |
1117 | serge | 128 | radeon_fence_unref(&tmp->fence); |
1179 | serge | 129 | |
1117 | serge | 130 | tmp->length_dw = 0; |
131 | clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); |
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132 | mutex_unlock(&rdev->ib_pool.mutex); |
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133 | } |
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134 | |||
135 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
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136 | { |
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137 | int r = 0; |
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138 | |||
139 | if (!ib->length_dw || !rdev->cp.ready) { |
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140 | /* TODO: Nothings in the ib we should report. */ |
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141 | DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); |
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142 | return -EINVAL; |
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143 | } |
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1179 | serge | 144 | |
145 | /* 64 dwords should be enough for fence too */ |
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1117 | serge | 146 | r = radeon_ring_lock(rdev, 64); |
147 | if (r) { |
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148 | DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); |
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149 | return r; |
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150 | } |
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1179 | serge | 151 | radeon_ring_ib_execute(rdev, ib); |
1117 | serge | 152 | radeon_fence_emit(rdev, ib->fence); |
1179 | serge | 153 | mutex_lock(&rdev->ib_pool.mutex); |
1117 | serge | 154 | list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); |
155 | mutex_unlock(&rdev->ib_pool.mutex); |
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1179 | serge | 156 | radeon_ring_unlock_commit(rdev); |
1117 | serge | 157 | return 0; |
158 | } |
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1120 | serge | 159 | #endif |
1117 | serge | 160 | |
161 | int radeon_ib_pool_init(struct radeon_device *rdev) |
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162 | { |
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163 | void *ptr; |
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164 | uint64_t gpu_addr; |
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165 | int i; |
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166 | int r = 0; |
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167 | |||
1179 | serge | 168 | if (rdev->ib_pool.robj) |
169 | return 0; |
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1117 | serge | 170 | /* Allocate 1M object buffer */ |
171 | INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); |
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1404 | serge | 172 | r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, |
1117 | serge | 173 | true, RADEON_GEM_DOMAIN_GTT, |
1404 | serge | 174 | &rdev->ib_pool.robj); |
1117 | serge | 175 | if (r) { |
176 | DRM_ERROR("radeon: failed to ib pool (%d).\n", r); |
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177 | return r; |
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178 | } |
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1404 | serge | 179 | r = radeon_bo_reserve(rdev->ib_pool.robj, false); |
180 | if (unlikely(r != 0)) |
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181 | return r; |
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182 | r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); |
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1117 | serge | 183 | if (r) { |
1404 | serge | 184 | radeon_bo_unreserve(rdev->ib_pool.robj); |
1117 | serge | 185 | DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); |
186 | return r; |
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187 | } |
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1404 | serge | 188 | r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr); |
189 | radeon_bo_unreserve(rdev->ib_pool.robj); |
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1117 | serge | 190 | if (r) { |
191 | DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); |
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192 | return r; |
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193 | } |
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194 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
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195 | unsigned offset; |
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196 | |||
197 | offset = i * 64 * 1024; |
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198 | rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; |
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199 | rdev->ib_pool.ibs[i].ptr = ptr + offset; |
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200 | rdev->ib_pool.ibs[i].idx = i; |
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201 | rdev->ib_pool.ibs[i].length_dw = 0; |
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202 | INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); |
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203 | } |
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204 | bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
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205 | rdev->ib_pool.ready = true; |
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206 | DRM_INFO("radeon: ib pool ready.\n"); |
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1129 | serge | 207 | if (radeon_debugfs_ib_init(rdev)) { |
208 | DRM_ERROR("Failed to register debugfs file for IB !\n"); |
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209 | } |
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1117 | serge | 210 | return r; |
211 | } |
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212 | |||
213 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
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214 | { |
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1404 | serge | 215 | int r; |
216 | |||
1117 | serge | 217 | if (!rdev->ib_pool.ready) { |
218 | return; |
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219 | } |
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1179 | serge | 220 | mutex_lock(&rdev->ib_pool.mutex); |
1117 | serge | 221 | bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
222 | if (rdev->ib_pool.robj) { |
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1404 | serge | 223 | r = radeon_bo_reserve(rdev->ib_pool.robj, false); |
224 | if (likely(r == 0)) { |
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225 | radeon_bo_kunmap(rdev->ib_pool.robj); |
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226 | radeon_bo_unpin(rdev->ib_pool.robj); |
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227 | radeon_bo_unreserve(rdev->ib_pool.robj); |
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228 | } |
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229 | radeon_bo_unref(&rdev->ib_pool.robj); |
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1117 | serge | 230 | rdev->ib_pool.robj = NULL; |
231 | } |
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1179 | serge | 232 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 233 | } |
234 | |||
1120 | serge | 235 | |
1117 | serge | 236 | /* |
237 | * Ring. |
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238 | */ |
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239 | void radeon_ring_free_size(struct radeon_device *rdev) |
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240 | { |
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1179 | serge | 241 | if (rdev->family >= CHIP_R600) |
242 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); |
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243 | else |
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1117 | serge | 244 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
245 | /* This works because ring_size is a power of 2 */ |
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246 | rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); |
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247 | rdev->cp.ring_free_dw -= rdev->cp.wptr; |
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248 | rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; |
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249 | if (!rdev->cp.ring_free_dw) { |
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250 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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251 | } |
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252 | } |
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253 | |||
254 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) |
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255 | { |
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256 | int r; |
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257 | |||
258 | /* Align requested size with padding so unlock_commit can |
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259 | * pad safely */ |
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260 | ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; |
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1179 | serge | 261 | mutex_lock(&rdev->cp.mutex); |
1117 | serge | 262 | while (ndw > (rdev->cp.ring_free_dw - 1)) { |
263 | radeon_ring_free_size(rdev); |
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264 | if (ndw < rdev->cp.ring_free_dw) { |
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265 | break; |
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266 | } |
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267 | // r = radeon_fence_wait_next(rdev); |
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268 | // if (r) { |
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269 | // mutex_unlock(&rdev->cp.mutex); |
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270 | // return r; |
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271 | // } |
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272 | } |
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273 | rdev->cp.count_dw = ndw; |
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274 | rdev->cp.wptr_old = rdev->cp.wptr; |
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275 | return 0; |
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276 | } |
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277 | |||
278 | void radeon_ring_unlock_commit(struct radeon_device *rdev) |
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279 | { |
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280 | unsigned count_dw_pad; |
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281 | unsigned i; |
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282 | |||
283 | /* We pad to match fetch size */ |
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284 | count_dw_pad = (rdev->cp.align_mask + 1) - |
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285 | (rdev->cp.wptr & rdev->cp.align_mask); |
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286 | for (i = 0; i < count_dw_pad; i++) { |
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1179 | serge | 287 | radeon_ring_write(rdev, 2 << 30); |
1117 | serge | 288 | } |
289 | DRM_MEMORYBARRIER(); |
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1179 | serge | 290 | radeon_cp_commit(rdev); |
291 | mutex_unlock(&rdev->cp.mutex); |
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1117 | serge | 292 | } |
293 | |||
294 | void radeon_ring_unlock_undo(struct radeon_device *rdev) |
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295 | { |
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296 | rdev->cp.wptr = rdev->cp.wptr_old; |
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1179 | serge | 297 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 298 | } |
299 | |||
300 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) |
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301 | { |
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302 | int r; |
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303 | |||
1179 | serge | 304 | ENTER(); |
1117 | serge | 305 | |
306 | rdev->cp.ring_size = ring_size; |
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1120 | serge | 307 | /* Allocate ring buffer */ |
1117 | serge | 308 | if (rdev->cp.ring_obj == NULL) { |
1404 | serge | 309 | r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true, |
1117 | serge | 310 | RADEON_GEM_DOMAIN_GTT, |
311 | &rdev->cp.ring_obj); |
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312 | if (r) { |
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1404 | serge | 313 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
1117 | serge | 314 | return r; |
315 | } |
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1404 | serge | 316 | r = radeon_bo_reserve(rdev->cp.ring_obj, false); |
317 | if (unlikely(r != 0)) |
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318 | return r; |
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319 | r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT, |
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1117 | serge | 320 | &rdev->cp.gpu_addr); |
321 | if (r) { |
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1404 | serge | 322 | radeon_bo_unreserve(rdev->cp.ring_obj); |
323 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
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1117 | serge | 324 | return r; |
325 | } |
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1404 | serge | 326 | r = radeon_bo_kmap(rdev->cp.ring_obj, |
1117 | serge | 327 | (void **)&rdev->cp.ring); |
1404 | serge | 328 | radeon_bo_unreserve(rdev->cp.ring_obj); |
1117 | serge | 329 | if (r) { |
1404 | serge | 330 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
1117 | serge | 331 | return r; |
332 | } |
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333 | } |
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334 | rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; |
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335 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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1119 | serge | 336 | |
1179 | serge | 337 | LEAVE(); |
1119 | serge | 338 | |
1117 | serge | 339 | return 0; |
340 | } |
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341 | |||
342 | void radeon_ring_fini(struct radeon_device *rdev) |
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343 | { |
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1404 | serge | 344 | int r; |
345 | |||
1179 | serge | 346 | mutex_lock(&rdev->cp.mutex); |
1117 | serge | 347 | if (rdev->cp.ring_obj) { |
1404 | serge | 348 | r = radeon_bo_reserve(rdev->cp.ring_obj, false); |
349 | if (likely(r == 0)) { |
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350 | radeon_bo_kunmap(rdev->cp.ring_obj); |
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351 | radeon_bo_unpin(rdev->cp.ring_obj); |
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352 | radeon_bo_unreserve(rdev->cp.ring_obj); |
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353 | } |
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354 | radeon_bo_unref(&rdev->cp.ring_obj); |
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1117 | serge | 355 | rdev->cp.ring = NULL; |
356 | rdev->cp.ring_obj = NULL; |
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357 | } |
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1179 | serge | 358 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 359 | } |
360 | |||
361 | |||
362 | /* |
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363 | * Debugfs info |
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364 | */ |
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365 | #if defined(CONFIG_DEBUG_FS) |
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366 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
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367 | { |
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368 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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369 | struct radeon_ib *ib = node->info_ent->data; |
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370 | unsigned i; |
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371 | |||
372 | if (ib == NULL) { |
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373 | return 0; |
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374 | } |
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375 | seq_printf(m, "IB %04lu\n", ib->idx); |
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376 | seq_printf(m, "IB fence %p\n", ib->fence); |
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377 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
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378 | for (i = 0; i < ib->length_dw; i++) { |
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379 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
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380 | } |
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381 | return 0; |
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382 | } |
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383 | |||
384 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; |
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385 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; |
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386 | #endif |
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387 | |||
388 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
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389 | { |
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390 | #if defined(CONFIG_DEBUG_FS) |
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391 | unsigned i; |
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392 | |||
393 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
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394 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); |
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395 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
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396 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; |
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397 | radeon_debugfs_ib_list[i].driver_features = 0; |
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398 | radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; |
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399 | } |
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400 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, |
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401 | RADEON_IB_POOL_SIZE); |
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402 | #else |
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403 | return 0; |
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404 | #endif |
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405 | }>>><>>>>> |