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Rev | Author | Line No. | Line |
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1404 | serge | 1 | |
2 | #include |
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3 | #include "radeon_drm.h" |
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4 | #include "radeon.h" |
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5 | |||
6 | |||
7 | |||
8 | static struct drm_mm mm_vram; |
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9 | |||
10 | |||
1986 | serge | 11 | |
12 | * Initialize an already allocate GEM object of the specified size with |
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13 | * shmfs backing store. |
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14 | */ |
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15 | int drm_gem_object_init(struct drm_device *dev, |
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16 | struct drm_gem_object *obj, size_t size) |
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17 | { |
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18 | BUG_ON((size & (PAGE_SIZE - 1)) != 0); |
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19 | |||
20 | |||
21 | obj->filp = NULL; |
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22 | |||
23 | |||
24 | obj->size = size; |
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25 | |||
26 | |||
27 | } |
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28 | |||
29 | |||
30 | |||
1404 | serge | 31 | struct drm_mm_node **node) |
32 | { |
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33 | struct drm_mm_node *vm_node; |
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34 | int r; |
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35 | |||
36 | |||
37 | |||
38 | |||
39 | |||
40 | |||
41 | return r; |
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42 | |||
43 | |||
44 | |||
45 | |||
46 | r = -ENOMEM; |
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47 | return r; |
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48 | } |
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49 | |||
50 | |||
51 | |||
52 | |||
53 | goto retry_pre_get; |
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54 | } |
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55 | |||
56 | |||
57 | }; |
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58 | |||
59 | |||
60 | |||
1986 | serge | 61 | |
1404 | serge | 62 | { |
63 | u32 c = 0; |
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64 | |||
65 | |||
66 | rbo->placement.lpfn = 0; |
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67 | rbo->placement.placement = rbo->placements; |
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68 | rbo->placement.busy_placement = rbo->placements; |
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69 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
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70 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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71 | TTM_PL_FLAG_VRAM; |
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72 | if (domain & RADEON_GEM_DOMAIN_GTT) |
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73 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
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74 | if (domain & RADEON_GEM_DOMAIN_CPU) |
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75 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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76 | if (!c) |
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77 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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78 | rbo->placement.num_placement = c; |
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79 | rbo->placement.num_busy_placement = c; |
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80 | } |
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81 | |||
82 | |||
83 | |||
84 | { |
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85 | int r; |
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86 | |||
87 | |||
88 | rdev->mc.mc_vram_size >> 20, |
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89 | (unsigned long long)rdev->mc.aper_size >> 20); |
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90 | DRM_INFO("RAM width %dbits %cDR\n", |
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91 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
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92 | |||
93 | |||
94 | ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT)); |
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95 | if (r) { |
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96 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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97 | return r; |
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98 | }; |
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99 | |||
100 | |||
101 | if (r) { |
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102 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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103 | return r; |
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104 | } |
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105 | |||
106 | |||
107 | } |
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108 | |||
109 | |||
110 | |||
111 | { |
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112 | int r; |
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113 | |||
114 | |||
115 | |||
116 | |||
117 | } |
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118 | |||
119 | |||
120 | { |
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121 | bo->reserved.counter = 1; |
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122 | } |
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123 | |||
124 | |||
2997 | Serge | 125 | |
126 | |||
1963 | serge | 127 | unsigned long size, int byte_align, bool kernel, u32 domain, |
2997 | Serge | 128 | struct sg_table *sg, struct radeon_bo **bo_ptr) |
129 | { |
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1404 | serge | 130 | struct radeon_bo *bo; |
1986 | serge | 131 | enum ttm_bo_type type; |
1404 | serge | 132 | |
133 | |||
134 | struct drm_mm *mman; |
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135 | u32 bo_domain; |
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136 | int r; |
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137 | |||
138 | |||
139 | |||
140 | |||
2005 | serge | 141 | |
142 | |||
1404 | serge | 143 | dbgprintf("Illegal buffer object size.\n"); |
144 | return -EINVAL; |
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145 | } |
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146 | |||
147 | |||
148 | { |
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149 | mman = &mm_vram; |
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150 | bo_domain = RADEON_GEM_DOMAIN_VRAM; |
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151 | } |
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152 | else if(domain & RADEON_GEM_DOMAIN_GTT) |
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153 | { |
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154 | mman = &mm_gtt; |
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155 | bo_domain = RADEON_GEM_DOMAIN_GTT; |
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156 | } |
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157 | else return -EINVAL; |
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158 | |||
159 | |||
160 | type = ttm_bo_type_kernel; |
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161 | } else { |
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162 | type = ttm_bo_type_device; |
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163 | } |
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164 | *bo_ptr = NULL; |
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165 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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166 | if (bo == NULL) |
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167 | return -ENOMEM; |
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168 | |||
169 | |||
1986 | serge | 170 | if (unlikely(r)) { |
171 | kfree(bo); |
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172 | return r; |
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173 | } |
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174 | bo->rdev = rdev; |
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1404 | serge | 175 | bo->gem_base.driver_private = NULL; |
1986 | serge | 176 | bo->surface_reg = -1; |
1404 | serge | 177 | bo->tbo.num_pages = num_pages; |
178 | bo->domain = domain; |
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179 | |||
180 | |||
181 | |||
182 | |||
183 | /* Kernel allocation are uninterruptible */ |
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184 | |||
185 | |||
186 | if (unlikely(r != 0)) |
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187 | return r; |
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188 | |||
189 | |||
190 | |||
191 | |||
192 | } |
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193 | |||
194 | |||
195 | |||
196 | |||
197 | { |
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198 | int r=0, i; |
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199 | |||
200 | |||
201 | bo->pin_count++; |
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202 | if (gpu_addr) |
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203 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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204 | return 0; |
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205 | } |
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206 | |||
207 | |||
208 | |||
209 | |||
210 | { |
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211 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 212 | } |
1404 | serge | 213 | else if (bo->domain & RADEON_GEM_DOMAIN_GTT) |
214 | { |
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215 | u32_t *pagelist; |
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216 | bo->kptr = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT ); |
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217 | dbgprintf("kernel alloc %x\n", bo->kptr ); |
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218 | |||
219 | |||
220 | dbgprintf("pagelist %x\n", pagelist); |
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221 | radeon_gart_bind(bo->rdev, bo->tbo.offset, |
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222 | bo->tbo.vm_node->size, pagelist, NULL); |
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2997 | Serge | 223 | bo->tbo.offset += (u64)bo->rdev->mc.gtt_start; |
1430 | serge | 224 | } |
1404 | serge | 225 | else |
226 | { |
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227 | DRM_ERROR("Unknown placement %x\n", bo->domain); |
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228 | bo->tbo.offset = -1; |
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229 | r = -1; |
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230 | }; |
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231 | |||
232 | |||
233 | DRM_ERROR("radeon: failed to pin object.\n"); |
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234 | } |
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235 | |||
236 | |||
237 | bo->pin_count = 1; |
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238 | if (gpu_addr != NULL) |
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239 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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240 | } |
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241 | |||
242 | |||
243 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
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244 | return r; |
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245 | }; |
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246 | |||
247 | |||
248 | { |
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249 | int r = 0; |
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250 | |||
251 | |||
252 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
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253 | return 0; |
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254 | } |
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255 | bo->pin_count--; |
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256 | if (bo->pin_count) |
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257 | return 0; |
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258 | |||
259 | |||
260 | { |
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261 | drm_mm_put_block(bo->tbo.vm_node); |
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262 | bo->tbo.vm_node = NULL; |
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263 | }; |
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264 | |||
265 | |||
266 | } |
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267 | |||
268 | |||
269 | { |
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270 | bool is_iomem; |
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271 | |||
272 | |||
273 | if (ptr) { |
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274 | *ptr = bo->kptr; |
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275 | } |
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276 | return 0; |
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277 | } |
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278 | |||
279 | |||
280 | { |
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281 | bo->cpu_addr = bo->rdev->mc.aper_base + |
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282 | (bo->tbo.vm_node->start << PAGE_SHIFT); |
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283 | bo->kptr = (void*)MapIoMem(bo->cpu_addr, |
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284 | bo->tbo.vm_node->size << 12, PG_SW); |
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285 | } |
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286 | else |
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287 | { |
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288 | return -1; |
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289 | } |
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290 | |||
291 | |||
292 | *ptr = bo->kptr; |
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293 | } |
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294 | |||
295 | |||
296 | } |
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297 | |||
298 | |||
2007 | serge | 299 | { |
300 | bool is_iomem; |
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301 | |||
302 | |||
303 | if (ptr) { |
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304 | *ptr = bo->uptr; |
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305 | } |
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306 | return 0; |
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307 | } |
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308 | |||
309 | |||
310 | { |
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311 | return -1; |
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312 | } |
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313 | else |
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314 | { |
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315 | bo->uptr = UserAlloc(bo->tbo.num_pages << PAGE_SHIFT); |
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316 | if(bo->uptr) |
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317 | { |
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318 | u32_t *src, *dst; |
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319 | int count; |
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320 | src = &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12]; |
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321 | dst = &((u32_t*)page_tabs)[(u32_t)bo->uptr >> 12]; |
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322 | count = bo->tbo.num_pages; |
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323 | |||
324 | |||
325 | { |
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326 | *dst++ = (0xFFFFF000 & *src++) | 0x207 ; // map as shared page |
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327 | }; |
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328 | } |
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329 | else |
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330 | return -1; |
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331 | } |
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332 | |||
333 | |||
334 | *ptr = bo->uptr; |
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335 | } |
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336 | |||
337 | |||
338 | } |
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339 | |||
340 | |||
1404 | serge | 341 | { |
342 | if (bo->kptr == NULL) |
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343 | return; |
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344 | |||
345 | |||
346 | { |
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347 | FreeKernelSpace(bo->kptr); |
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348 | } |
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349 | |||
350 | |||
351 | |||
352 | |||
353 | |||
354 | |||
355 | { |
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356 | struct ttm_buffer_object *tbo; |
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357 | |||
358 | |||
359 | return; |
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360 | |||
361 | |||
362 | } |
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363 | |||
364 | |||
365 | |||
366 | uint32_t *tiling_flags, |
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367 | uint32_t *pitch) |
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368 | { |
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369 | // BUG_ON(!atomic_read(&bo->tbo.reserved)); |
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370 | if (tiling_flags) |
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371 | *tiling_flags = bo->tiling_flags; |
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372 | if (pitch) |
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373 | *pitch = bo->pitch; |
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374 | } |
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375 | |||
376 | |||
377 | |||
378 | * Allocate a GEM object of the specified size with shmfs backing store |
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379 | */ |
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380 | struct drm_gem_object * |
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381 | drm_gem_object_alloc(struct drm_device *dev, size_t size) |
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382 | { |
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383 | struct drm_gem_object *obj; |
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384 | |||
385 | |||
386 | |||
387 | |||
388 | |||
389 | |||
390 | obj->size = size; |
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391 | return obj; |
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392 | } |
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393 | |||
394 | |||
395 | |||
396 | unsigned long size, bool kernel, u32 domain, |
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397 | struct radeon_bo **bo_ptr) |
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398 | { |
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399 | enum ttm_bo_type type; |
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400 | |||
401 | |||
402 | struct drm_mm *mman; |
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403 | struct drm_mm_node *vm_node; |
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404 | |||
405 | |||
406 | u32 bo_domain; |
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407 | int r; |
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408 | |||
409 | |||
410 | |||
411 | |||
412 | dbgprintf("Illegal buffer object size.\n"); |
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413 | return -EINVAL; |
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414 | } |
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415 | |||
416 | |||
417 | RADEON_GEM_DOMAIN_VRAM ) |
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418 | { |
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419 | return -EINVAL; |
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420 | }; |
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421 | |||
422 | |||
423 | type = ttm_bo_type_kernel; |
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424 | } else { |
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425 | type = ttm_bo_type_device; |
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426 | } |
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427 | *bo_ptr = NULL; |
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428 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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429 | if (bo == NULL) |
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430 | return -ENOMEM; |
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431 | |||
432 | |||
433 | // bo->gobj = gobj; |
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1963 | serge | 434 | bo->surface_reg = -1; |
1404 | serge | 435 | bo->tbo.num_pages = num_pages; |
436 | bo->domain = domain; |
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437 | |||
438 | |||
439 | |||
440 | |||
441 | /* Kernel allocation are uninterruptible */ |
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442 | |||
443 | |||
444 | |||
445 | |||
446 | vm_node->start = 0; |
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447 | vm_node->mm = NULL; |
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448 | |||
449 | |||
450 | bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT; |
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451 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 452 | bo->kptr = (void*)0xFE000000; |
1404 | serge | 453 | bo->pin_count = 1; |
454 | |||
455 | |||
456 | |||
457 | |||
458 | }><>><>><>><>><>><>><> |
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459 |