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Rev | Author | Line No. | Line |
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1404 | serge | 1 | |
2 | #include |
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3 | #include "radeon_drm.h" |
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4 | #include "radeon.h" |
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5 | |||
6 | |||
7 | |||
8 | static struct drm_mm mm_vram; |
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9 | |||
10 | |||
1986 | serge | 11 | |
12 | * Initialize an already allocate GEM object of the specified size with |
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13 | * shmfs backing store. |
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14 | */ |
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15 | int drm_gem_object_init(struct drm_device *dev, |
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16 | struct drm_gem_object *obj, size_t size) |
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17 | { |
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18 | BUG_ON((size & (PAGE_SIZE - 1)) != 0); |
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19 | |||
20 | |||
21 | obj->filp = NULL; |
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22 | |||
23 | |||
24 | obj->size = size; |
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25 | |||
26 | |||
27 | } |
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28 | |||
29 | |||
30 | |||
1404 | serge | 31 | struct drm_mm_node **node) |
32 | { |
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33 | struct drm_mm_node *vm_node; |
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34 | int r; |
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35 | |||
36 | |||
37 | |||
38 | |||
39 | |||
40 | |||
41 | return r; |
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42 | |||
43 | |||
44 | |||
45 | |||
46 | r = -ENOMEM; |
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47 | return r; |
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48 | } |
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49 | |||
50 | |||
51 | |||
52 | |||
53 | goto retry_pre_get; |
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54 | } |
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55 | |||
56 | |||
57 | }; |
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58 | |||
59 | |||
60 | |||
1986 | serge | 61 | |
1404 | serge | 62 | { |
63 | u32 c = 0; |
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64 | |||
65 | |||
66 | rbo->placement.lpfn = 0; |
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67 | rbo->placement.placement = rbo->placements; |
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68 | rbo->placement.busy_placement = rbo->placements; |
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69 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
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70 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
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71 | TTM_PL_FLAG_VRAM; |
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72 | if (domain & RADEON_GEM_DOMAIN_GTT) |
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73 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
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74 | if (domain & RADEON_GEM_DOMAIN_CPU) |
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75 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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76 | if (!c) |
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77 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
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78 | rbo->placement.num_placement = c; |
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79 | rbo->placement.num_busy_placement = c; |
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80 | } |
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81 | |||
82 | |||
83 | |||
84 | { |
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85 | int r; |
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86 | |||
87 | |||
88 | rdev->mc.mc_vram_size >> 20, |
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89 | (unsigned long long)rdev->mc.aper_size >> 20); |
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90 | DRM_INFO("RAM width %dbits %cDR\n", |
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91 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
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92 | |||
93 | |||
94 | ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT)); |
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95 | if (r) { |
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96 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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97 | return r; |
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98 | }; |
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99 | |||
100 | |||
101 | if (r) { |
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102 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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103 | return r; |
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104 | } |
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105 | |||
106 | |||
107 | } |
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108 | |||
109 | |||
110 | |||
111 | { |
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112 | int r; |
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113 | |||
114 | |||
115 | |||
116 | |||
117 | } |
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118 | |||
119 | |||
120 | { |
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121 | bo->reserved.counter = 1; |
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122 | } |
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123 | |||
124 | |||
1963 | serge | 125 | unsigned long size, int byte_align, bool kernel, u32 domain, |
1986 | serge | 126 | struct radeon_bo **bo_ptr) |
1963 | serge | 127 | { |
1404 | serge | 128 | struct radeon_bo *bo; |
1986 | serge | 129 | enum ttm_bo_type type; |
1404 | serge | 130 | |
131 | |||
132 | struct drm_mm *mman; |
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133 | u32 bo_domain; |
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134 | int r; |
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135 | |||
136 | |||
137 | |||
138 | |||
139 | dbgprintf("Illegal buffer object size.\n"); |
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140 | return -EINVAL; |
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141 | } |
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142 | |||
143 | |||
144 | { |
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145 | mman = &mm_vram; |
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146 | bo_domain = RADEON_GEM_DOMAIN_VRAM; |
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147 | } |
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148 | else if(domain & RADEON_GEM_DOMAIN_GTT) |
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149 | { |
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150 | mman = &mm_gtt; |
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151 | bo_domain = RADEON_GEM_DOMAIN_GTT; |
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152 | } |
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153 | else return -EINVAL; |
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154 | |||
155 | |||
156 | type = ttm_bo_type_kernel; |
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157 | } else { |
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158 | type = ttm_bo_type_device; |
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159 | } |
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160 | *bo_ptr = NULL; |
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161 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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162 | if (bo == NULL) |
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163 | return -ENOMEM; |
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164 | |||
165 | |||
1986 | serge | 166 | if (unlikely(r)) { |
167 | kfree(bo); |
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168 | return r; |
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169 | } |
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170 | bo->rdev = rdev; |
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1404 | serge | 171 | bo->gem_base.driver_private = NULL; |
1986 | serge | 172 | bo->surface_reg = -1; |
1404 | serge | 173 | bo->tbo.num_pages = num_pages; |
174 | bo->domain = domain; |
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175 | |||
176 | |||
177 | |||
178 | |||
179 | /* Kernel allocation are uninterruptible */ |
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180 | |||
181 | |||
182 | if (unlikely(r != 0)) |
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183 | return r; |
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184 | |||
185 | |||
186 | |||
187 | |||
188 | } |
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189 | |||
190 | |||
191 | |||
192 | |||
193 | { |
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194 | int r=0, i; |
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195 | |||
196 | |||
197 | bo->pin_count++; |
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198 | if (gpu_addr) |
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199 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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200 | return 0; |
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201 | } |
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202 | |||
203 | |||
204 | |||
205 | |||
206 | { |
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207 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 208 | } |
1404 | serge | 209 | else if (bo->domain & RADEON_GEM_DOMAIN_GTT) |
210 | { |
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211 | u32_t *pagelist; |
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212 | bo->kptr = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT ); |
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213 | dbgprintf("kernel alloc %x\n", bo->kptr ); |
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214 | |||
215 | |||
216 | dbgprintf("pagelist %x\n", pagelist); |
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217 | radeon_gart_bind(bo->rdev, bo->tbo.offset, |
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218 | bo->tbo.vm_node->size, pagelist); |
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219 | bo->tbo.offset += (u64)bo->rdev->mc.gtt_start; |
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1430 | serge | 220 | } |
1404 | serge | 221 | else |
222 | { |
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223 | DRM_ERROR("Unknown placement %x\n", bo->domain); |
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224 | bo->tbo.offset = -1; |
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225 | r = -1; |
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226 | }; |
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227 | |||
228 | |||
229 | DRM_ERROR("radeon: failed to pin object.\n"); |
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230 | } |
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231 | |||
232 | |||
233 | bo->pin_count = 1; |
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234 | if (gpu_addr != NULL) |
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235 | *gpu_addr = radeon_bo_gpu_offset(bo); |
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236 | } |
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237 | |||
238 | |||
239 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
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240 | return r; |
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241 | }; |
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242 | |||
243 | |||
244 | { |
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245 | int r = 0; |
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246 | |||
247 | |||
248 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
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249 | return 0; |
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250 | } |
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251 | bo->pin_count--; |
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252 | if (bo->pin_count) |
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253 | return 0; |
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254 | |||
255 | |||
256 | { |
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257 | drm_mm_put_block(bo->tbo.vm_node); |
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258 | bo->tbo.vm_node = NULL; |
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259 | }; |
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260 | |||
261 | |||
262 | } |
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263 | |||
264 | |||
265 | { |
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266 | bool is_iomem; |
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267 | |||
268 | |||
269 | if (ptr) { |
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270 | *ptr = bo->kptr; |
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271 | } |
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272 | return 0; |
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273 | } |
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274 | |||
275 | |||
276 | { |
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277 | bo->cpu_addr = bo->rdev->mc.aper_base + |
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278 | (bo->tbo.vm_node->start << PAGE_SHIFT); |
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279 | bo->kptr = (void*)MapIoMem(bo->cpu_addr, |
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280 | bo->tbo.vm_node->size << 12, PG_SW); |
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281 | } |
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282 | else |
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283 | { |
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284 | return -1; |
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285 | } |
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286 | |||
287 | |||
288 | *ptr = bo->kptr; |
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289 | } |
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290 | |||
291 | |||
292 | } |
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293 | |||
294 | |||
295 | { |
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296 | if (bo->kptr == NULL) |
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297 | return; |
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298 | |||
299 | |||
300 | { |
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301 | FreeKernelSpace(bo->kptr); |
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302 | } |
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303 | |||
304 | |||
305 | |||
306 | |||
307 | |||
308 | |||
309 | { |
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310 | struct ttm_buffer_object *tbo; |
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311 | |||
312 | |||
313 | return; |
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314 | |||
315 | |||
316 | } |
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317 | |||
318 | |||
319 | |||
320 | uint32_t *tiling_flags, |
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321 | uint32_t *pitch) |
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322 | { |
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323 | // BUG_ON(!atomic_read(&bo->tbo.reserved)); |
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324 | if (tiling_flags) |
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325 | *tiling_flags = bo->tiling_flags; |
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326 | if (pitch) |
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327 | *pitch = bo->pitch; |
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328 | } |
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329 | |||
330 | |||
331 | |||
332 | * Allocate a GEM object of the specified size with shmfs backing store |
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333 | */ |
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334 | struct drm_gem_object * |
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335 | drm_gem_object_alloc(struct drm_device *dev, size_t size) |
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336 | { |
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337 | struct drm_gem_object *obj; |
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338 | |||
339 | |||
340 | |||
341 | |||
342 | |||
343 | |||
344 | obj->size = size; |
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345 | return obj; |
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346 | } |
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347 | |||
348 | |||
349 | |||
350 | unsigned long size, bool kernel, u32 domain, |
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351 | struct radeon_bo **bo_ptr) |
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352 | { |
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353 | enum ttm_bo_type type; |
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354 | |||
355 | |||
356 | struct drm_mm *mman; |
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357 | struct drm_mm_node *vm_node; |
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358 | |||
359 | |||
360 | u32 bo_domain; |
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361 | int r; |
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362 | |||
363 | |||
364 | |||
365 | |||
366 | dbgprintf("Illegal buffer object size.\n"); |
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367 | return -EINVAL; |
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368 | } |
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369 | |||
370 | |||
371 | RADEON_GEM_DOMAIN_VRAM ) |
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372 | { |
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373 | return -EINVAL; |
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374 | }; |
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375 | |||
376 | |||
377 | type = ttm_bo_type_kernel; |
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378 | } else { |
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379 | type = ttm_bo_type_device; |
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380 | } |
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381 | *bo_ptr = NULL; |
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382 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
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383 | if (bo == NULL) |
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384 | return -ENOMEM; |
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385 | |||
386 | |||
387 | // bo->gobj = gobj; |
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1963 | serge | 388 | bo->surface_reg = -1; |
1404 | serge | 389 | bo->tbo.num_pages = num_pages; |
390 | bo->domain = domain; |
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391 | |||
392 | |||
393 | |||
394 | |||
395 | /* Kernel allocation are uninterruptible */ |
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396 | |||
397 | |||
398 | |||
399 | |||
400 | vm_node->start = 0; |
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401 | vm_node->mm = NULL; |
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402 | |||
403 | |||
404 | bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT; |
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405 | bo->tbo.offset += (u64)bo->rdev->mc.vram_start; |
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1430 | serge | 406 | bo->kptr = (void*)0xFE000000; |
1404 | serge | 407 | bo->pin_count = 1; |
408 | |||
409 | |||
410 | |||
411 | |||
412 | }><>><>><>><>><> |
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413 |