Rev 5078 | Rev 5346 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
5078 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
||
3 | * All Rights Reserved. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the |
||
7 | * "Software"), to deal in the Software without restriction, including |
||
8 | * without limitation the rights to use, copy, modify, merge, publish, |
||
9 | * distribute, sub license, and/or sell copies of the Software, and to |
||
10 | * permit persons to whom the Software is furnished to do so, subject to |
||
11 | * the following conditions: |
||
12 | * |
||
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
||
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
||
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
||
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
||
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
||
20 | * |
||
21 | * The above copyright notice and this permission notice (including the |
||
22 | * next paragraph) shall be included in all copies or substantial portions |
||
23 | * of the Software. |
||
24 | * |
||
25 | */ |
||
26 | /* |
||
27 | * Authors: |
||
28 | * Jerome Glisse |
||
29 | * Thomas Hellstrom |
||
30 | * Dave Airlie |
||
31 | */ |
||
32 | #include |
||
33 | #include |
||
34 | #include |
||
35 | #include |
||
36 | #include "radeon.h" |
||
37 | #include "radeon_trace.h" |
||
38 | |||
39 | |||
40 | int radeon_ttm_init(struct radeon_device *rdev); |
||
41 | void radeon_ttm_fini(struct radeon_device *rdev); |
||
42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
||
43 | |||
44 | /* |
||
45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
||
46 | * function are calling it. |
||
47 | */ |
||
48 | |||
49 | static void radeon_update_memory_usage(struct radeon_bo *bo, |
||
50 | unsigned mem_type, int sign) |
||
51 | { |
||
52 | struct radeon_device *rdev = bo->rdev; |
||
53 | u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; |
||
54 | |||
55 | switch (mem_type) { |
||
56 | case TTM_PL_TT: |
||
57 | if (sign > 0) |
||
58 | __atomic_add_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
||
59 | else |
||
60 | __atomic_sub_fetch(&rdev->gtt_usage.counter, size,__ATOMIC_RELAXED); |
||
61 | break; |
||
62 | case TTM_PL_VRAM: |
||
63 | if (sign > 0) |
||
64 | __atomic_add_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED); |
||
65 | else |
||
66 | __atomic_sub_fetch(&rdev->vram_usage.counter, size,__ATOMIC_RELAXED ); |
||
67 | break; |
||
68 | } |
||
69 | } |
||
70 | |||
71 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
||
72 | { |
||
73 | struct radeon_bo *bo; |
||
74 | |||
75 | bo = container_of(tbo, struct radeon_bo, tbo); |
||
76 | |||
77 | radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); |
||
78 | |||
79 | mutex_lock(&bo->rdev->gem.mutex); |
||
80 | list_del_init(&bo->list); |
||
81 | mutex_unlock(&bo->rdev->gem.mutex); |
||
82 | radeon_bo_clear_surface_reg(bo); |
||
83 | WARN_ON(!list_empty(&bo->va)); |
||
84 | drm_gem_object_release(&bo->gem_base); |
||
85 | kfree(bo); |
||
86 | } |
||
87 | |||
88 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
||
89 | { |
||
90 | if (bo->destroy == &radeon_ttm_bo_destroy) |
||
91 | return true; |
||
92 | return false; |
||
93 | } |
||
94 | |||
95 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
||
96 | { |
||
97 | u32 c = 0, i; |
||
98 | |||
99 | rbo->placement.placement = rbo->placements; |
||
100 | rbo->placement.busy_placement = rbo->placements; |
||
5271 | serge | 101 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
102 | /* Try placing BOs which don't need CPU access outside of the |
||
103 | * CPU accessible part of VRAM |
||
104 | */ |
||
105 | if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
||
106 | rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { |
||
107 | rbo->placements[c].fpfn = |
||
108 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
||
109 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
||
110 | TTM_PL_FLAG_UNCACHED | |
||
5078 | serge | 111 | TTM_PL_FLAG_VRAM; |
5271 | serge | 112 | } |
113 | |||
114 | rbo->placements[c].fpfn = 0; |
||
115 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
||
116 | TTM_PL_FLAG_UNCACHED | |
||
117 | TTM_PL_FLAG_VRAM; |
||
118 | } |
||
119 | |||
5078 | serge | 120 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
121 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
||
5271 | serge | 122 | rbo->placements[c].fpfn = 0; |
123 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
||
124 | TTM_PL_FLAG_TT; |
||
125 | |||
5078 | serge | 126 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
127 | (rbo->rdev->flags & RADEON_IS_AGP)) { |
||
5271 | serge | 128 | rbo->placements[c].fpfn = 0; |
129 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
||
130 | TTM_PL_FLAG_UNCACHED | |
||
5078 | serge | 131 | TTM_PL_FLAG_TT; |
132 | } else { |
||
5271 | serge | 133 | rbo->placements[c].fpfn = 0; |
134 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
||
135 | TTM_PL_FLAG_TT; |
||
5078 | serge | 136 | } |
137 | } |
||
5271 | serge | 138 | |
5078 | serge | 139 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
140 | if (rbo->flags & RADEON_GEM_GTT_UC) { |
||
5271 | serge | 141 | rbo->placements[c].fpfn = 0; |
142 | rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | |
||
143 | TTM_PL_FLAG_SYSTEM; |
||
144 | |||
5078 | serge | 145 | } else if ((rbo->flags & RADEON_GEM_GTT_WC) || |
146 | rbo->rdev->flags & RADEON_IS_AGP) { |
||
5271 | serge | 147 | rbo->placements[c].fpfn = 0; |
148 | rbo->placements[c++].flags = TTM_PL_FLAG_WC | |
||
149 | TTM_PL_FLAG_UNCACHED | |
||
5078 | serge | 150 | TTM_PL_FLAG_SYSTEM; |
151 | } else { |
||
5271 | serge | 152 | rbo->placements[c].fpfn = 0; |
153 | rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | |
||
154 | TTM_PL_FLAG_SYSTEM; |
||
5078 | serge | 155 | } |
156 | } |
||
5271 | serge | 157 | if (!c) { |
158 | rbo->placements[c].fpfn = 0; |
||
159 | rbo->placements[c++].flags = TTM_PL_MASK_CACHING | |
||
160 | TTM_PL_FLAG_SYSTEM; |
||
161 | } |
||
162 | |||
5078 | serge | 163 | rbo->placement.num_placement = c; |
164 | rbo->placement.num_busy_placement = c; |
||
165 | |||
5271 | serge | 166 | for (i = 0; i < c; ++i) { |
167 | if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && |
||
168 | (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
||
169 | !rbo->placements[i].fpfn) |
||
170 | rbo->placements[i].lpfn = |
||
171 | rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
||
172 | else |
||
173 | rbo->placements[i].lpfn = 0; |
||
174 | } |
||
175 | |||
5078 | serge | 176 | /* |
177 | * Use two-ended allocation depending on the buffer size to |
||
178 | * improve fragmentation quality. |
||
179 | * 512kb was measured as the most optimal number. |
||
180 | */ |
||
181 | if (rbo->tbo.mem.size > 512 * 1024) { |
||
182 | for (i = 0; i < c; i++) { |
||
5271 | serge | 183 | rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; |
5078 | serge | 184 | } |
185 | } |
||
186 | } |
||
187 | |||
188 | int radeon_bo_create(struct radeon_device *rdev, |
||
5271 | serge | 189 | unsigned long size, int byte_align, bool kernel, |
190 | u32 domain, u32 flags, struct sg_table *sg, |
||
191 | struct reservation_object *resv, |
||
192 | struct radeon_bo **bo_ptr) |
||
5078 | serge | 193 | { |
194 | struct radeon_bo *bo; |
||
195 | enum ttm_bo_type type; |
||
196 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
||
197 | size_t acc_size; |
||
198 | int r; |
||
199 | |||
200 | size = ALIGN(size, PAGE_SIZE); |
||
201 | |||
202 | if (kernel) { |
||
203 | type = ttm_bo_type_kernel; |
||
204 | } else if (sg) { |
||
205 | type = ttm_bo_type_sg; |
||
206 | } else { |
||
207 | type = ttm_bo_type_device; |
||
208 | } |
||
209 | *bo_ptr = NULL; |
||
210 | |||
211 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
||
212 | sizeof(struct radeon_bo)); |
||
213 | |||
214 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
||
215 | if (bo == NULL) |
||
216 | return -ENOMEM; |
||
217 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
||
218 | if (unlikely(r)) { |
||
219 | kfree(bo); |
||
220 | return r; |
||
221 | } |
||
222 | bo->rdev = rdev; |
||
223 | bo->surface_reg = -1; |
||
224 | INIT_LIST_HEAD(&bo->list); |
||
225 | INIT_LIST_HEAD(&bo->va); |
||
226 | bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | |
||
227 | RADEON_GEM_DOMAIN_GTT | |
||
228 | RADEON_GEM_DOMAIN_CPU); |
||
229 | |||
230 | bo->flags = flags; |
||
231 | /* PCI GART is always snooped */ |
||
232 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
233 | bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
||
234 | |||
5271 | serge | 235 | #ifdef CONFIG_X86_32 |
236 | /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit |
||
237 | * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 |
||
238 | */ |
||
239 | bo->flags &= ~RADEON_GEM_GTT_WC; |
||
240 | #endif |
||
5078 | serge | 241 | |
242 | radeon_ttm_placement_from_domain(bo, domain); |
||
243 | /* Kernel allocation are uninterruptible */ |
||
244 | // down_read(&rdev->pm.mclk_lock); |
||
245 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
||
246 | &bo->placement, page_align, !kernel, NULL, |
||
5271 | serge | 247 | acc_size, sg, resv, &radeon_ttm_bo_destroy); |
5078 | serge | 248 | // up_read(&rdev->pm.mclk_lock); |
249 | if (unlikely(r != 0)) { |
||
250 | return r; |
||
251 | } |
||
252 | *bo_ptr = bo; |
||
253 | |||
254 | trace_radeon_bo_create(bo); |
||
255 | |||
256 | return 0; |
||
257 | } |
||
258 | |||
259 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
||
260 | { |
||
261 | bool is_iomem; |
||
262 | int r; |
||
263 | |||
264 | if (bo->kptr) { |
||
265 | if (ptr) { |
||
266 | *ptr = bo->kptr; |
||
267 | } |
||
268 | return 0; |
||
269 | } |
||
270 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
||
271 | if (r) { |
||
272 | return r; |
||
273 | } |
||
274 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
||
275 | if (ptr) { |
||
276 | *ptr = bo->kptr; |
||
277 | } |
||
278 | radeon_bo_check_tiling(bo, 0, 0); |
||
279 | return 0; |
||
280 | } |
||
281 | |||
282 | void radeon_bo_kunmap(struct radeon_bo *bo) |
||
283 | { |
||
284 | if (bo->kptr == NULL) |
||
285 | return; |
||
286 | bo->kptr = NULL; |
||
287 | radeon_bo_check_tiling(bo, 0, 0); |
||
288 | ttm_bo_kunmap(&bo->kmap); |
||
289 | } |
||
290 | |||
291 | struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) |
||
292 | { |
||
293 | if (bo == NULL) |
||
294 | return NULL; |
||
295 | |||
296 | ttm_bo_reference(&bo->tbo); |
||
297 | return bo; |
||
298 | } |
||
299 | |||
300 | void radeon_bo_unref(struct radeon_bo **bo) |
||
301 | { |
||
302 | struct ttm_buffer_object *tbo; |
||
303 | struct radeon_device *rdev; |
||
304 | |||
305 | if ((*bo) == NULL) |
||
306 | return; |
||
307 | rdev = (*bo)->rdev; |
||
308 | tbo = &((*bo)->tbo); |
||
309 | ttm_bo_unref(&tbo); |
||
310 | if (tbo == NULL) |
||
311 | *bo = NULL; |
||
312 | } |
||
313 | |||
314 | int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, |
||
315 | u64 *gpu_addr) |
||
316 | { |
||
317 | int r, i; |
||
318 | |||
319 | if (bo->pin_count) { |
||
320 | bo->pin_count++; |
||
321 | if (gpu_addr) |
||
322 | *gpu_addr = radeon_bo_gpu_offset(bo); |
||
323 | |||
324 | if (max_offset != 0) { |
||
325 | u64 domain_start; |
||
326 | |||
327 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
||
328 | domain_start = bo->rdev->mc.vram_start; |
||
329 | else |
||
330 | domain_start = bo->rdev->mc.gtt_start; |
||
331 | WARN_ON_ONCE(max_offset < |
||
332 | (radeon_bo_gpu_offset(bo) - domain_start)); |
||
333 | } |
||
334 | |||
335 | return 0; |
||
336 | } |
||
337 | radeon_ttm_placement_from_domain(bo, domain); |
||
5271 | serge | 338 | for (i = 0; i < bo->placement.num_placement; i++) { |
5078 | serge | 339 | /* force to pin into visible video ram */ |
5271 | serge | 340 | if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && |
341 | !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && |
||
342 | (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) |
||
343 | bo->placements[i].lpfn = |
||
344 | bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
||
345 | else |
||
346 | bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; |
||
347 | |||
348 | bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; |
||
5078 | serge | 349 | } |
350 | |||
351 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
||
352 | if (likely(r == 0)) { |
||
353 | bo->pin_count = 1; |
||
354 | if (gpu_addr != NULL) |
||
355 | *gpu_addr = radeon_bo_gpu_offset(bo); |
||
356 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
||
357 | bo->rdev->vram_pin_size += radeon_bo_size(bo); |
||
358 | else |
||
359 | bo->rdev->gart_pin_size += radeon_bo_size(bo); |
||
360 | } else { |
||
361 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
||
362 | } |
||
363 | return r; |
||
364 | } |
||
365 | |||
366 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
||
367 | { |
||
368 | return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); |
||
369 | } |
||
370 | |||
371 | int radeon_bo_unpin(struct radeon_bo *bo) |
||
372 | { |
||
373 | int r, i; |
||
374 | |||
375 | if (!bo->pin_count) { |
||
376 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
||
377 | return 0; |
||
378 | } |
||
379 | bo->pin_count--; |
||
380 | if (bo->pin_count) |
||
381 | return 0; |
||
5271 | serge | 382 | for (i = 0; i < bo->placement.num_placement; i++) { |
383 | bo->placements[i].lpfn = 0; |
||
384 | bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; |
||
385 | } |
||
5078 | serge | 386 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
387 | if (likely(r == 0)) { |
||
388 | if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
||
389 | bo->rdev->vram_pin_size -= radeon_bo_size(bo); |
||
390 | else |
||
391 | bo->rdev->gart_pin_size -= radeon_bo_size(bo); |
||
392 | } else { |
||
393 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
||
394 | } |
||
395 | return r; |
||
396 | } |
||
397 | |||
398 | int radeon_bo_init(struct radeon_device *rdev) |
||
399 | { |
||
400 | /* Add an MTRR for the VRAM */ |
||
401 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
||
402 | rdev->mc.mc_vram_size >> 20, |
||
403 | (unsigned long long)rdev->mc.aper_size >> 20); |
||
404 | DRM_INFO("RAM width %dbits %cDR\n", |
||
405 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
||
406 | return radeon_ttm_init(rdev); |
||
407 | } |
||
408 | |||
409 | void radeon_bo_fini(struct radeon_device *rdev) |
||
410 | { |
||
411 | // radeon_ttm_fini(rdev); |
||
412 | // arch_phys_wc_del(rdev->mc.vram_mtrr); |
||
413 | } |
||
414 | |||
415 | /* Returns how many bytes TTM can move per IB. |
||
416 | */ |
||
417 | static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) |
||
418 | { |
||
419 | u64 real_vram_size = rdev->mc.real_vram_size; |
||
420 | u64 vram_usage = atomic64_read(&rdev->vram_usage); |
||
421 | |||
422 | /* This function is based on the current VRAM usage. |
||
423 | * |
||
424 | * - If all of VRAM is free, allow relocating the number of bytes that |
||
425 | * is equal to 1/4 of the size of VRAM for this IB. |
||
426 | |||
427 | * - If more than one half of VRAM is occupied, only allow relocating |
||
428 | * 1 MB of data for this IB. |
||
429 | * |
||
430 | * - From 0 to one half of used VRAM, the threshold decreases |
||
431 | * linearly. |
||
432 | * __________________ |
||
433 | * 1/4 of -|\ | |
||
434 | * VRAM | \ | |
||
435 | * | \ | |
||
436 | * | \ | |
||
437 | * | \ | |
||
438 | * | \ | |
||
439 | * | \ | |
||
440 | * | \________|1 MB |
||
441 | * |----------------| |
||
442 | * VRAM 0 % 100 % |
||
443 | * used used |
||
444 | * |
||
445 | * Note: It's a threshold, not a limit. The threshold must be crossed |
||
446 | * for buffer relocations to stop, so any buffer of an arbitrary size |
||
447 | * can be moved as long as the threshold isn't crossed before |
||
448 | * the relocation takes place. We don't want to disable buffer |
||
449 | * relocations completely. |
||
450 | * |
||
451 | * The idea is that buffers should be placed in VRAM at creation time |
||
452 | * and TTM should only do a minimum number of relocations during |
||
453 | * command submission. In practice, you need to submit at least |
||
454 | * a dozen IBs to move all buffers to VRAM if they are in GTT. |
||
455 | * |
||
456 | * Also, things can get pretty crazy under memory pressure and actual |
||
457 | * VRAM usage can change a lot, so playing safe even at 50% does |
||
458 | * consistently increase performance. |
||
459 | */ |
||
460 | |||
461 | u64 half_vram = real_vram_size >> 1; |
||
462 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; |
||
463 | u64 bytes_moved_threshold = half_free_vram >> 1; |
||
464 | return max(bytes_moved_threshold, 1024*1024ull); |
||
465 | } |
||
466 | |||
467 | int radeon_bo_list_validate(struct radeon_device *rdev, |
||
468 | struct ww_acquire_ctx *ticket, |
||
469 | struct list_head *head, int ring) |
||
470 | { |
||
5271 | serge | 471 | struct radeon_bo_list *lobj; |
472 | struct list_head duplicates; |
||
5078 | serge | 473 | int r; |
474 | u64 bytes_moved = 0, initial_bytes_moved; |
||
475 | u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); |
||
476 | |||
5271 | serge | 477 | INIT_LIST_HEAD(&duplicates); |
478 | r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); |
||
5078 | serge | 479 | if (unlikely(r != 0)) { |
480 | return r; |
||
481 | } |
||
482 | |||
483 | list_for_each_entry(lobj, head, tv.head) { |
||
5271 | serge | 484 | struct radeon_bo *bo = lobj->robj; |
5078 | serge | 485 | if (!bo->pin_count) { |
486 | u32 domain = lobj->prefered_domains; |
||
5271 | serge | 487 | u32 allowed = lobj->allowed_domains; |
5078 | serge | 488 | u32 current_domain = |
489 | radeon_mem_type_to_domain(bo->tbo.mem.mem_type); |
||
490 | |||
5271 | serge | 491 | WARN_ONCE(bo->gem_base.dumb, |
492 | "GPU use of dumb buffer is illegal.\n"); |
||
493 | |||
5078 | serge | 494 | /* Check if this buffer will be moved and don't move it |
495 | * if we have moved too many buffers for this IB already. |
||
496 | * |
||
497 | * Note that this allows moving at least one buffer of |
||
498 | * any size, because it doesn't take the current "bo" |
||
499 | * into account. We don't want to disallow buffer moves |
||
500 | * completely. |
||
501 | */ |
||
5271 | serge | 502 | if ((allowed & current_domain) != 0 && |
5078 | serge | 503 | (domain & current_domain) == 0 && /* will be moved */ |
504 | bytes_moved > bytes_moved_threshold) { |
||
505 | /* don't move it */ |
||
506 | domain = current_domain; |
||
507 | } |
||
508 | |||
509 | retry: |
||
510 | radeon_ttm_placement_from_domain(bo, domain); |
||
511 | if (ring == R600_RING_TYPE_UVD_INDEX) |
||
5271 | serge | 512 | radeon_uvd_force_into_uvd_segment(bo, allowed); |
5078 | serge | 513 | |
514 | initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); |
||
515 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
||
516 | bytes_moved += atomic64_read(&rdev->num_bytes_moved) - |
||
517 | initial_bytes_moved; |
||
518 | |||
519 | if (unlikely(r)) { |
||
520 | if (r != -ERESTARTSYS && |
||
521 | domain != lobj->allowed_domains) { |
||
522 | domain = lobj->allowed_domains; |
||
523 | goto retry; |
||
524 | } |
||
525 | ttm_eu_backoff_reservation(ticket, head); |
||
526 | return r; |
||
527 | } |
||
528 | } |
||
529 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
||
530 | lobj->tiling_flags = bo->tiling_flags; |
||
531 | } |
||
5271 | serge | 532 | |
533 | list_for_each_entry(lobj, &duplicates, tv.head) { |
||
534 | lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); |
||
535 | lobj->tiling_flags = lobj->robj->tiling_flags; |
||
536 | } |
||
537 | |||
5078 | serge | 538 | return 0; |
539 | } |
||
540 | |||
541 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
||
542 | { |
||
543 | struct radeon_device *rdev = bo->rdev; |
||
544 | struct radeon_surface_reg *reg; |
||
545 | struct radeon_bo *old_object; |
||
546 | int steal; |
||
547 | int i; |
||
548 | |||
549 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
550 | |||
551 | if (!bo->tiling_flags) |
||
552 | return 0; |
||
553 | |||
554 | if (bo->surface_reg >= 0) { |
||
555 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
556 | i = bo->surface_reg; |
||
557 | goto out; |
||
558 | } |
||
559 | |||
560 | steal = -1; |
||
561 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
||
562 | |||
563 | reg = &rdev->surface_regs[i]; |
||
564 | if (!reg->bo) |
||
565 | break; |
||
566 | |||
567 | old_object = reg->bo; |
||
568 | if (old_object->pin_count == 0) |
||
569 | steal = i; |
||
570 | } |
||
571 | |||
572 | /* if we are all out */ |
||
573 | if (i == RADEON_GEM_MAX_SURFACES) { |
||
574 | if (steal == -1) |
||
575 | return -ENOMEM; |
||
576 | /* find someone with a surface reg and nuke their BO */ |
||
577 | reg = &rdev->surface_regs[steal]; |
||
578 | old_object = reg->bo; |
||
579 | /* blow away the mapping */ |
||
580 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
||
581 | ttm_bo_unmap_virtual(&old_object->tbo); |
||
582 | old_object->surface_reg = -1; |
||
583 | i = steal; |
||
584 | } |
||
585 | |||
586 | bo->surface_reg = i; |
||
587 | reg->bo = bo; |
||
588 | |||
589 | out: |
||
590 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
||
591 | bo->tbo.mem.start << PAGE_SHIFT, |
||
592 | bo->tbo.num_pages << PAGE_SHIFT); |
||
593 | return 0; |
||
594 | } |
||
595 | |||
596 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
||
597 | { |
||
598 | struct radeon_device *rdev = bo->rdev; |
||
599 | struct radeon_surface_reg *reg; |
||
600 | |||
601 | if (bo->surface_reg == -1) |
||
602 | return; |
||
603 | |||
604 | reg = &rdev->surface_regs[bo->surface_reg]; |
||
605 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
||
606 | |||
607 | reg->bo = NULL; |
||
608 | bo->surface_reg = -1; |
||
609 | } |
||
610 | |||
611 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
||
612 | uint32_t tiling_flags, uint32_t pitch) |
||
613 | { |
||
614 | struct radeon_device *rdev = bo->rdev; |
||
615 | int r; |
||
616 | |||
617 | if (rdev->family >= CHIP_CEDAR) { |
||
618 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; |
||
619 | |||
620 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; |
||
621 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; |
||
622 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; |
||
623 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; |
||
624 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; |
||
625 | switch (bankw) { |
||
626 | case 0: |
||
627 | case 1: |
||
628 | case 2: |
||
629 | case 4: |
||
630 | case 8: |
||
631 | break; |
||
632 | default: |
||
633 | return -EINVAL; |
||
634 | } |
||
635 | switch (bankh) { |
||
636 | case 0: |
||
637 | case 1: |
||
638 | case 2: |
||
639 | case 4: |
||
640 | case 8: |
||
641 | break; |
||
642 | default: |
||
643 | return -EINVAL; |
||
644 | } |
||
645 | switch (mtaspect) { |
||
646 | case 0: |
||
647 | case 1: |
||
648 | case 2: |
||
649 | case 4: |
||
650 | case 8: |
||
651 | break; |
||
652 | default: |
||
653 | return -EINVAL; |
||
654 | } |
||
655 | if (tilesplit > 6) { |
||
656 | return -EINVAL; |
||
657 | } |
||
658 | if (stilesplit > 6) { |
||
659 | return -EINVAL; |
||
660 | } |
||
661 | } |
||
662 | r = radeon_bo_reserve(bo, false); |
||
663 | if (unlikely(r != 0)) |
||
664 | return r; |
||
665 | bo->tiling_flags = tiling_flags; |
||
666 | bo->pitch = pitch; |
||
667 | radeon_bo_unreserve(bo); |
||
668 | return 0; |
||
669 | } |
||
670 | |||
671 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
||
672 | uint32_t *tiling_flags, |
||
673 | uint32_t *pitch) |
||
674 | { |
||
675 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
676 | |||
677 | if (tiling_flags) |
||
678 | *tiling_flags = bo->tiling_flags; |
||
679 | if (pitch) |
||
680 | *pitch = bo->pitch; |
||
681 | } |
||
682 | |||
683 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
||
684 | bool force_drop) |
||
685 | { |
||
686 | if (!force_drop) |
||
687 | lockdep_assert_held(&bo->tbo.resv->lock.base); |
||
688 | |||
689 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
||
690 | return 0; |
||
691 | |||
692 | if (force_drop) { |
||
693 | radeon_bo_clear_surface_reg(bo); |
||
694 | return 0; |
||
695 | } |
||
696 | |||
697 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
||
698 | if (!has_moved) |
||
699 | return 0; |
||
700 | |||
701 | if (bo->surface_reg >= 0) |
||
702 | radeon_bo_clear_surface_reg(bo); |
||
703 | return 0; |
||
704 | } |
||
705 | |||
706 | if ((bo->surface_reg >= 0) && !has_moved) |
||
707 | return 0; |
||
708 | |||
709 | return radeon_bo_get_surface_reg(bo); |
||
710 | } |
||
711 | |||
712 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
||
713 | struct ttm_mem_reg *new_mem) |
||
714 | { |
||
715 | struct radeon_bo *rbo; |
||
716 | |||
717 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
||
718 | return; |
||
719 | |||
720 | rbo = container_of(bo, struct radeon_bo, tbo); |
||
721 | radeon_bo_check_tiling(rbo, 0, 1); |
||
722 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
||
723 | |||
724 | /* update statistics */ |
||
725 | if (!new_mem) |
||
726 | return; |
||
727 | |||
728 | radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); |
||
729 | radeon_update_memory_usage(rbo, new_mem->mem_type, 1); |
||
730 | } |
||
731 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
||
732 | { |
||
733 | int r; |
||
734 | |||
735 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); |
||
736 | if (unlikely(r != 0)) |
||
737 | return r; |
||
738 | if (mem_type) |
||
739 | *mem_type = bo->tbo.mem.mem_type; |
||
5271 | serge | 740 | |
5078 | serge | 741 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); |
742 | ttm_bo_unreserve(&bo->tbo); |
||
743 | return r; |
||
744 | } |
||
5271 | serge | 745 | |
746 | /** |
||
747 | * radeon_bo_fence - add fence to buffer object |
||
748 | * |
||
749 | * @bo: buffer object in question |
||
750 | * @fence: fence to add |
||
751 | * @shared: true if fence should be added shared |
||
752 | * |
||
753 | */ |
||
754 | void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, |
||
755 | bool shared) |
||
756 | { |
||
757 | struct reservation_object *resv = bo->tbo.resv; |
||
758 | |||
759 | if (shared) |
||
760 | reservation_object_add_shared_fence(resv, &fence->base); |
||
761 | else |
||
762 | reservation_object_add_excl_fence(resv, &fence->base); |
||
763 | }><>><>>>> |