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| Rev | Author | Line No. | Line |
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| 1120 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Thomas Hellstrom |
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| 30 | * Dave Airlie |
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| 31 | */ |
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| 1179 | serge | 32 | #include |
| 33 | #include |
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| 1120 | serge | 34 | #include "radeon_drm.h" |
| 35 | #include "radeon.h" |
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| 36 | #include |
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| 1126 | serge | 37 | #include "radeon_object.h" |
| 1120 | serge | 38 | |
| 39 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
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| 40 | int pages, u32_t *pagelist); |
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| 41 | |||
| 42 | |||
| 43 | |||
| 44 | |||
| 45 | static struct drm_mm mm_gtt; |
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| 46 | static struct drm_mm mm_vram; |
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| 47 | |||
| 48 | |||
| 49 | int radeon_object_init(struct radeon_device *rdev) |
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| 50 | { |
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| 51 | int r = 0; |
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| 52 | |||
| 1125 | serge | 53 | dbgprintf("%s\n",__FUNCTION__); |
| 54 | |||
| 1120 | serge | 55 | r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT, |
| 56 | ((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT)); |
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| 57 | if (r) { |
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| 58 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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| 59 | return r; |
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| 60 | }; |
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| 61 | |||
| 62 | r = drm_mm_init(&mm_gtt, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); |
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| 63 | if (r) { |
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| 64 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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| 65 | return r; |
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| 66 | } |
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| 67 | |||
| 68 | return r; |
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| 69 | // return radeon_ttm_init(rdev); |
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| 70 | } |
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| 71 | |||
| 72 | static inline uint32_t radeon_object_flags_from_domain(uint32_t domain) |
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| 73 | { |
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| 74 | uint32_t flags = 0; |
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| 75 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
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| 76 | flags |= TTM_PL_FLAG_VRAM; |
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| 77 | } |
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| 78 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
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| 79 | flags |= TTM_PL_FLAG_TT; |
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| 80 | } |
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| 81 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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| 82 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 83 | } |
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| 84 | if (!flags) { |
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| 85 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 86 | } |
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| 87 | return flags; |
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| 88 | } |
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| 89 | |||
| 90 | |||
| 91 | int radeon_object_create(struct radeon_device *rdev, |
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| 92 | struct drm_gem_object *gobj, |
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| 93 | unsigned long size, |
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| 94 | bool kernel, |
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| 95 | uint32_t domain, |
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| 96 | bool interruptible, |
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| 97 | struct radeon_object **robj_ptr) |
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| 98 | { |
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| 99 | struct radeon_object *robj; |
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| 100 | enum ttm_bo_type type; |
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| 101 | uint32_t flags; |
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| 102 | int r; |
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| 103 | |||
| 104 | dbgprintf("%s\n",__FUNCTION__); |
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| 105 | |||
| 106 | if (kernel) { |
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| 107 | type = ttm_bo_type_kernel; |
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| 108 | } else { |
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| 109 | type = ttm_bo_type_device; |
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| 110 | } |
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| 111 | *robj_ptr = NULL; |
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| 112 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 113 | if (robj == NULL) { |
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| 114 | return -ENOMEM; |
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| 115 | } |
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| 116 | robj->rdev = rdev; |
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| 117 | // robj->gobj = gobj; |
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| 118 | INIT_LIST_HEAD(&robj->list); |
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| 119 | |||
| 120 | flags = radeon_object_flags_from_domain(domain); |
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| 121 | |||
| 122 | robj->flags = flags; |
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| 123 | |||
| 124 | dbgprintf("robj flags %x\n", robj->flags); |
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| 125 | |||
| 126 | if( flags & TTM_PL_FLAG_VRAM) |
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| 127 | { |
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| 128 | size_t num_pages; |
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| 129 | |||
| 130 | struct drm_mm_node *vm_node; |
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| 131 | |||
| 132 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 133 | |||
| 134 | if (num_pages == 0) { |
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| 135 | printk("Illegal buffer object size.\n"); |
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| 136 | return -EINVAL; |
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| 137 | } |
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| 138 | retry_pre_get: |
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| 139 | r = drm_mm_pre_get(&mm_vram); |
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| 140 | |||
| 141 | if (unlikely(r != 0)) |
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| 142 | return r; |
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| 143 | |||
| 144 | vm_node = drm_mm_search_free(&mm_vram, num_pages, 0, 0); |
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| 145 | |||
| 146 | if (unlikely(vm_node == NULL)) { |
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| 147 | r = -ENOMEM; |
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| 148 | return r; |
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| 149 | } |
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| 150 | |||
| 151 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 152 | |||
| 153 | if (unlikely(robj->mm_node == NULL)) { |
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| 154 | goto retry_pre_get; |
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| 155 | } |
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| 156 | |||
| 157 | robj->vm_addr = ((uint32_t)robj->mm_node->start); |
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| 158 | |||
| 159 | dbgprintf("alloc vram: base %x size %x\n", |
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| 160 | robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 161 | |||
| 162 | }; |
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| 163 | |||
| 164 | if( flags & TTM_PL_FLAG_TT) |
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| 165 | { |
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| 166 | size_t num_pages; |
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| 167 | |||
| 168 | struct drm_mm_node *vm_node; |
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| 169 | |||
| 170 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 171 | |||
| 172 | if (num_pages == 0) { |
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| 173 | printk("Illegal buffer object size.\n"); |
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| 174 | return -EINVAL; |
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| 175 | } |
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| 176 | retry_pre_get1: |
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| 177 | r = drm_mm_pre_get(&mm_gtt); |
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| 178 | |||
| 179 | if (unlikely(r != 0)) |
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| 180 | return r; |
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| 181 | |||
| 182 | vm_node = drm_mm_search_free(&mm_gtt, num_pages, 0, 0); |
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| 183 | |||
| 184 | if (unlikely(vm_node == NULL)) { |
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| 185 | r = -ENOMEM; |
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| 186 | return r; |
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| 187 | } |
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| 188 | |||
| 189 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 190 | |||
| 191 | if (unlikely(robj->mm_node == NULL)) { |
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| 192 | goto retry_pre_get1; |
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| 193 | } |
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| 194 | |||
| 195 | robj->vm_addr = ((uint32_t)robj->mm_node->start) ; |
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| 196 | |||
| 197 | dbgprintf("alloc gtt: base %x size %x\n", |
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| 198 | robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 199 | }; |
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| 200 | |||
| 201 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 202 | // 0, 0, false, NULL, size, |
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| 203 | // &radeon_ttm_object_object_destroy); |
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| 204 | if (unlikely(r != 0)) { |
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| 205 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 206 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 207 | size, flags, 0); |
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| 208 | return r; |
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| 209 | } |
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| 210 | *robj_ptr = robj; |
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| 211 | // if (gobj) { |
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| 212 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 213 | // } |
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| 214 | return 0; |
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| 215 | } |
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| 216 | |||
| 217 | #define page_tabs 0xFDC00000 |
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| 218 | |||
| 219 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
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| 220 | uint64_t *gpu_addr) |
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| 221 | { |
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| 222 | uint32_t flags; |
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| 223 | uint32_t tmp; |
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| 224 | int r = 0; |
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| 225 | |||
| 226 | dbgprintf("%s\n",__FUNCTION__); |
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| 227 | |||
| 228 | // flags = radeon_object_flags_from_domain(domain); |
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| 229 | // spin_lock(&robj->tobj.lock); |
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| 230 | if (robj->pin_count) { |
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| 231 | robj->pin_count++; |
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| 232 | if (gpu_addr != NULL) { |
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| 233 | *gpu_addr = robj->gpu_addr; |
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| 234 | } |
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| 235 | // spin_unlock(&robj->tobj.lock); |
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| 236 | return 0; |
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| 237 | } |
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| 238 | // spin_unlock(&robj->tobj.lock); |
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| 239 | // r = radeon_object_reserve(robj, false); |
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| 240 | // if (unlikely(r != 0)) { |
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| 241 | // DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
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| 242 | // return r; |
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| 243 | // } |
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| 244 | // tmp = robj->tobj.mem.placement; |
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| 245 | // ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
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| 246 | // robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
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| 247 | // r = ttm_buffer_object_validate(&robj->tobj, |
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| 248 | // robj->tobj.proposed_placement, |
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| 249 | // false, false); |
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| 250 | |||
| 251 | robj->gpu_addr = ((u64)robj->vm_addr) << PAGE_SHIFT; |
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| 252 | |||
| 253 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 254 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 255 | else if (robj->flags & TTM_PL_FLAG_TT) |
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| 256 | { |
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| 257 | u32_t *pagelist; |
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| 258 | robj->kptr = KernelAlloc( robj->mm_node->size << PAGE_SHIFT ); |
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| 259 | dbgprintf("kernel alloc %x\n", robj->kptr ); |
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| 260 | |||
| 261 | pagelist = &((u32_t*)page_tabs)[(u32_t)robj->kptr >> 12]; |
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| 262 | dbgprintf("pagelist %x\n", pagelist); |
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| 263 | radeon_gart_bind(robj->rdev, robj->gpu_addr, |
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| 264 | robj->mm_node->size, pagelist); |
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| 265 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 266 | } |
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| 267 | else |
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| 268 | { |
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| 269 | DRM_ERROR("Unknown placement %d\n", robj->flags); |
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| 270 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 271 | r = -1; |
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| 272 | }; |
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| 273 | |||
| 274 | // flags & TTM_PL_FLAG_VRAM |
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| 275 | if (gpu_addr != NULL) { |
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| 276 | *gpu_addr = robj->gpu_addr; |
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| 277 | } |
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| 278 | robj->pin_count = 1; |
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| 279 | if (unlikely(r != 0)) { |
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| 280 | DRM_ERROR("radeon: failed to pin object.\n"); |
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| 281 | } |
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| 282 | |||
| 283 | dbgprintf("done %s\n",__FUNCTION__); |
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| 284 | |||
| 285 | return r; |
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| 286 | } |
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| 287 | |||
| 288 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 289 | { |
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| 290 | int r = 0; |
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| 291 | |||
| 292 | dbgprintf("%s\n",__FUNCTION__); |
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| 293 | |||
| 294 | // spin_lock(&robj->tobj.lock); |
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| 295 | if (robj->kptr) { |
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| 296 | if (ptr) { |
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| 297 | *ptr = robj->kptr; |
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| 298 | } |
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| 299 | // spin_unlock(&robj->tobj.lock); |
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| 300 | return 0; |
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| 301 | } |
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| 302 | // spin_unlock(&robj->tobj.lock); |
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| 303 | |||
| 304 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 305 | { |
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| 306 | robj->cpu_addr = robj->rdev->mc.aper_base + |
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| 307 | (robj->vm_addr << PAGE_SHIFT); |
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| 308 | robj->kptr = (void*)MapIoMem(robj->cpu_addr, |
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| 309 | robj->mm_node->size << 12, PG_SW); |
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| 310 | dbgprintf("map io mem %x at %x\n", robj->cpu_addr, robj->kptr); |
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| 311 | |||
| 312 | } |
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| 313 | else |
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| 314 | { |
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| 315 | return -1; |
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| 316 | } |
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| 317 | |||
| 318 | if (ptr) { |
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| 319 | *ptr = robj->kptr; |
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| 320 | } |
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| 321 | |||
| 322 | dbgprintf("done %s\n",__FUNCTION__); |
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| 323 | |||
| 324 | return 0; |
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| 325 | } |
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| 326 | |||
| 327 | |||
| 328 | #if 0 |
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| 329 | |||
| 330 | void radeon_object_unpin(struct radeon_object *robj) |
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| 331 | { |
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| 332 | uint32_t flags; |
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| 333 | int r; |
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| 334 | |||
| 335 | // spin_lock(&robj->tobj.lock); |
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| 336 | if (!robj->pin_count) { |
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| 337 | // spin_unlock(&robj->tobj.lock); |
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| 338 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
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| 339 | return; |
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| 340 | } |
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| 341 | robj->pin_count--; |
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| 342 | if (robj->pin_count) { |
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| 343 | // spin_unlock(&robj->tobj.lock); |
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| 344 | return; |
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| 345 | } |
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| 346 | // spin_unlock(&robj->tobj.lock); |
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| 347 | r = radeon_object_reserve(robj, false); |
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| 348 | if (unlikely(r != 0)) { |
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| 349 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
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| 350 | return; |
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| 351 | } |
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| 352 | flags = robj->tobj.mem.placement; |
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| 353 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
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| 354 | r = ttm_buffer_object_validate(&robj->tobj, |
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| 355 | robj->tobj.proposed_placement, |
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| 356 | false, false); |
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| 357 | if (unlikely(r != 0)) { |
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| 358 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
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| 359 | } |
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| 360 | radeon_object_unreserve(robj); |
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| 361 | } |
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| 362 | |||
| 363 | |||
| 364 | |||
| 365 | |||
| 366 | |||
| 367 | /* |
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| 368 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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| 369 | * function are calling it. |
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| 370 | */ |
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| 371 | |||
| 372 | static int radeon_object_reserve(struct radeon_object *robj, bool interruptible) |
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| 373 | { |
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| 374 | return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0); |
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| 375 | } |
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| 376 | |||
| 377 | static void radeon_object_unreserve(struct radeon_object *robj) |
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| 378 | { |
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| 379 | ttm_bo_unreserve(&robj->tobj); |
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| 380 | } |
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| 381 | |||
| 382 | static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj) |
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| 383 | { |
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| 384 | struct radeon_object *robj; |
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| 385 | |||
| 386 | robj = container_of(tobj, struct radeon_object, tobj); |
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| 387 | // list_del_init(&robj->list); |
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| 388 | kfree(robj); |
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| 389 | } |
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| 390 | |||
| 391 | static inline void radeon_object_gpu_addr(struct radeon_object *robj) |
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| 392 | { |
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| 393 | /* Default gpu address */ |
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| 394 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 395 | if (robj->tobj.mem.mm_node == NULL) { |
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| 396 | return; |
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| 397 | } |
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| 398 | robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT; |
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| 399 | switch (robj->tobj.mem.mem_type) { |
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| 400 | case TTM_PL_VRAM: |
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| 401 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 402 | break; |
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| 403 | case TTM_PL_TT: |
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| 404 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 405 | break; |
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| 406 | default: |
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| 407 | DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type); |
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| 408 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 409 | return; |
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| 410 | } |
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| 411 | } |
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| 412 | |||
| 413 | |||
| 414 | int radeon_object_create(struct radeon_device *rdev, |
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| 415 | struct drm_gem_object *gobj, |
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| 416 | unsigned long size, |
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| 417 | bool kernel, |
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| 418 | uint32_t domain, |
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| 419 | bool interruptible, |
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| 420 | struct radeon_object **robj_ptr) |
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| 421 | { |
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| 422 | struct radeon_object *robj; |
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| 423 | enum ttm_bo_type type; |
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| 424 | uint32_t flags; |
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| 425 | int r; |
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| 426 | |||
| 427 | // if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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| 428 | // rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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| 429 | // } |
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| 430 | if (kernel) { |
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| 431 | type = ttm_bo_type_kernel; |
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| 432 | } else { |
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| 433 | type = ttm_bo_type_device; |
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| 434 | } |
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| 435 | *robj_ptr = NULL; |
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| 436 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 437 | if (robj == NULL) { |
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| 438 | return -ENOMEM; |
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| 439 | } |
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| 440 | robj->rdev = rdev; |
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| 441 | robj->gobj = gobj; |
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| 442 | // INIT_LIST_HEAD(&robj->list); |
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| 443 | |||
| 444 | flags = radeon_object_flags_from_domain(domain); |
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| 445 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 446 | // 0, 0, false, NULL, size, |
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| 447 | // &radeon_ttm_object_object_destroy); |
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| 448 | if (unlikely(r != 0)) { |
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| 449 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 450 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 451 | size, flags, 0); |
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| 452 | return r; |
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| 453 | } |
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| 454 | *robj_ptr = robj; |
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| 455 | // if (gobj) { |
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| 456 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 457 | // } |
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| 458 | return 0; |
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| 459 | } |
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| 460 | |||
| 461 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 462 | { |
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| 463 | int r; |
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| 464 | |||
| 465 | // spin_lock(&robj->tobj.lock); |
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| 466 | if (robj->kptr) { |
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| 467 | if (ptr) { |
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| 468 | *ptr = robj->kptr; |
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| 469 | } |
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| 470 | // spin_unlock(&robj->tobj.lock); |
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| 471 | return 0; |
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| 472 | } |
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| 473 | // spin_unlock(&robj->tobj.lock); |
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| 474 | r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap); |
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| 475 | if (r) { |
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| 476 | return r; |
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| 477 | } |
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| 478 | // spin_lock(&robj->tobj.lock); |
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| 479 | robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem); |
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| 480 | // spin_unlock(&robj->tobj.lock); |
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| 481 | if (ptr) { |
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| 482 | *ptr = robj->kptr; |
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| 483 | } |
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| 484 | return 0; |
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| 485 | } |
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| 486 | |||
| 487 | void radeon_object_kunmap(struct radeon_object *robj) |
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| 488 | { |
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| 489 | // spin_lock(&robj->tobj.lock); |
||
| 490 | if (robj->kptr == NULL) { |
||
| 491 | // spin_unlock(&robj->tobj.lock); |
||
| 492 | return; |
||
| 493 | } |
||
| 494 | robj->kptr = NULL; |
||
| 495 | // spin_unlock(&robj->tobj.lock); |
||
| 496 | ttm_bo_kunmap(&robj->kmap); |
||
| 497 | } |
||
| 498 | |||
| 499 | void radeon_object_unref(struct radeon_object **robj) |
||
| 500 | { |
||
| 501 | struct ttm_buffer_object *tobj; |
||
| 502 | |||
| 503 | if ((*robj) == NULL) { |
||
| 504 | return; |
||
| 505 | } |
||
| 506 | tobj = &((*robj)->tobj); |
||
| 507 | ttm_bo_unref(&tobj); |
||
| 508 | if (tobj == NULL) { |
||
| 509 | *robj = NULL; |
||
| 510 | } |
||
| 511 | } |
||
| 512 | |||
| 513 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset) |
||
| 514 | { |
||
| 515 | *offset = robj->tobj.addr_space_offset; |
||
| 516 | return 0; |
||
| 517 | } |
||
| 518 | |||
| 519 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
||
| 520 | uint64_t *gpu_addr) |
||
| 521 | { |
||
| 522 | uint32_t flags; |
||
| 523 | uint32_t tmp; |
||
| 524 | int r; |
||
| 525 | |||
| 526 | flags = radeon_object_flags_from_domain(domain); |
||
| 527 | // spin_lock(&robj->tobj.lock); |
||
| 528 | if (robj->pin_count) { |
||
| 529 | robj->pin_count++; |
||
| 530 | if (gpu_addr != NULL) { |
||
| 531 | *gpu_addr = robj->gpu_addr; |
||
| 532 | } |
||
| 533 | // spin_unlock(&robj->tobj.lock); |
||
| 534 | return 0; |
||
| 535 | } |
||
| 536 | // spin_unlock(&robj->tobj.lock); |
||
| 537 | r = radeon_object_reserve(robj, false); |
||
| 538 | if (unlikely(r != 0)) { |
||
| 539 | DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
||
| 540 | return r; |
||
| 541 | } |
||
| 542 | tmp = robj->tobj.mem.placement; |
||
| 543 | ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
||
| 544 | robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
||
| 545 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 546 | robj->tobj.proposed_placement, |
||
| 547 | false, false); |
||
| 548 | radeon_object_gpu_addr(robj); |
||
| 549 | if (gpu_addr != NULL) { |
||
| 550 | *gpu_addr = robj->gpu_addr; |
||
| 551 | } |
||
| 552 | robj->pin_count = 1; |
||
| 553 | if (unlikely(r != 0)) { |
||
| 554 | DRM_ERROR("radeon: failed to pin object.\n"); |
||
| 555 | } |
||
| 556 | radeon_object_unreserve(robj); |
||
| 557 | return r; |
||
| 558 | } |
||
| 559 | |||
| 560 | void radeon_object_unpin(struct radeon_object *robj) |
||
| 561 | { |
||
| 562 | uint32_t flags; |
||
| 563 | int r; |
||
| 564 | |||
| 565 | // spin_lock(&robj->tobj.lock); |
||
| 566 | if (!robj->pin_count) { |
||
| 567 | // spin_unlock(&robj->tobj.lock); |
||
| 568 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
||
| 569 | return; |
||
| 570 | } |
||
| 571 | robj->pin_count--; |
||
| 572 | if (robj->pin_count) { |
||
| 573 | // spin_unlock(&robj->tobj.lock); |
||
| 574 | return; |
||
| 575 | } |
||
| 576 | // spin_unlock(&robj->tobj.lock); |
||
| 577 | r = radeon_object_reserve(robj, false); |
||
| 578 | if (unlikely(r != 0)) { |
||
| 579 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
||
| 580 | return; |
||
| 581 | } |
||
| 582 | flags = robj->tobj.mem.placement; |
||
| 583 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
||
| 584 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 585 | robj->tobj.proposed_placement, |
||
| 586 | false, false); |
||
| 587 | if (unlikely(r != 0)) { |
||
| 588 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
||
| 589 | } |
||
| 590 | radeon_object_unreserve(robj); |
||
| 591 | } |
||
| 592 | |||
| 593 | int radeon_object_wait(struct radeon_object *robj) |
||
| 594 | { |
||
| 595 | int r = 0; |
||
| 596 | |||
| 597 | /* FIXME: should use block reservation instead */ |
||
| 598 | r = radeon_object_reserve(robj, true); |
||
| 599 | if (unlikely(r != 0)) { |
||
| 600 | DRM_ERROR("radeon: failed to reserve object for waiting.\n"); |
||
| 601 | return r; |
||
| 602 | } |
||
| 603 | // spin_lock(&robj->tobj.lock); |
||
| 604 | if (robj->tobj.sync_obj) { |
||
| 605 | r = ttm_bo_wait(&robj->tobj, true, false, false); |
||
| 606 | } |
||
| 607 | // spin_unlock(&robj->tobj.lock); |
||
| 608 | radeon_object_unreserve(robj); |
||
| 609 | return r; |
||
| 610 | } |
||
| 611 | |||
| 612 | int radeon_object_evict_vram(struct radeon_device *rdev) |
||
| 613 | { |
||
| 614 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 615 | /* Useless to evict on IGP chips */ |
||
| 616 | return 0; |
||
| 617 | } |
||
| 618 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
||
| 619 | } |
||
| 620 | |||
| 621 | void radeon_object_force_delete(struct radeon_device *rdev) |
||
| 622 | { |
||
| 623 | struct radeon_object *robj, *n; |
||
| 624 | struct drm_gem_object *gobj; |
||
| 625 | |||
| 626 | if (list_empty(&rdev->gem.objects)) { |
||
| 627 | return; |
||
| 628 | } |
||
| 629 | DRM_ERROR("Userspace still has active objects !\n"); |
||
| 630 | list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) { |
||
| 631 | mutex_lock(&rdev->ddev->struct_mutex); |
||
| 632 | gobj = robj->gobj; |
||
| 633 | DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n", |
||
| 634 | gobj, robj, (unsigned long)gobj->size, |
||
| 635 | *((unsigned long *)&gobj->refcount)); |
||
| 636 | list_del_init(&robj->list); |
||
| 637 | radeon_object_unref(&robj); |
||
| 638 | gobj->driver_private = NULL; |
||
| 639 | drm_gem_object_unreference(gobj); |
||
| 640 | mutex_unlock(&rdev->ddev->struct_mutex); |
||
| 641 | } |
||
| 642 | } |
||
| 643 | |||
| 644 | void radeon_object_fini(struct radeon_device *rdev) |
||
| 645 | { |
||
| 646 | radeon_ttm_fini(rdev); |
||
| 647 | } |
||
| 648 | |||
| 649 | void radeon_object_list_add_object(struct radeon_object_list *lobj, |
||
| 650 | struct list_head *head) |
||
| 651 | { |
||
| 652 | if (lobj->wdomain) { |
||
| 653 | list_add(&lobj->list, head); |
||
| 654 | } else { |
||
| 655 | list_add_tail(&lobj->list, head); |
||
| 656 | } |
||
| 657 | } |
||
| 658 | |||
| 659 | int radeon_object_list_reserve(struct list_head *head) |
||
| 660 | { |
||
| 661 | struct radeon_object_list *lobj; |
||
| 662 | struct list_head *i; |
||
| 663 | int r; |
||
| 664 | |||
| 665 | list_for_each(i, head) { |
||
| 666 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 667 | if (!lobj->robj->pin_count) { |
||
| 668 | r = radeon_object_reserve(lobj->robj, true); |
||
| 669 | if (unlikely(r != 0)) { |
||
| 670 | DRM_ERROR("radeon: failed to reserve object.\n"); |
||
| 671 | return r; |
||
| 672 | } |
||
| 673 | } else { |
||
| 674 | } |
||
| 675 | } |
||
| 676 | return 0; |
||
| 677 | } |
||
| 678 | |||
| 679 | void radeon_object_list_unreserve(struct list_head *head) |
||
| 680 | { |
||
| 681 | struct radeon_object_list *lobj; |
||
| 682 | struct list_head *i; |
||
| 683 | |||
| 684 | list_for_each(i, head) { |
||
| 685 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 686 | if (!lobj->robj->pin_count) { |
||
| 687 | radeon_object_unreserve(lobj->robj); |
||
| 688 | } else { |
||
| 689 | } |
||
| 690 | } |
||
| 691 | } |
||
| 692 | |||
| 693 | int radeon_object_list_validate(struct list_head *head, void *fence) |
||
| 694 | { |
||
| 695 | struct radeon_object_list *lobj; |
||
| 696 | struct radeon_object *robj; |
||
| 697 | struct radeon_fence *old_fence = NULL; |
||
| 698 | struct list_head *i; |
||
| 699 | uint32_t flags; |
||
| 700 | int r; |
||
| 701 | |||
| 702 | r = radeon_object_list_reserve(head); |
||
| 703 | if (unlikely(r != 0)) { |
||
| 704 | radeon_object_list_unreserve(head); |
||
| 705 | return r; |
||
| 706 | } |
||
| 707 | list_for_each(i, head) { |
||
| 708 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 709 | robj = lobj->robj; |
||
| 710 | if (lobj->wdomain) { |
||
| 711 | flags = radeon_object_flags_from_domain(lobj->wdomain); |
||
| 712 | flags |= TTM_PL_FLAG_TT; |
||
| 713 | } else { |
||
| 714 | flags = radeon_object_flags_from_domain(lobj->rdomain); |
||
| 715 | flags |= TTM_PL_FLAG_TT; |
||
| 716 | flags |= TTM_PL_FLAG_VRAM; |
||
| 717 | } |
||
| 718 | if (!robj->pin_count) { |
||
| 719 | robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING; |
||
| 720 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 721 | robj->tobj.proposed_placement, |
||
| 722 | true, false); |
||
| 723 | if (unlikely(r)) { |
||
| 724 | radeon_object_list_unreserve(head); |
||
| 725 | DRM_ERROR("radeon: failed to validate.\n"); |
||
| 726 | return r; |
||
| 727 | } |
||
| 728 | radeon_object_gpu_addr(robj); |
||
| 729 | } |
||
| 730 | lobj->gpu_offset = robj->gpu_addr; |
||
| 731 | if (fence) { |
||
| 732 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; |
||
| 733 | robj->tobj.sync_obj = radeon_fence_ref(fence); |
||
| 734 | robj->tobj.sync_obj_arg = NULL; |
||
| 735 | } |
||
| 736 | if (old_fence) { |
||
| 737 | radeon_fence_unref(&old_fence); |
||
| 738 | } |
||
| 739 | } |
||
| 740 | return 0; |
||
| 741 | } |
||
| 742 | |||
| 743 | void radeon_object_list_unvalidate(struct list_head *head) |
||
| 744 | { |
||
| 745 | struct radeon_object_list *lobj; |
||
| 746 | struct radeon_fence *old_fence = NULL; |
||
| 747 | struct list_head *i; |
||
| 748 | |||
| 749 | list_for_each(i, head) { |
||
| 750 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 751 | old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj; |
||
| 752 | lobj->robj->tobj.sync_obj = NULL; |
||
| 753 | if (old_fence) { |
||
| 754 | radeon_fence_unref(&old_fence); |
||
| 755 | } |
||
| 756 | } |
||
| 757 | radeon_object_list_unreserve(head); |
||
| 758 | } |
||
| 759 | |||
| 760 | void radeon_object_list_clean(struct list_head *head) |
||
| 761 | { |
||
| 762 | radeon_object_list_unreserve(head); |
||
| 763 | } |
||
| 764 | |||
| 765 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
||
| 766 | struct vm_area_struct *vma) |
||
| 767 | { |
||
| 768 | return ttm_fbdev_mmap(vma, &robj->tobj); |
||
| 769 | } |
||
| 770 | |||
| 1128 | serge | 771 | #endif |
| 772 | |||
| 1120 | serge | 773 | unsigned long radeon_object_size(struct radeon_object *robj) |
| 774 | { |
||
| 775 | return robj->tobj.num_pages << PAGE_SHIFT; |
||
| 776 | } |
||
| 777 |